arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260

DTC is generating warnings about missing port like:
DTOVL   arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
 arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
 /fragment@5/__overlay__: graph port node name should be 'port'
...

That's why change description and add it directly to dpsub mode to contain
full description with also port.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/576630cc9696e21bef15bd1f0ca35e396adc4eca.1758529693.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2025-09-22 10:28:15 +02:00
parent 68dc66d7e0
commit 145645a9f2
4 changed files with 26 additions and 18 deletions

View File

@@ -154,11 +154,13 @@
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
ports {
out_dp: port@5 {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
};
};

View File

@@ -155,11 +155,13 @@
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
ports {
out_dp: port@5 {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
};
};

View File

@@ -3,7 +3,7 @@
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* SD level shifter:
* "A" - A01 board un-modified (NXP)
@@ -131,11 +131,13 @@
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
ports {
out_dp: port@5 {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
};
};

View File

@@ -3,7 +3,7 @@
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020 - 2022, Xilinx, Inc.
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -116,11 +116,13 @@
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
&out_dp {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
ports {
out_dp: port@5 {
dpsub_dp_out: endpoint {
remote-endpoint = <&dpcon_in>;
};
};
};
};