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Merge tag 'v2026.04-rc3' into next

Browse Source 
Prepare v2026.04-rc3
This commit is contained in:
Tom Rini
2026-02-23 13:45:55 -06:00
parent ef65b15383 4f70106bea
commit 15bd325817
45 changed files with 924 additions and 380 deletions
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13
MAINTAINERS
View File

@@ -751,7 +751,6 @@ N: stm
N: stm32
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
@@ -1147,8 +1146,7 @@ F: tools/file2include.c
F: tools/mkeficapsule.c
ENVIRONMENT
M: Joe Hershberger <joe.hershberger@ni.com>
S: Maintained
S: Orphaned
F: env/
F: include/env/
F: include/env*
@@ -1462,8 +1460,6 @@ F: drivers/mmc/
N: mmc
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
M: Jerome Forissier <jerome.forissier@arm.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
@@ -1549,8 +1545,7 @@ F: drivers/pci/pcie_dw_imx.c
F: drivers/phy/phy-imx8m-pcie.c
PCI Endpoint
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
S: Orphaned
F: drivers/pci_endpoint/
F: include/pci_ep.h
@@ -1747,8 +1742,7 @@ S: Maintained
F: drivers/rng/smccc_trng.c
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
S: Orphaned
T: git https://source.denx.de/u-boot/custodians/u-boot-spi.git
F: drivers/spi/
F: include/spi*
@@ -1762,7 +1756,6 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/spi/
SPI-NOR
M: Jagan Teki <jagan@amarulasolutions.com>
M: Vignesh R <vigneshr@ti.com>
R: Tudor Ambarus <tudor.ambarus@linaro.org>
S: Maintained

2
Makefile
View File

@@ -3,7 +3,7 @@
VERSION = 2026
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

13
arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
View File

@@ -1,20 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 16
#define DDRSS_REGION_IDX 15
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -646,8 +647,8 @@
#define DDRSS_PI_204_DATA 0x00C90100
#define DDRSS_PI_205_DATA 0x010000C9
#define DDRSS_PI_206_DATA 0x00C900C9
#define DDRSS_PI_207_DATA 0x32103200
#define DDRSS_PI_208_DATA 0x01013210
#define DDRSS_PI_207_DATA 0x321E3200
#define DDRSS_PI_208_DATA 0x0101321E
#define DDRSS_PI_209_DATA 0x0A070601
#define DDRSS_PI_210_DATA 0x0D09070D
#define DDRSS_PI_211_DATA 0x0D09070D

25
arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
* AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:49:36 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1866MHz
* Density (per channel): 8Gb
* Number of Ranks: 2
*/
*/
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 933000000
#define DDRSS_PLL_FREQUENCY_2 933000000
#define DDRSS_SDRAM_IDX 16
#define DDRSS_REGION_IDX 17
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
#define DDRSS_CTL_340_DATA 0x00000000
#define DDRSS_CTL_341_DATA 0x00000000
#define DDRSS_CTL_342_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x7FFFFFFF
#define DDRSS_CTL_344_DATA 0x00000000
#define DDRSS_CTL_345_DATA 0x00000000
#define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
#define DDRSS_CTL_357_DATA 0x00000000
#define DDRSS_CTL_358_DATA 0x00000000
#define DDRSS_CTL_359_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0x00000000
#define DDRSS_CTL_361_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0xFFFFFFFF
#define DDRSS_CTL_361_DATA 0xFFFF0000
#define DDRSS_CTL_362_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0xFFFFFFFF
#define DDRSS_CTL_364_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00000000
#define DDRSS_CTL_366_DATA 0x00000000
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00FFFFFF
#define DDRSS_CTL_366_DATA 0xFFFF00FF
#define DDRSS_CTL_367_DATA 0x0000FFFF
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
#define DDRSS_PI_216_DATA 0x01D40100
#define DDRSS_PI_217_DATA 0x010001D4
#define DDRSS_PI_218_DATA 0x01D401D4
#define DDRSS_PI_219_DATA 0x32103200
#define DDRSS_PI_220_DATA 0x01013210
#define DDRSS_PI_219_DATA 0x200B3200
#define DDRSS_PI_220_DATA 0x0101200B
#define DDRSS_PI_221_DATA 0x0A070601
#define DDRSS_PI_222_DATA 0x1C11090D
#define DDRSS_PI_223_DATA 0x1C110913

25
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
* AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:50:37 GMT+0530 (India Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 1600MHz
* Density (per channel): 16Gb
* Number of Ranks: 2
*/
*/
#define DDRSS_PLL_FHS_CNT 5
#define DDRSS_PLL_FREQUENCY_1 800000000
#define DDRSS_PLL_FREQUENCY_2 800000000
#define DDRSS_SDRAM_IDX 17
#define DDRSS_REGION_IDX 17
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -358,7 +359,7 @@
#define DDRSS_CTL_340_DATA 0x00000000
#define DDRSS_CTL_341_DATA 0x00000000
#define DDRSS_CTL_342_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x00000000
#define DDRSS_CTL_343_DATA 0x7FFFFFFF
#define DDRSS_CTL_344_DATA 0x00000000
#define DDRSS_CTL_345_DATA 0x00000000
#define DDRSS_CTL_346_DATA 0x00000000
@@ -375,14 +376,14 @@
#define DDRSS_CTL_357_DATA 0x00000000
#define DDRSS_CTL_358_DATA 0x00000000
#define DDRSS_CTL_359_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0x00000000
#define DDRSS_CTL_361_DATA 0x00000000
#define DDRSS_CTL_360_DATA 0xFFFFFFFF
#define DDRSS_CTL_361_DATA 0xFFFF0000
#define DDRSS_CTL_362_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0x00000000
#define DDRSS_CTL_363_DATA 0xFFFFFFFF
#define DDRSS_CTL_364_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00000000
#define DDRSS_CTL_366_DATA 0x00000000
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_365_DATA 0x00FFFFFF
#define DDRSS_CTL_366_DATA 0xFFFF00FF
#define DDRSS_CTL_367_DATA 0x0000FFFF
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x00000000
@@ -669,8 +670,8 @@
#define DDRSS_PI_216_DATA 0x01910100
#define DDRSS_PI_217_DATA 0x01000191
#define DDRSS_PI_218_DATA 0x01910191
#define DDRSS_PI_219_DATA 0x32103200
#define DDRSS_PI_220_DATA 0x01013210
#define DDRSS_PI_219_DATA 0x301B3200
#define DDRSS_PI_220_DATA 0x0101301B
#define DDRSS_PI_221_DATA 0x0A070601
#define DDRSS_PI_222_DATA 0x180F090D
#define DDRSS_PI_223_DATA 0x180F0911

119
arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
* AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:45:31 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 17
#define DDRSS_REGION_IDX 16
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_38_DATA 0x0000091C
#define DDRSS_CTL_39_DATA 0x18181818
#define DDRSS_CTL_40_DATA 0x0000091C
#define DDRSS_CTL_41_DATA 0x18181818
#define DDRSS_CTL_42_DATA 0x0000091C
#define DDRSS_CTL_43_DATA 0x18181818
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_56_DATA 0x07070005
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_59_DATA 0x07070005
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_62_DATA 0x03000005
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
#define DDRSS_CTL_84_DATA 0x00000000
#define DDRSS_CTL_85_DATA 0x00000000
#define DDRSS_CTL_86_DATA 0x00000000
#define DDRSS_CTL_87_DATA 0x00090009
#define DDRSS_CTL_88_DATA 0x00000009
#define DDRSS_CTL_87_DATA 0x00050005
#define DDRSS_CTL_88_DATA 0x00000005
#define DDRSS_CTL_89_DATA 0x00000000
#define DDRSS_CTL_90_DATA 0x00000000
#define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
#define DDRSS_CTL_153_DATA 0x00000000
#define DDRSS_CTL_154_DATA 0x00000000
#define DDRSS_CTL_155_DATA 0x00000000
#define DDRSS_CTL_156_DATA 0x080C0000
#define DDRSS_CTL_157_DATA 0x080C080C
#define DDRSS_CTL_156_DATA 0x08080000
#define DDRSS_CTL_157_DATA 0x08080808
#define DDRSS_CTL_158_DATA 0x08000000
#define DDRSS_CTL_159_DATA 0x00000808
#define DDRSS_CTL_160_DATA 0x000E0000
@@ -251,12 +252,12 @@
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
#define DDRSS_CTL_239_DATA 0x00001401
#define DDRSS_CTL_240_DATA 0x00001401
#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_236_DATA 0x00001400
#define DDRSS_CTL_237_DATA 0x00001400
#define DDRSS_CTL_238_DATA 0x00001400
#define DDRSS_CTL_239_DATA 0x00001400
#define DDRSS_CTL_240_DATA 0x00001400
#define DDRSS_CTL_241_DATA 0x00001400
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x0C000000
#define DDRSS_CTL_371_DATA 0x060C0606
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_370_DATA 0x08000000
#define DDRSS_CTL_371_DATA 0x06080606
#define DDRSS_CTL_372_DATA 0x06060806
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
#define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_392_DATA 0x080D0302
#define DDRSS_CTL_393_DATA 0x001E0506
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_401_DATA 0x080D0302
#define DDRSS_CTL_402_DATA 0x001E0506
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_410_DATA 0x080D0302
#define DDRSS_CTL_411_DATA 0x00000506
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
#define DDRSS_PI_167_DATA 0x0000003A
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_167_DATA 0x00000036
#define DDRSS_PI_168_DATA 0x00000036
#define DDRSS_PI_169_DATA 0x00040036
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_171_DATA 0xC8000009
#define DDRSS_PI_172_DATA 0x0000091C
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_174_DATA 0x001CC800
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_184_DATA 0x01080108
#define DDRSS_PI_185_DATA 0x00000108
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05000000
#define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x0D000000
#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_193_DATA 0x09000000
#define DDRSS_PI_194_DATA 0x06060909
#define DDRSS_PI_195_DATA 0x03030306
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
#define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
#define DDRSS_PI_218_DATA 0x001600C8
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
#define DDRSS_PI_221_DATA 0x00001701
#define DDRSS_PI_222_DATA 0x1F0F0053
#define DDRSS_PI_223_DATA 0x05000001
#define DDRSS_PI_224_DATA 0x001B0A0D
#define DDRSS_PI_224_DATA 0x00170A09
#define DDRSS_PI_225_DATA 0x1F0F0053
#define DDRSS_PI_226_DATA 0x05000001
#define DDRSS_PI_227_DATA 0x001B0A0D
#define DDRSS_PI_227_DATA 0x00170A09
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_230_DATA 0x00010A09
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_236_DATA 0x0B071818
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_241_DATA 0x0B071818
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_246_DATA 0x00001818
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
#define DDRSS_PI_256_DATA 0x02550255
#define DDRSS_PI_257_DATA 0x0C080C08
#define DDRSS_PI_258_DATA 0x00000C08
#define DDRSS_PI_257_DATA 0x08080808
#define DDRSS_PI_258_DATA 0x00000808
#define DDRSS_PI_259_DATA 0x000890B8
#define DDRSS_PI_260_DATA 0x00000000
#define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_302_DATA 0x00001400
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_310_DATA 0x00001400
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_318_DATA 0x00001400
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_326_DATA 0x00001400
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_334_DATA 0x00001400
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_342_DATA 0x00001400
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
#define DDRSS_PHY_1316_DATA 0x00000000
#define DDRSS_PHY_1317_DATA 0x00000000
#define DDRSS_PHY_1318_DATA 0x00000000
#define DDRSS_PHY_1319_DATA 0x07070001
#define DDRSS_PHY_1319_DATA 0x07030001
#define DDRSS_PHY_1320_DATA 0x00005400
#define DDRSS_PHY_1321_DATA 0x000040A2
#define DDRSS_PHY_1322_DATA 0x00024410

117
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
View File

@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
* Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
* AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32
* Fri Jan 30 2026 13:47:49 GMT+0530 (India Standard Time)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
* Number of Ranks: 1
*/
*/
#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 15
#define DDRSS_REGION_IDX 15
#define DDRSS_TOOL_VERSION "0.10.32"
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
@@ -53,12 +54,12 @@
#define DDRSS_CTL_35_DATA 0x00000000
#define DDRSS_CTL_36_DATA 0x00000000
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0400091C
#define DDRSS_CTL_39_DATA 0x1C1C1C1C
#define DDRSS_CTL_40_DATA 0x0400091C
#define DDRSS_CTL_41_DATA 0x1C1C1C1C
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_38_DATA 0x0000091C
#define DDRSS_CTL_39_DATA 0x18181818
#define DDRSS_CTL_40_DATA 0x0000091C
#define DDRSS_CTL_41_DATA 0x18181818
#define DDRSS_CTL_42_DATA 0x0000091C
#define DDRSS_CTL_43_DATA 0x18181818
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
@@ -71,13 +72,13 @@
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_56_DATA 0x07070005
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_59_DATA 0x07070005
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_62_DATA 0x03000005
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
@@ -102,8 +103,8 @@
#define DDRSS_CTL_84_DATA 0x00000000
#define DDRSS_CTL_85_DATA 0x00000000
#define DDRSS_CTL_86_DATA 0x00000000
#define DDRSS_CTL_87_DATA 0x00090009
#define DDRSS_CTL_88_DATA 0x00000009
#define DDRSS_CTL_87_DATA 0x00050005
#define DDRSS_CTL_88_DATA 0x00000005
#define DDRSS_CTL_89_DATA 0x00000000
#define DDRSS_CTL_90_DATA 0x00000000
#define DDRSS_CTL_91_DATA 0x00000000
@@ -171,8 +172,8 @@
#define DDRSS_CTL_153_DATA 0x00000000
#define DDRSS_CTL_154_DATA 0x00000000
#define DDRSS_CTL_155_DATA 0x00000000
#define DDRSS_CTL_156_DATA 0x080C0000
#define DDRSS_CTL_157_DATA 0x080C080C
#define DDRSS_CTL_156_DATA 0x08080000
#define DDRSS_CTL_157_DATA 0x08080808
#define DDRSS_CTL_158_DATA 0x00000000
#define DDRSS_CTL_159_DATA 0x07010A09
#define DDRSS_CTL_160_DATA 0x000E0A09
@@ -251,12 +252,12 @@
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
#define DDRSS_CTL_239_DATA 0x00001401
#define DDRSS_CTL_240_DATA 0x00001401
#define DDRSS_CTL_241_DATA 0x00001401
#define DDRSS_CTL_236_DATA 0x00001400
#define DDRSS_CTL_237_DATA 0x00001400
#define DDRSS_CTL_238_DATA 0x00001400
#define DDRSS_CTL_239_DATA 0x00001400
#define DDRSS_CTL_240_DATA 0x00001400
#define DDRSS_CTL_241_DATA 0x00001400
#define DDRSS_CTL_242_DATA 0x00000493
#define DDRSS_CTL_243_DATA 0x00000493
#define DDRSS_CTL_244_DATA 0x00000493
@@ -385,9 +386,9 @@
#define DDRSS_CTL_367_DATA 0x00000000
#define DDRSS_CTL_368_DATA 0x00000000
#define DDRSS_CTL_369_DATA 0x00000000
#define DDRSS_CTL_370_DATA 0x0C000000
#define DDRSS_CTL_371_DATA 0x060C0606
#define DDRSS_CTL_372_DATA 0x06060C06
#define DDRSS_CTL_370_DATA 0x08000000
#define DDRSS_CTL_371_DATA 0x06080606
#define DDRSS_CTL_372_DATA 0x06060806
#define DDRSS_CTL_373_DATA 0x00010101
#define DDRSS_CTL_374_DATA 0x02000000
#define DDRSS_CTL_375_DATA 0x05020101
@@ -407,8 +408,8 @@
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_392_DATA 0x080D0302
#define DDRSS_CTL_393_DATA 0x001E0506
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
@@ -416,8 +417,8 @@
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_401_DATA 0x080D0302
#define DDRSS_CTL_402_DATA 0x001E0506
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,8 +426,8 @@
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_410_DATA 0x080D0302
#define DDRSS_CTL_411_DATA 0x00000506
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -605,14 +606,14 @@
#define DDRSS_PI_164_DATA 0x00007800
#define DDRSS_PI_165_DATA 0x00780078
#define DDRSS_PI_166_DATA 0x00141414
#define DDRSS_PI_167_DATA 0x0000003A
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_167_DATA 0x00000036
#define DDRSS_PI_168_DATA 0x00000036
#define DDRSS_PI_169_DATA 0x00040036
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_171_DATA 0xC8000009
#define DDRSS_PI_172_DATA 0x0000091C
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_174_DATA 0x001CC800
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_177_DATA 0x00000118
@@ -622,8 +623,8 @@
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
#define DDRSS_PI_184_DATA 0x010C010C
#define DDRSS_PI_185_DATA 0x0000010C
#define DDRSS_PI_184_DATA 0x01080108
#define DDRSS_PI_185_DATA 0x00000108
#define DDRSS_PI_186_DATA 0x00000000
#define DDRSS_PI_187_DATA 0x05000000
#define DDRSS_PI_188_DATA 0x01010505
@@ -631,9 +632,9 @@
#define DDRSS_PI_190_DATA 0x00181818
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x0D000000
#define DDRSS_PI_194_DATA 0x0A0A0D0D
#define DDRSS_PI_195_DATA 0x0303030A
#define DDRSS_PI_193_DATA 0x09000000
#define DDRSS_PI_194_DATA 0x06060909
#define DDRSS_PI_195_DATA 0x03030306
#define DDRSS_PI_196_DATA 0x00000000
#define DDRSS_PI_197_DATA 0x00000000
#define DDRSS_PI_198_DATA 0x00000000
@@ -659,32 +660,32 @@
#define DDRSS_PI_218_DATA 0x001600C8
#define DDRSS_PI_219_DATA 0x001600C8
#define DDRSS_PI_220_DATA 0x010100C8
#define DDRSS_PI_221_DATA 0x00001B01
#define DDRSS_PI_221_DATA 0x00001701
#define DDRSS_PI_222_DATA 0x1F0F0053
#define DDRSS_PI_223_DATA 0x05000001
#define DDRSS_PI_224_DATA 0x001B0A0D
#define DDRSS_PI_224_DATA 0x00170A09
#define DDRSS_PI_225_DATA 0x1F0F0053
#define DDRSS_PI_226_DATA 0x05000001
#define DDRSS_PI_227_DATA 0x001B0A0D
#define DDRSS_PI_227_DATA 0x00170A09
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_230_DATA 0x00010A09
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_236_DATA 0x0B071818
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_241_DATA 0x0B071818
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_246_DATA 0x00001818
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
@@ -695,8 +696,8 @@
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
#define DDRSS_PI_256_DATA 0x02550255
#define DDRSS_PI_257_DATA 0x0C080C08
#define DDRSS_PI_258_DATA 0x00000C08
#define DDRSS_PI_257_DATA 0x08080808
#define DDRSS_PI_258_DATA 0x00000808
#define DDRSS_PI_259_DATA 0x000890B8
#define DDRSS_PI_260_DATA 0x00000000
#define DDRSS_PI_261_DATA 0x00000000
@@ -740,7 +741,7 @@
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_302_DATA 0x00001400
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
@@ -748,7 +749,7 @@
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_310_DATA 0x00001400
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
@@ -756,7 +757,7 @@
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_318_DATA 0x00001400
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
@@ -764,7 +765,7 @@
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_326_DATA 0x00001400
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
@@ -772,7 +773,7 @@
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_334_DATA 0x00001400
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
@@ -780,7 +781,7 @@
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_342_DATA 0x00001400
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
#define DDRSS_PHY_0_DATA 0x04C00000
@@ -2102,7 +2103,7 @@
#define DDRSS_PHY_1316_DATA 0x00000000
#define DDRSS_PHY_1317_DATA 0x00000000
#define DDRSS_PHY_1318_DATA 0x00000000
#define DDRSS_PHY_1319_DATA 0x07070001
#define DDRSS_PHY_1319_DATA 0x07030001
#define DDRSS_PHY_1320_DATA 0x00005400
#define DDRSS_PHY_1321_DATA 0x000040A2
#define DDRSS_PHY_1322_DATA 0x00024410

197
arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi
View File

@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10
* Wed Dec 15 2021 14:35:01 GMT-0800 (Pacific Standard Time)
* AM64x SysConfig DDR Subsystem Register Configuration Tool v0.09.05
* Fri Feb 03 2023 11:04:00 GMT+0100 (Mitteleuropäische Normalzeit)
* DDR Type: DDR4
* Frequency = 800MHz (1600MTs)
* Density: 16Gb
@@ -13,6 +13,7 @@
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_CTL_0_DATA 0x00000A00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
@@ -58,39 +59,39 @@
#define DDRSS_CTL_42_DATA 0x0400091C
#define DDRSS_CTL_43_DATA 0x1C1C1C1C
#define DDRSS_CTL_44_DATA 0x05050404
#define DDRSS_CTL_45_DATA 0x00002806
#define DDRSS_CTL_45_DATA 0x00002706
#define DDRSS_CTL_46_DATA 0x0602001D
#define DDRSS_CTL_47_DATA 0x05001D0C
#define DDRSS_CTL_48_DATA 0x00280605
#define DDRSS_CTL_47_DATA 0x05001D0B
#define DDRSS_CTL_48_DATA 0x00270605
#define DDRSS_CTL_49_DATA 0x0602001D
#define DDRSS_CTL_50_DATA 0x05001D0C
#define DDRSS_CTL_51_DATA 0x00280605
#define DDRSS_CTL_50_DATA 0x05001D0B
#define DDRSS_CTL_51_DATA 0x00270605
#define DDRSS_CTL_52_DATA 0x0602001D
#define DDRSS_CTL_53_DATA 0x07001D0C
#define DDRSS_CTL_53_DATA 0x07001D0B
#define DDRSS_CTL_54_DATA 0x00180807
#define DDRSS_CTL_55_DATA 0x0400DB60
#define DDRSS_CTL_55_DATA 0x04006DB0
#define DDRSS_CTL_56_DATA 0x07070009
#define DDRSS_CTL_57_DATA 0x00001808
#define DDRSS_CTL_58_DATA 0x0400DB60
#define DDRSS_CTL_58_DATA 0x04006DB0
#define DDRSS_CTL_59_DATA 0x07070009
#define DDRSS_CTL_60_DATA 0x00001808
#define DDRSS_CTL_61_DATA 0x0400DB60
#define DDRSS_CTL_61_DATA 0x04006DB0
#define DDRSS_CTL_62_DATA 0x03000009
#define DDRSS_CTL_63_DATA 0x0D0D0002
#define DDRSS_CTL_64_DATA 0x0D0D0D0D
#define DDRSS_CTL_63_DATA 0x0D0C0002
#define DDRSS_CTL_64_DATA 0x0D0C0D0C
#define DDRSS_CTL_65_DATA 0x01010000
#define DDRSS_CTL_66_DATA 0x031A1A1A
#define DDRSS_CTL_67_DATA 0x0C0C0C0C
#define DDRSS_CTL_68_DATA 0x00000C0C
#define DDRSS_CTL_66_DATA 0x03191919
#define DDRSS_CTL_67_DATA 0x0B0B0B0B
#define DDRSS_CTL_68_DATA 0x00000B0B
#define DDRSS_CTL_69_DATA 0x00000101
#define DDRSS_CTL_70_DATA 0x00000000
#define DDRSS_CTL_71_DATA 0x01000000
#define DDRSS_CTL_72_DATA 0x01180803
#define DDRSS_CTL_73_DATA 0x00001860
#define DDRSS_CTL_73_DATA 0x00000C30
#define DDRSS_CTL_74_DATA 0x00000118
#define DDRSS_CTL_75_DATA 0x00001860
#define DDRSS_CTL_75_DATA 0x00000C30
#define DDRSS_CTL_76_DATA 0x00000118
#define DDRSS_CTL_77_DATA 0x00001860
#define DDRSS_CTL_77_DATA 0x00000C30
#define DDRSS_CTL_78_DATA 0x00000005
#define DDRSS_CTL_79_DATA 0x00000000
#define DDRSS_CTL_80_DATA 0x00000000
@@ -132,27 +133,27 @@
#define DDRSS_CTL_116_DATA 0x00040003
#define DDRSS_CTL_117_DATA 0x00040005
#define DDRSS_CTL_118_DATA 0x00000000
#define DDRSS_CTL_119_DATA 0x00061800
#define DDRSS_CTL_120_DATA 0x00061800
#define DDRSS_CTL_121_DATA 0x00061800
#define DDRSS_CTL_122_DATA 0x00061800
#define DDRSS_CTL_123_DATA 0x00061800
#define DDRSS_CTL_119_DATA 0x00030C00
#define DDRSS_CTL_120_DATA 0x00030C00
#define DDRSS_CTL_121_DATA 0x00030C00
#define DDRSS_CTL_122_DATA 0x00030C00
#define DDRSS_CTL_123_DATA 0x00030C00
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x0000AAA0
#define DDRSS_CTL_126_DATA 0x00061800
#define DDRSS_CTL_127_DATA 0x00061800
#define DDRSS_CTL_128_DATA 0x00061800
#define DDRSS_CTL_129_DATA 0x00061800
#define DDRSS_CTL_130_DATA 0x00061800
#define DDRSS_CTL_125_DATA 0x00005550
#define DDRSS_CTL_126_DATA 0x00030C00
#define DDRSS_CTL_127_DATA 0x00030C00
#define DDRSS_CTL_128_DATA 0x00030C00
#define DDRSS_CTL_129_DATA 0x00030C00
#define DDRSS_CTL_130_DATA 0x00030C00
#define DDRSS_CTL_131_DATA 0x00000000
#define DDRSS_CTL_132_DATA 0x0000AAA0
#define DDRSS_CTL_133_DATA 0x00061800
#define DDRSS_CTL_134_DATA 0x00061800
#define DDRSS_CTL_135_DATA 0x00061800
#define DDRSS_CTL_136_DATA 0x00061800
#define DDRSS_CTL_137_DATA 0x00061800
#define DDRSS_CTL_132_DATA 0x00005550
#define DDRSS_CTL_133_DATA 0x00030C00
#define DDRSS_CTL_134_DATA 0x00030C00
#define DDRSS_CTL_135_DATA 0x00030C00
#define DDRSS_CTL_136_DATA 0x00030C00
#define DDRSS_CTL_137_DATA 0x00030C00
#define DDRSS_CTL_138_DATA 0x00000000
#define DDRSS_CTL_139_DATA 0x0000AAA0
#define DDRSS_CTL_139_DATA 0x00005550
#define DDRSS_CTL_140_DATA 0x00000000
#define DDRSS_CTL_141_DATA 0x00000000
#define DDRSS_CTL_142_DATA 0x00000000
@@ -178,7 +179,7 @@
#define DDRSS_CTL_162_DATA 0x0E0A0907
#define DDRSS_CTL_163_DATA 0x0A090000
#define DDRSS_CTL_164_DATA 0x0A090701
#define DDRSS_CTL_165_DATA 0x0000000E
#define DDRSS_CTL_165_DATA 0x0000080E
#define DDRSS_CTL_166_DATA 0x00040003
#define DDRSS_CTL_167_DATA 0x00000007
#define DDRSS_CTL_168_DATA 0x00000000
@@ -219,22 +220,22 @@
#define DDRSS_CTL_203_DATA 0x00000000
#define DDRSS_CTL_204_DATA 0x00042400
#define DDRSS_CTL_205_DATA 0x00000301
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_206_DATA 0x000000C0
#define DDRSS_CTL_207_DATA 0x00000424
#define DDRSS_CTL_208_DATA 0x00000301
#define DDRSS_CTL_209_DATA 0x00000000
#define DDRSS_CTL_209_DATA 0x000000C0
#define DDRSS_CTL_210_DATA 0x00000424
#define DDRSS_CTL_211_DATA 0x00000301
#define DDRSS_CTL_212_DATA 0x00000000
#define DDRSS_CTL_212_DATA 0x000000C0
#define DDRSS_CTL_213_DATA 0x00000424
#define DDRSS_CTL_214_DATA 0x00000301
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_215_DATA 0x000000C0
#define DDRSS_CTL_216_DATA 0x00000424
#define DDRSS_CTL_217_DATA 0x00000301
#define DDRSS_CTL_218_DATA 0x00000000
#define DDRSS_CTL_218_DATA 0x000000C0
#define DDRSS_CTL_219_DATA 0x00000424
#define DDRSS_CTL_220_DATA 0x00000301
#define DDRSS_CTL_221_DATA 0x00000000
#define DDRSS_CTL_221_DATA 0x000000C0
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000000
@@ -243,12 +244,12 @@
#define DDRSS_CTL_227_DATA 0x00000000
#define DDRSS_CTL_228_DATA 0x00000000
#define DDRSS_CTL_229_DATA 0x00000000
#define DDRSS_CTL_230_DATA 0x00000000
#define DDRSS_CTL_231_DATA 0x00000000
#define DDRSS_CTL_232_DATA 0x00000000
#define DDRSS_CTL_233_DATA 0x00000000
#define DDRSS_CTL_234_DATA 0x00000000
#define DDRSS_CTL_235_DATA 0x00000000
#define DDRSS_CTL_230_DATA 0x0000000C
#define DDRSS_CTL_231_DATA 0x0000000C
#define DDRSS_CTL_232_DATA 0x0000000C
#define DDRSS_CTL_233_DATA 0x0000000C
#define DDRSS_CTL_234_DATA 0x0000000C
#define DDRSS_CTL_235_DATA 0x0000000C
#define DDRSS_CTL_236_DATA 0x00001401
#define DDRSS_CTL_237_DATA 0x00001401
#define DDRSS_CTL_238_DATA 0x00001401
@@ -334,7 +335,7 @@
#define DDRSS_CTL_318_DATA 0x3FFF0000
#define DDRSS_CTL_319_DATA 0x000FFF00
#define DDRSS_CTL_320_DATA 0xFFFFFFFF
#define DDRSS_CTL_321_DATA 0x000FFF00
#define DDRSS_CTL_321_DATA 0x00FFFF00
#define DDRSS_CTL_322_DATA 0x0A000000
#define DDRSS_CTL_323_DATA 0x0001FFFF
#define DDRSS_CTL_324_DATA 0x01010101
@@ -343,7 +344,7 @@
#define DDRSS_CTL_327_DATA 0x00000C01
#define DDRSS_CTL_328_DATA 0x00000000
#define DDRSS_CTL_329_DATA 0x00000000
#define DDRSS_CTL_330_DATA 0x01000000
#define DDRSS_CTL_330_DATA 0x00000000
#define DDRSS_CTL_331_DATA 0x01000000
#define DDRSS_CTL_332_DATA 0x00000100
#define DDRSS_CTL_333_DATA 0x00010000
@@ -398,31 +399,31 @@
#define DDRSS_CTL_382_DATA 0x00000000
#define DDRSS_CTL_383_DATA 0x04000100
#define DDRSS_CTL_384_DATA 0x1E000004
#define DDRSS_CTL_385_DATA 0x000030C0
#define DDRSS_CTL_385_DATA 0x00001860
#define DDRSS_CTL_386_DATA 0x00000200
#define DDRSS_CTL_387_DATA 0x00000200
#define DDRSS_CTL_388_DATA 0x00000200
#define DDRSS_CTL_389_DATA 0x00000200
#define DDRSS_CTL_390_DATA 0x0000DB60
#define DDRSS_CTL_391_DATA 0x0001E780
#define DDRSS_CTL_390_DATA 0x00006DB0
#define DDRSS_CTL_391_DATA 0x0000F3C0
#define DDRSS_CTL_392_DATA 0x0C0D0302
#define DDRSS_CTL_393_DATA 0x001E090A
#define DDRSS_CTL_394_DATA 0x000030C0
#define DDRSS_CTL_394_DATA 0x00001860
#define DDRSS_CTL_395_DATA 0x00000200
#define DDRSS_CTL_396_DATA 0x00000200
#define DDRSS_CTL_397_DATA 0x00000200
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x0000DB60
#define DDRSS_CTL_400_DATA 0x0001E780
#define DDRSS_CTL_399_DATA 0x00006DB0
#define DDRSS_CTL_400_DATA 0x0000F3C0
#define DDRSS_CTL_401_DATA 0x0C0D0302
#define DDRSS_CTL_402_DATA 0x001E090A
#define DDRSS_CTL_403_DATA 0x000030C0
#define DDRSS_CTL_403_DATA 0x00001860
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x0000DB60
#define DDRSS_CTL_409_DATA 0x0001E780
#define DDRSS_CTL_408_DATA 0x00006DB0
#define DDRSS_CTL_409_DATA 0x0000F3C0
#define DDRSS_CTL_410_DATA 0x0C0D0302
#define DDRSS_CTL_411_DATA 0x0000090A
#define DDRSS_CTL_412_DATA 0x00000000
@@ -607,16 +608,16 @@
#define DDRSS_PI_168_DATA 0x0000003A
#define DDRSS_PI_169_DATA 0x0004003A
#define DDRSS_PI_170_DATA 0x04000400
#define DDRSS_PI_171_DATA 0x68040009
#define DDRSS_PI_171_DATA 0xC8040009
#define DDRSS_PI_172_DATA 0x0400091C
#define DDRSS_PI_173_DATA 0x00091C68
#define DDRSS_PI_174_DATA 0x001C6804
#define DDRSS_PI_173_DATA 0x00091CC8
#define DDRSS_PI_174_DATA 0x001CC804
#define DDRSS_PI_175_DATA 0x00000118
#define DDRSS_PI_176_DATA 0x00001860
#define DDRSS_PI_176_DATA 0x00000C30
#define DDRSS_PI_177_DATA 0x00000118
#define DDRSS_PI_178_DATA 0x00001860
#define DDRSS_PI_178_DATA 0x00000C30
#define DDRSS_PI_179_DATA 0x00000118
#define DDRSS_PI_180_DATA 0x04001860
#define DDRSS_PI_180_DATA 0x04000C30
#define DDRSS_PI_181_DATA 0x01010404
#define DDRSS_PI_182_DATA 0x00001901
#define DDRSS_PI_183_DATA 0x00190019
@@ -667,28 +668,28 @@
#define DDRSS_PI_228_DATA 0x1F0F0053
#define DDRSS_PI_229_DATA 0x05000001
#define DDRSS_PI_230_DATA 0x00010A0D
#define DDRSS_PI_231_DATA 0x0D0C0700
#define DDRSS_PI_231_DATA 0x0C0B0700
#define DDRSS_PI_232_DATA 0x000D0605
#define DDRSS_PI_233_DATA 0x0000C570
#define DDRSS_PI_233_DATA 0x000062B8
#define DDRSS_PI_234_DATA 0x0000001D
#define DDRSS_PI_235_DATA 0x180A0800
#define DDRSS_PI_236_DATA 0x0C071C1C
#define DDRSS_PI_237_DATA 0x0D06050D
#define DDRSS_PI_238_DATA 0x0000C570
#define DDRSS_PI_236_DATA 0x0B071C1C
#define DDRSS_PI_237_DATA 0x0D06050C
#define DDRSS_PI_238_DATA 0x000062B8
#define DDRSS_PI_239_DATA 0x0000001D
#define DDRSS_PI_240_DATA 0x180A0800
#define DDRSS_PI_241_DATA 0x0C071C1C
#define DDRSS_PI_242_DATA 0x0D06050D
#define DDRSS_PI_243_DATA 0x0000C570
#define DDRSS_PI_241_DATA 0x0B071C1C
#define DDRSS_PI_242_DATA 0x0D06050C
#define DDRSS_PI_243_DATA 0x000062B8
#define DDRSS_PI_244_DATA 0x0000001D
#define DDRSS_PI_245_DATA 0x180A0800
#define DDRSS_PI_246_DATA 0x00001C1C
#define DDRSS_PI_247_DATA 0x000030C0
#define DDRSS_PI_248_DATA 0x0001E780
#define DDRSS_PI_249_DATA 0x000030C0
#define DDRSS_PI_250_DATA 0x0001E780
#define DDRSS_PI_251_DATA 0x000030C0
#define DDRSS_PI_252_DATA 0x0001E780
#define DDRSS_PI_247_DATA 0x00001860
#define DDRSS_PI_248_DATA 0x0000F3C0
#define DDRSS_PI_249_DATA 0x00001860
#define DDRSS_PI_250_DATA 0x0000F3C0
#define DDRSS_PI_251_DATA 0x00001860
#define DDRSS_PI_252_DATA 0x0000F3C0
#define DDRSS_PI_253_DATA 0x02550255
#define DDRSS_PI_254_DATA 0x03030255
#define DDRSS_PI_255_DATA 0x00025503
@@ -735,49 +736,49 @@
#define DDRSS_PI_296_DATA 0x00000000
#define DDRSS_PI_297_DATA 0x00000424
#define DDRSS_PI_298_DATA 0x00000301
#define DDRSS_PI_299_DATA 0x00000000
#define DDRSS_PI_299_DATA 0x000000C0
#define DDRSS_PI_300_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_301_DATA 0x0000000C
#define DDRSS_PI_302_DATA 0x00001401
#define DDRSS_PI_303_DATA 0x00000493
#define DDRSS_PI_304_DATA 0x00000000
#define DDRSS_PI_305_DATA 0x00000424
#define DDRSS_PI_306_DATA 0x00000301
#define DDRSS_PI_307_DATA 0x00000000
#define DDRSS_PI_307_DATA 0x000000C0
#define DDRSS_PI_308_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_309_DATA 0x0000000C
#define DDRSS_PI_310_DATA 0x00001401
#define DDRSS_PI_311_DATA 0x00000493
#define DDRSS_PI_312_DATA 0x00000000
#define DDRSS_PI_313_DATA 0x00000424
#define DDRSS_PI_314_DATA 0x00000301
#define DDRSS_PI_315_DATA 0x00000000
#define DDRSS_PI_315_DATA 0x000000C0
#define DDRSS_PI_316_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_317_DATA 0x0000000C
#define DDRSS_PI_318_DATA 0x00001401
#define DDRSS_PI_319_DATA 0x00000493
#define DDRSS_PI_320_DATA 0x00000000
#define DDRSS_PI_321_DATA 0x00000424
#define DDRSS_PI_322_DATA 0x00000301
#define DDRSS_PI_323_DATA 0x00000000
#define DDRSS_PI_323_DATA 0x000000C0
#define DDRSS_PI_324_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_325_DATA 0x0000000C
#define DDRSS_PI_326_DATA 0x00001401
#define DDRSS_PI_327_DATA 0x00000493
#define DDRSS_PI_328_DATA 0x00000000
#define DDRSS_PI_329_DATA 0x00000424
#define DDRSS_PI_330_DATA 0x00000301
#define DDRSS_PI_331_DATA 0x00000000
#define DDRSS_PI_331_DATA 0x000000C0
#define DDRSS_PI_332_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_333_DATA 0x0000000C
#define DDRSS_PI_334_DATA 0x00001401
#define DDRSS_PI_335_DATA 0x00000493
#define DDRSS_PI_336_DATA 0x00000000
#define DDRSS_PI_337_DATA 0x00000424
#define DDRSS_PI_338_DATA 0x00000301
#define DDRSS_PI_339_DATA 0x00000000
#define DDRSS_PI_339_DATA 0x000000C0
#define DDRSS_PI_340_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_341_DATA 0x0000000C
#define DDRSS_PI_342_DATA 0x00001401
#define DDRSS_PI_343_DATA 0x00000493
#define DDRSS_PI_344_DATA 0x00000000
@@ -901,7 +902,7 @@
#define DDRSS_PHY_117_DATA 0x00800080
#define DDRSS_PHY_118_DATA 0x00800080
#define DDRSS_PHY_119_DATA 0x01000080
#define DDRSS_PHY_120_DATA 0x01A00000
#define DDRSS_PHY_120_DATA 0x01000000
#define DDRSS_PHY_121_DATA 0x00000000
#define DDRSS_PHY_122_DATA 0x00000000
#define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1158,7 @@
#define DDRSS_PHY_373_DATA 0x00800080
#define DDRSS_PHY_374_DATA 0x00800080
#define DDRSS_PHY_375_DATA 0x01000080
#define DDRSS_PHY_376_DATA 0x01A00000
#define DDRSS_PHY_376_DATA 0x01000000
#define DDRSS_PHY_377_DATA 0x00000000
#define DDRSS_PHY_378_DATA 0x00000000
#define DDRSS_PHY_379_DATA 0x00080200
@@ -2115,7 +2116,7 @@
#define DDRSS_PHY_1331_DATA 0x00004410
#define DDRSS_PHY_1332_DATA 0x00000000
#define DDRSS_PHY_1333_DATA 0x00000046
#define DDRSS_PHY_1334_DATA 0x00010000
#define DDRSS_PHY_1334_DATA 0x00000400
#define DDRSS_PHY_1335_DATA 0x00000008
#define DDRSS_PHY_1336_DATA 0x00000000
#define DDRSS_PHY_1337_DATA 0x00000000
@@ -2152,7 +2153,7 @@
#define DDRSS_PHY_1368_DATA 0x00000002
#define DDRSS_PHY_1369_DATA 0x00000100
#define DDRSS_PHY_1370_DATA 0x00000000
#define DDRSS_PHY_1371_DATA 0x0001F7C0
#define DDRSS_PHY_1371_DATA 0x00000FC3
#define DDRSS_PHY_1372_DATA 0x00020002
#define DDRSS_PHY_1373_DATA 0x00000000
#define DDRSS_PHY_1374_DATA 0x00001142
@@ -2186,4 +2187,4 @@
#define DDRSS_PHY_1402_DATA 0x01990000
#define DDRSS_PHY_1403_DATA 0x300D3F11
#define DDRSS_PHY_1404_DATA 0x01990000
#define DDRSS_PHY_1405_DATA 0x20040001
#define DDRSS_PHY_1405_DATA 0x20040004

10
arch/arm/mach-k3/r5/j722s/clk-data.c
View File

@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -159,6 +159,7 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
@@ -223,6 +224,8 @@ static const struct clk_data clk_list[] = {
CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};
@@ -307,6 +310,11 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
DEV_CLK(107, 0, "wkup_clksel_out0"),
DEV_CLK(107, 1, "hsdiv3_16fft_main_15_hsdivout0_clk"),
DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
DEV_CLK(107, 3, "board_0_wkup_i2c0_scl_out"),
DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),

3
arch/arm/mach-k3/r5/j722s/dev-data.c
View File

@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
* Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -42,6 +42,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(16, &soc_lpsc_list[0]),
PSC_DEV(77, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(107, &soc_lpsc_list[0]),
PSC_DEV(178, &soc_lpsc_list[1]),
PSC_DEV(179, &soc_lpsc_list[2]),
PSC_DEV(57, &soc_lpsc_list[3]),

7
arch/sandbox/dts/test.dts
View File

@@ -1272,6 +1272,13 @@
filename = "mmc8.img";
};
/* This is used for zip/unzip/gzwrite tests. */
mmc9 {
status = "disabled";
compatible = "sandbox,mmc";
filename = "mmc9.img";
};
pch {
compatible = "sandbox,pch";
};

2
arch/x86/cpu/coreboot/sdram.c
View File

@@ -42,6 +42,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
continue;
/* Filter memory over 4GB. */
if (start > 0xffffffffULL)
continue;
if (end > 0xffffffffULL)
end = 0x100000000ULL;
/* Skip this region if it's too small. */

2
board/ti/am64x/evm.c
View File

@@ -136,7 +136,7 @@ static struct ti_fdt_map ti_am64_evm_fdt_map[] = {
static void setup_board_eeprom_env(void)
{
char *name = "am64x_gpevm";
char *name = NULL;
if (do_board_detect())
goto invalid_eeprom;

1
board/ti/j7200/j7200.env
View File

@@ -26,7 +26,6 @@ bootdir=/boot
rd_spec=-
#if CONFIG_TARGET_J7200_A72_EVM
do_main_cpsw0_qsgmii_phyinit=1
init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
gpio clear gpio@22_16
main_cpsw0_qsgmii_phyinit=

18
board/ti/j721e/evm.c
View File

@@ -363,7 +363,7 @@ static struct ti_fdt_map ti_j721e_evm_fdt_map[] = {
};
static void setup_board_eeprom_env(void)
{
char *name = "j721e";
char *name = NULL;
if (do_board_detect())
goto invalid_eeprom;
@@ -403,6 +403,19 @@ static void setup_serial(void)
env_set("serial#", serial_string);
}
static void qsgmii_daughtercard_env_update(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
if (!strcmp(ext_cards[i].card_name, "J7X-VSC8514-ETH") &&
daughter_card_detect_flags[i]) {
env_set("do_main_cpsw0_qsgmii_phyinit", "1");
return;
}
}
}
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -412,6 +425,9 @@ int board_late_init(void)
/* Check for and probe any plugged-in daughtercards */
if (board_is_j721e_som() || board_is_j7200_som())
probe_daughtercards();
/* Update env for power-on-reset of the QSGMII Daughtercard */
qsgmii_daughtercard_env_update();
}
return 0;

3
board/ti/j721e/j721e.env
View File

@@ -29,9 +29,6 @@ rd_spec=-
init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
gpio clear gpio@22_16
main_cpsw0_qsgmii_phyinit=
if test $board_name = J721EX-PM1-SOM || test $board_name = J721EX-PM2-SOM || test $board_name = j721e; then
do_main_cpsw0_qsgmii_phyinit=1; else
do_main_cpsw0_qsgmii_phyinit=0; fi;
if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then
run init_main_cpsw0_qsgmii_phy; \
fi;

2
board/ti/j721s2/evm.c
View File

@@ -103,7 +103,7 @@ static struct ti_fdt_map ti_j721s2_evm_fdt_map[] = {
static void setup_board_eeprom_env(void)
{
char *name = "j721s2";
char *name = NULL;
if (do_board_detect())
goto invalid_eeprom;

3
boot/bootmeth_rauc.c
View File

@@ -97,6 +97,7 @@ static int distro_rauc_scan_parts(struct bootflow *bflow)
{
struct blk_desc *desc;
struct distro_rauc_priv *priv;
struct disk_partition fs_info;
char *boot_order;
const char **boot_order_list;
bool slot_found = false;
@@ -123,7 +124,7 @@ static int distro_rauc_scan_parts(struct bootflow *bflow)
if (ret)
continue;
fs_close();
ret = part_get_info(desc, slot->root_part, NULL);
ret = part_get_info(desc, slot->root_part, &fs_info);
if (ret)
continue;
slot_found = true;

165
boot/image-fit.c
View File

@@ -2368,6 +2368,71 @@ int boot_get_setup_fit(struct bootm_headers *images, uint8_t arch,
}
#ifndef USE_HOSTCC
#ifdef CONFIG_OF_LIBFDT_OVERLAY
static int boot_get_fdt_fit_into_buffer(const void *src, ulong srclen,
ulong extra, ulong min_dstlen,
void **fdtdstbuf, ulong *fdtdstlenp)
{
const void *fdtsrcbuf;
void *tmp = NULL;
void *dstbuf, *newdstbuf = NULL;
ulong dstlen, newdstlen;
int err = 0;
/* Make sure the source FDT/DTO is 8-byte aligned for libfdt. */
fdtsrcbuf = src;
if (!IS_ALIGNED((uintptr_t)src, 8)) {
tmp = memalign(8, srclen);
if (!tmp)
return -ENOMEM;
memcpy(tmp, src, srclen);
fdtsrcbuf = tmp;
}
newdstlen = ALIGN(fdt_totalsize(fdtsrcbuf) + extra, SZ_4K);
min_dstlen = ALIGN(min_dstlen, SZ_4K);
if (newdstlen < min_dstlen)
newdstlen = min_dstlen;
dstbuf = *fdtdstbuf;
dstlen = dstbuf ? *fdtdstlenp : 0;
/*
* If the caller already provided a large enough writable buffer,
* and we're not moving the FDT, nothing to do.
*/
if (dstlen >= newdstlen && dstbuf == fdtsrcbuf)
goto out;
/* Try to reuse existing destination buffer if it is large enough. */
if (dstbuf && dstlen >= newdstlen) {
err = fdt_open_into(fdtsrcbuf, dstbuf, dstlen);
goto out;
}
newdstbuf = memalign(8, newdstlen);
if (!newdstbuf) {
err = -ENOMEM;
goto out;
}
err = fdt_open_into(fdtsrcbuf, newdstbuf, newdstlen);
if (err < 0)
goto out;
free(dstbuf);
*fdtdstbuf = newdstbuf;
*fdtdstlenp = newdstlen;
newdstbuf = NULL;
out:
free(newdstbuf);
free(tmp);
return err;
}
#endif
int boot_get_fdt_fit(struct bootm_headers *images, ulong addr,
const char **fit_unamep, const char **fit_uname_configp,
int arch, ulong *datap, ulong *lenp)
@@ -2380,18 +2445,12 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr,
char *next_config = NULL;
ulong load, len;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
ulong ovload, ovlen, ovcopylen;
ulong ovload, ovlen, ovcopylen, need;
const char *uconfig;
const char *uname;
/*
* of_flat_tree is storing the void * returned by map_sysmem, then its
* address is passed to boot_relocate_fdt which expects a char ** and it
* is then cast into a ulong. Setting its type to void * would require
* to cast its address to char ** when passing it to boot_relocate_fdt.
* Instead, let's be lazy and use void *.
*/
char *of_flat_tree;
void *base, *ov, *ovcopy = NULL;
void *ovcopy = NULL;
void *base_buf = NULL;
ulong base_buf_size = 0;
int i, err, noffset, ov_noffset;
#endif
@@ -2434,18 +2493,31 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr,
/* we need to apply overlays */
#ifdef CONFIG_OF_LIBFDT_OVERLAY
/* Relocate FDT so resizing does not overwrite other data in FIT. */
of_flat_tree = map_sysmem(load, len);
len = ALIGN(fdt_totalsize(load), SZ_4K);
err = boot_relocate_fdt(&of_flat_tree, &len);
if (err) {
printf("Required FDT relocation for applying DTOs failed: %d\n",
err);
fdt_noffset = -EBADF;
/*
* Make a writable copy of the base FDT for applying overlays.
*
* Do not use boot_relocate_fdt() here: it allocates from the bootm map and
* may overlap with the FIT buffer (still needed to load the kernel /
* ramdisk) when the FIT is loaded into RAM.
*/
err = boot_get_fdt_fit_into_buffer(map_sysmem(load, len), len,
CONFIG_SYS_FDT_PAD, 0, &base_buf,
&base_buf_size);
if (err < 0) {
if (err != -ENOMEM)
printf("Required FDT copy for applying DTOs failed: %s\n",
fdt_strerror(err));
fdt_noffset = err;
goto out;
}
load = (ulong)of_flat_tree;
/*
* Track packed DTB data size (same as libfdt internal fdt_data_size_()).
* fdt_off_dt_strings() is an offset from the blob start, so this includes
* headers/reserve map/struct blocks. Do not use fdt_totalsize() here since
* it includes free space and would overestimate growth requirements.
*/
len = fdt_off_dt_strings(base_buf) + fdt_size_dt_strings(base_buf);
/* apply extra configs in FIT first, followed by args */
for (i = 1; ; i++) {
@@ -2489,48 +2561,61 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr,
}
debug("%s loaded at 0x%08lx len=0x%08lx\n",
uname, ovload, ovlen);
ov = map_sysmem(ovload, ovlen);
ovcopylen = ALIGN(fdt_totalsize(ov), SZ_4K);
ovcopy = malloc(ovcopylen);
if (!ovcopy) {
printf("failed to duplicate DTO before application\n");
fdt_noffset = -ENOMEM;
goto out;
}
err = fdt_open_into(ov, ovcopy, ovcopylen);
err = boot_get_fdt_fit_into_buffer(map_sysmem(ovload, ovlen),
ovlen, 0, 0, &ovcopy,
&ovcopylen);
if (err < 0) {
printf("failed on fdt_open_into for DTO: %s\n",
fdt_strerror(err));
if (err != -ENOMEM)
printf("failed on fdt_open_into for DTO: %s\n",
fdt_strerror(err));
fdt_noffset = err;
goto out;
}
base = map_sysmem(load, len + ovlen);
err = fdt_open_into(base, base, len + ovlen);
/*
* Ensure the base FDT buffer is open and has enough room for
* the overlay. Grow it on demand.
*/
need = len + ovcopylen + CONFIG_SYS_FDT_PAD;
err = boot_get_fdt_fit_into_buffer(base_buf, base_buf_size, 0,
need, &base_buf,
&base_buf_size);
if (err < 0) {
printf("failed on fdt_open_into: %s\n",
fdt_strerror(err));
if (err != -ENOMEM)
printf("failed to expand FDT for DTO application: %s\n",
fdt_strerror(err));
fdt_noffset = err;
goto out;
}
/* the verbose method prints out messages on error */
err = fdt_overlay_apply_verbose(base, ovcopy);
err = fdt_overlay_apply_verbose(base_buf, ovcopy);
if (err < 0) {
fdt_noffset = err;
goto out;
}
fdt_pack(base);
len = fdt_totalsize(base);
len = fdt_off_dt_strings(base_buf) + fdt_size_dt_strings(base_buf);
free(ovcopy);
ovcopy = NULL;
}
err = fdt_pack(base_buf);
if (err < 0) {
fdt_noffset = err;
goto out;
}
len = fdt_totalsize(base_buf);
#else
printf("config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set\n");
fdt_noffset = -EBADF;
#endif
out:
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (fdt_noffset >= 0 && base_buf)
load = map_to_sysmem(base_buf);
#endif
if (datap)
*datap = load;
if (lenp)
@@ -2541,6 +2626,8 @@ out:
*fit_uname_configp = fit_uname_config;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (fdt_noffset < 0)
free(base_buf);
free(ovcopy);
#endif
free(fit_uname_config_copy);

2
boot/pxe_utils.c
View File

@@ -1083,7 +1083,7 @@ static void eol_or_eof(char **c)
*/
/*
* Parse a string literal and store a pointer it at *dst. String literals
* Parse a string literal and store a pointer to it at *dst. String literals
* terminate at the end of the line.
*/
static int parse_sliteral(char **c, char **dst)

2
common/Kconfig
View File

@@ -26,7 +26,7 @@ config CONSOLE_RECORD_INIT_F
config CONSOLE_RECORD_OUT_SIZE
hex "Output buffer size"
depends on CONSOLE_RECORD
default 0x6000
default 0x20000
help
Set the size of the console recording output buffer. When this fills
up, no more data will be recorded until some is removed. The buffer

1
configs/sandbox64_defconfig
View File

@@ -47,6 +47,7 @@ CONFIG_LOOPW=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ZIP=y
CONFIG_CMD_BCB=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DEMO=y

1
configs/sandbox_defconfig
View File

@@ -74,6 +74,7 @@ CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEM_SEARCH=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ZIP=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_FPGA_LOADP=y

2
doc/develop/release_cycle.rst
View File

@@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on:
* U-Boot |next_ver|-rc2 was released on Mon 09 February 2026.
.. * U-Boot |next_ver|-rc3 was released on Mon 23 February 2026.
* U-Boot |next_ver|-rc3 was released on Mon 23 February 2026.
.. * U-Boot |next_ver|-rc4 was released on Mon 09 March 2026.

112
doc/usage/cmd/sm3sum.rst Normal file
View File

@@ -0,0 +1,112 @@
.. SPDX-License-Identifier: GPL-2.0-or-later
.. Copyright Nabla Software Engineering GmbH
Written by Heiko Schocher <hs@nabladev.com>
.. index::
single: sm3sum (command)
sm3sum command
==============
Synopsis
--------
::
sm3sum - compute SM3 message digest
Usage:
sm3sum address count [[*]sum]
- compute SM3 message digest [save to sum]
sm3sum -v address count [*]sum
- verify sm3sum of memory area
Description
-----------
The sm3sum command calculates the SM3 hash of data of ``count`` bytes
at address ``address``. If the ``-v`` option is passed to the command,
it compares the calculated hash with the hash found at address ``sum``.
The SM3 secure hash is calculated as specified by OSCCA GM/T
0004-2012 SM3 and described at
https://datatracker.ietf.org/doc/html/draft-sca-cfrg-sm3-02
Parameters
----------
address
address from where the sm3 hash is calculated.
Hexadecimal string, 0x prefix optional.
count
length in bytes of memory area for which the sm3 hash is calculated
Hexadecimal string, 0x prefix optional.
sum
if it starts with ``*`` the string is interpreted as an address
in hexadecimal format to which the calculated hash gets stored.
else the string is interpreted as a name for an environment variable
in which the calculated hash is stored as string.
or if ``-v`` option is passed:
address of hash with which the calculated hash gets compared.
Example
-------
create some data
::
u-boot=> mw 0x100000000 0x426f6f46 1
u-boot=> md.b 0x100000000 4
00000000: 46 6f 6f 42 FooB
and calculate the sm3sum of 4 bytes starting from address ``0x100000000``
and store it in environment variable ``hashval``
::
u-boot=> sm3sum 0x100000000 4 hashval
sm3_256 for 100000000 ... 100000003 ==> cdf49da4e33017bf2d9fe87b885d80c9a7c920be7e10ffb8c89036a1eb1503b7
u-boot=> print hashval
hashval=cdf49da4e33017bf2d9fe87b885d80c9a7c920be7e10ffb8c89036a1eb1503b7
u-boot=>
or calculate sm3sum of 4 bytes starting from address ``0x100000000`` and
store it at address ``0x110000000``
::
u-boot=> sm3sum 0x100000000 4 *0x110000000
sm3_256 for 100000000 ... 100000003 ==> cdf49da4e33017bf2d9fe87b885d80c9a7c920be7e10ffb8c89036a1eb1503b7
and now check if this hash is the expected sm3sum hash value with ``-v``
option
::
u-boot=> sm3sum -v 0x100000000 4 *0x110000000
u-boot=> echo $?
0
example with wrong hash
::
u-boot=> sm3sum -v 0x100000000 4 *0x110000004
sm3_256 for 100000000 ... 100000003 ==> cdf49da4e33017bf2d9fe87b885d80c9a7c920be7e10ffb8c89036a1eb1503b7 != e33017bf2d9fe87b885d80c9a7c920be7e10ffb8c89036a1eb1503b7ffffffff ** ERROR **
u-boot=>
Configuration
-------------
Enable the sm3sum command via Kconfig option ``CONFIG_CMD_SM3SUM``.
The ``-v`` option is separate enabled through Kconfig option
``CONFIG_SM3SUM_VERIFY``.

4
drivers/clk/Kconfig
View File

@@ -228,7 +228,7 @@ config CLK_VERSAL
depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
depends on ZYNQMP_FIRMWARE
help
This clock driver adds support for clock realted settings for
This clock driver adds support for clock related settings for
Versal platform.
config CLK_VEXPRESS_OSC
@@ -262,7 +262,7 @@ config CLK_ZYNQMP
depends on ARCH_ZYNQMP
imply ZYNQMP_FIRMWARE
help
This clock driver adds support for clock realted settings for
This clock driver adds support for clock related settings for
ZynqMP platform.
source "drivers/clk/adi/Kconfig"

2
drivers/clk/clk_zynqmp.c
View File

@@ -150,6 +150,7 @@ enum zynqmp_clk {
clk_max,
};
#if IS_ENABLED(CONFIG_CMD_CLK)
static const char * const clk_names[clk_max] = {
"iopll", "rpll", "apll", "dpll",
"vpll", "iopll_to_fpd", "rpll_to_fpd",
@@ -177,6 +178,7 @@ static const char * const clk_names[clk_max] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref",
};
#endif
static const u32 pll_src[][4] = {
{apll, 0xff, dpll, vpll}, /* acpu */

2
drivers/net/phy/mscc.c
View File

@@ -1388,7 +1388,7 @@ static int vsc8541_config(struct phy_device *phydev)
return -EINVAL;
}
/* Default RMII Clk Output to 0=OFF/1=ON */
rmii_clk_out = 0;
rmii_clk_out = 1;
retval = vsc8531_vsc8541_clk_skew_config(phydev);
if (retval != 0)

53
drivers/usb/cdns3/core.c
View File

@@ -392,6 +392,52 @@ static const struct udevice_id cdns3_ids[] = {
{ },
};
/*
* The VBUS Valid Bit in the OTG Status register can be used to determine
* the role. When VBUS Valid is set, it indicates that a USB Host is supplying
* power, so the Controller should assume the PERIPHERAL role. If it isn't set,
* it indicates the absence of a USB Host, so the Controller should assume the
* HOST role. If the OTG Status register is inaccessible, return an error.
*/
static int cdns3_get_otg_mode(struct udevice *parent, enum usb_dr_mode *mode)
{
/* Create a temporary child device for using devfdt_remap_addr_name() */
struct udevice child = {
.parent = parent,
};
struct cdns3 cdns, *cdnsp;
void __iomem *otg_regs;
dev_set_ofnode(&child, ofnode_first_subnode(dev_ofnode(parent)));
otg_regs = devfdt_remap_addr_name(&child, "otg");
if (!otg_regs) {
dev_err(parent, "failed to get otg registers for child node\n");
return -ENXIO;
}
/*
* As mentioned in drivers/usb/cdns3/drd.c, there are two versions
* of the Controller. The following logic detects the version of the
* Controller and interprets the register layout accordingly.
*/
cdnsp = &cdns;
cdnsp->otg_v0_regs = otg_regs;
if (!readl(&cdnsp->otg_v0_regs->cmd)) {
cdnsp->otg_regs = otg_regs;
} else {
cdnsp->otg_v1_regs = otg_regs;
cdnsp->otg_regs = (void *)&cdnsp->otg_v1_regs->cmd;
}
/* Use VBUS Valid to determine role */
if (readl(&cdnsp->otg_regs->sts) & OTGSTS_VBUS_VALID)
*mode = USB_DR_MODE_PERIPHERAL;
else
*mode = USB_DR_MODE_HOST;
return 0;
}
int cdns3_bind(struct udevice *parent)
{
enum usb_dr_mode dr_mode;
@@ -413,6 +459,13 @@ int cdns3_bind(struct udevice *parent)
if (dr_mode == USB_DR_MODE_UNKNOWN)
dr_mode = usb_get_dr_mode(dev_ofnode(parent));
/* Use VBUS Valid to determine role */
if (dr_mode == USB_DR_MODE_OTG) {
ret = cdns3_get_otg_mode(parent, &dr_mode);
if (ret < 0)
return ret;
}
switch (dr_mode) {
#if defined(CONFIG_SPL_USB_HOST) || \
(!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))

11
drivers/usb/cdns3/drd.c
View File

@@ -301,6 +301,17 @@ int cdns3_drd_init(struct cdns3 *cdns)
cdns->dr_mode = USB_DR_MODE_PERIPHERAL;
}
/*
* In the absence of STRAP configuration, use VBUS Valid to
* determine the appropriate role to be assigned to dr_mode.
*/
if (cdns->dr_mode == USB_DR_MODE_OTG) {
if (cdns3_get_vbus(cdns))
cdns->dr_mode = USB_DR_MODE_PERIPHERAL;
else
cdns->dr_mode = USB_DR_MODE_HOST;
}
state = readl(&cdns->otg_regs->sts);
if (OTGSTS_OTG_NRDY(state) != 0) {
dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n");

92
drivers/usb/dwc3/core.c
View File

@@ -59,40 +59,52 @@ static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
int retries = 1000;
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
/*
* We're resetting only the device side because, if we're in host mode,
* XHCI driver will reset the host block. If dwc3 was configured for
* host-only mode, then we can return early.
*/
if (dwc->dr_mode == USB_DR_MODE_HOST)
return 0;
/* Assert USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= DWC3_DCTL_CSFTRST;
reg &= ~DWC3_DCTL_RUN_STOP;
dwc3_gadget_dctl_write_safe(dwc, reg);
/* Assert USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
/*
* For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
* is cleared only after all the clocks are synchronized. This can
* take a little more than 50ms. Set the polling rate at 20ms
* for 10 times instead.
*/
if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
retries = 10;
mdelay(100);
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
goto done;
/* Clear USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
mdelay(20);
else
udelay(1);
} while (--retries);
/* Clear USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
return -ETIMEDOUT;
mdelay(100);
/* After PHYs are stable we can take Core out of reset state */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
done:
/*
* For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
* is cleared, we must wait at least 50ms before accessing the PHY
* domain (synchronization delay).
*/
if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
mdelay(50);
return 0;
}
@@ -580,6 +592,26 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
}
static bool dwc3_core_is_valid(struct dwc3 *dwc)
{
u32 reg;
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
dwc->ip = DWC3_GSNPS_ID(reg);
/* This should read as U3 followed by revision number */
if (DWC3_IP_IS(DWC3)) {
dwc->revision = reg;
} else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
} else {
return false;
}
return true;
}
/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
@@ -592,15 +624,11 @@ static int dwc3_core_init(struct dwc3 *dwc)
u32 reg;
int ret;
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
/* This should read as U3 followed by revision number */
if ((reg & DWC3_GSNPSID_MASK) != 0x55330000 &&
(reg & DWC3_GSNPSID_MASK) != 0x33310000) {
if (!dwc3_core_is_valid(dwc)) {
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
ret = -ENODEV;
goto err0;
}
dwc->revision = reg;
/* Handle USB2.0-only core configuration */
if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==

60
drivers/usb/dwc3/core.h
View File

@@ -56,6 +56,7 @@
#define DWC3_GEVNTCOUNT_MASK 0xfffc
#define DWC3_GSNPSID_MASK 0xffff0000
#define DWC3_GSNPSREV_MASK 0xffff
#define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
/* DWC3 registers memory space boundries */
#define DWC3_XHCI_REGS_START 0x0
@@ -99,6 +100,9 @@
#define DWC3_GPRTBIMAP_FS0 0xc188
#define DWC3_GPRTBIMAP_FS1 0xc18c
#define DWC3_VER_NUMBER 0xc1a0
#define DWC3_VER_TYPE 0xc1a4
#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
@@ -686,7 +690,9 @@ struct dwc3_scratchpad_array {
* @num_event_buffers: calculated number of event buffers
* @u1u2: only used on revisions <1.83a for workaround
* @maximum_speed: maximum speed requested (mainly for testing purposes)
* @ip: controller's ID
* @revision: revision register contents
* @version_type: VERSIONTYPE register contents, a sub release of a revision
* @dr_mode: requested mode of operation
* @hsphy_mode: UTMI phy mode, one of following:
* - USBPHY_INTERFACE_MODE_UTMI
@@ -795,6 +801,13 @@ struct dwc3 {
u32 num_event_buffers;
u32 u1u2;
u32 maximum_speed;
u32 ip;
#define DWC3_IP 0x5533
#define DWC31_IP 0x3331
#define DWC32_IP 0x3332
u32 revision;
#define DWC3_REVISION_173A 0x5533173a
@@ -817,6 +830,32 @@ struct dwc3 {
#define DWC3_REVISION_270A 0x5533270a
#define DWC3_REVISION_280A 0x5533280a
#define DWC3_REVISION_290A 0x5533290a
#define DWC3_REVISION_300A 0x5533300a
#define DWC3_REVISION_310A 0x5533310a
#define DWC3_REVISION_320A 0x5533320a
#define DWC3_REVISION_330A 0x5533330a
#define DWC31_REVISION_ANY 0x0
#define DWC31_REVISION_110A 0x3131302a
#define DWC31_REVISION_120A 0x3132302a
#define DWC31_REVISION_160A 0x3136302a
#define DWC31_REVISION_170A 0x3137302a
#define DWC31_REVISION_180A 0x3138302a
#define DWC31_REVISION_190A 0x3139302a
#define DWC31_REVISION_200A 0x3230302a
#define DWC32_REVISION_ANY 0x0
#define DWC32_REVISION_100A 0x3130302a
u32 version_type;
#define DWC31_VERSIONTYPE_ANY 0x0
#define DWC31_VERSIONTYPE_EA01 0x65613031
#define DWC31_VERSIONTYPE_EA02 0x65613032
#define DWC31_VERSIONTYPE_EA03 0x65613033
#define DWC31_VERSIONTYPE_EA04 0x65613034
#define DWC31_VERSIONTYPE_EA05 0x65613035
#define DWC31_VERSIONTYPE_EA06 0x65613036
enum dwc3_ep0_next ep0_next_event;
enum dwc3_ep0_state ep0state;
@@ -1062,6 +1101,27 @@ void dwc3_of_parse(struct dwc3 *dwc);
int dwc3_init(struct dwc3 *dwc);
void dwc3_remove(struct dwc3 *dwc);
#define DWC3_IP_IS(_ip) \
(dwc->ip == _ip##_IP)
#define DWC3_VER_IS(_ip, _ver) \
(DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
#define DWC3_VER_IS_PRIOR(_ip, _ver) \
(DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
#define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
(DWC3_IP_IS(_ip) && \
dwc->revision >= _ip##_REVISION_##_from && \
(!(_ip##_REVISION_##_to) || \
dwc->revision <= _ip##_REVISION_##_to))
#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
(DWC3_VER_IS(_ip, _ver) && \
dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
(!(_ip##_VERSIONTYPE_##_to) || \
dwc->version_type <= _ip##_VERSIONTYPE_##_to))
static inline int dwc3_host_init(struct dwc3 *dwc)
{ return 0; }
static inline void dwc3_host_exit(struct dwc3 *dwc)

20
drivers/usb/dwc3/gadget.c
View File

@@ -62,7 +62,7 @@ int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
return -EINVAL;
}
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
return 0;
}
@@ -1396,7 +1396,7 @@ static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
{
u32 reg;
u32 timeout = 500;
u32 timeout = 2000;
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (is_on) {
@@ -1422,9 +1422,10 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
dwc->pullups_connected = false;
}
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
do {
udelay(2000);
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
if (is_on) {
if (!(reg & DWC3_DSTS_DEVCTRLHLT))
@@ -1436,7 +1437,6 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
timeout--;
if (!timeout)
return -ETIMEDOUT;
udelay(1);
} while (1);
dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
@@ -2137,10 +2137,8 @@ static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_INITU1ENA;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
reg &= ~DWC3_DCTL_INITU2ENA;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
dwc3_disconnect_gadget(dwc);
dwc->start_config_issued = false;
@@ -2189,7 +2187,7 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
dwc->test_mode = false;
dwc3_stop_active_transfers(dwc);
@@ -2305,11 +2303,11 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
} else {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
}
dep = dwc->eps[0];
@@ -2417,7 +2415,7 @@ static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
reg &= ~u1u2;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc3_gadget_dctl_write_safe(dwc, reg);
break;
default:
/* do nothing */

14
drivers/usb/dwc3/gadget.h
View File

@@ -104,4 +104,18 @@ static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
return DWC3_DEPCMD_GET_RSC_IDX(res_id);
}
/**
* dwc3_gadget_dctl_write_safe - write to DCTL safe from link state change
* @dwc: pointer to our context structure
* @value: value to write to DCTL
*
* Use this function when doing read-modify-write to DCTL. It will not
* send link state change request.
*/
static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value)
{
value &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
dwc3_writel(dwc->regs, DWC3_DCTL, value);
}
#endif /* __DRIVERS_USB_DWC3_GADGET_H */

19
drivers/usb/gadget/dwc2_udc_otg.c
View File

@@ -975,12 +975,6 @@ static int dwc2_udc_otg_of_to_plat(struct udevice *dev)
void (*set_params)(struct dwc2_plat_otg_data *data);
int ret;
if (usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_PERIPHERAL &&
usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_OTG) {
dev_dbg(dev, "Invalid mode\n");
return -ENODEV;
}
plat->regs_otg = dev_read_addr(dev);
plat->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0);
@@ -1163,6 +1157,18 @@ static int dwc2_udc_otg_remove(struct udevice *dev)
return dm_scan_fdt_dev(dev);
}
static int dwc2_udc_otg_bind(struct udevice *dev)
{
enum usb_dr_mode dr_mode = usb_get_dr_mode(dev_ofnode(dev));
if (dr_mode != USB_DR_MODE_PERIPHERAL && dr_mode != USB_DR_MODE_OTG) {
dev_dbg(dev, "Invalid dr_mode %d\n", dr_mode);
return -ENODEV;
}
return 0;
}
static int dwc2_gadget_handle_interrupts(struct udevice *dev)
{
return dwc2_udc_handle_interrupt();
@@ -1186,6 +1192,7 @@ U_BOOT_DRIVER(dwc2_udc_otg) = {
.of_match = dwc2_udc_otg_ids,
.ops = &dwc2_gadget_ops,
.of_to_plat = dwc2_udc_otg_of_to_plat,
.bind = dwc2_udc_otg_bind,
.probe = dwc2_udc_otg_probe,
.remove = dwc2_udc_otg_remove,
.plat_auto = sizeof(struct dwc2_plat_otg_data),

5
fs/squashfs/sqfs.c
View File

@@ -178,6 +178,11 @@ static int sqfs_frag_lookup(u32 inode_fragment_index,
goto out;
}
if (SQFS_METADATA_SIZE(header) > SQFS_METADATA_BLOCK_SIZE) {
ret = -EINVAL;
goto out;
}
entries = malloc(SQFS_METADATA_BLOCK_SIZE);
if (!entries) {
ret = -ENOMEM;

4
include/configs/amd_versal2.h
View File

@@ -16,8 +16,8 @@
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xF9000000
#define GICR_BASE 0xF9060000
#define GICD_BASE 0xe2000000
#define GICR_BASE 0xe2060000
/* Serial setup */
#define CFG_SYS_BAUDRATE_TABLE \

3
include/env/ti/ti_common.env vendored
View File

@@ -22,11 +22,10 @@ get_fit_overlaystring=
done;
get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}
run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}
do_main_cpsw0_qsgmii_phyinit=0
bootcmd_ti_mmc=
run init_${boot};
#if CONFIG_CMD_REMOTEPROC
if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
if env exists do_main_cpsw0_qsgmii_phyinit;
then run main_cpsw0_qsgmii_phyinit;
fi;
run boot_rprocs;

18
lib/efi_loader/efi_conformance.c
View File

@@ -13,8 +13,6 @@
#include <malloc.h>
static const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID;
static const efi_guid_t efi_ebbr_2_1_guid =
EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID;
/**
* efi_ecpt_register() - Install the ECPT system table.
@@ -23,12 +21,17 @@ static const efi_guid_t efi_ebbr_2_1_guid =
*/
efi_status_t efi_ecpt_register(void)
{
u16 num_entries = 0;
struct efi_conformance_profiles_table *ecpt;
efi_status_t ret;
size_t ecpt_size;
ecpt_size = num_entries * sizeof(efi_guid_t)
static const efi_guid_t profiles[] = {
#if CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE)
EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID,
#endif
};
ecpt_size = sizeof(profiles)
+ sizeof(struct efi_conformance_profiles_table);
ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, ecpt_size,
(void **)&ecpt);
@@ -39,12 +42,9 @@ efi_status_t efi_ecpt_register(void)
return ret;
}
if (CONFIG_IS_ENABLED(EFI_EBBR_2_1_CONFORMANCE))
guidcpy(&ecpt->conformance_profiles[num_entries++],
&efi_ebbr_2_1_guid);
memcpy(ecpt->conformance_profiles, profiles, sizeof(profiles));
ecpt->version = EFI_CONFORMANCE_PROFILES_TABLE_VERSION;
ecpt->number_of_profiles = num_entries;
ecpt->number_of_profiles = ARRAY_SIZE(profiles);
/* Install the ECPT in the system configuration table. */
ret = efi_install_configuration_table(&efi_ecpt_guid, (void *)ecpt);

13
lib/efi_loader/efi_tcg2.c
View File

@@ -1213,8 +1213,10 @@ tcg2_measure_gpt_data(struct udevice *dev,
goto out2;
}
ret = block_io->read_blocks(block_io, block_io->media->media_id, 1,
block_io->media->block_size, gpt_h);
ret = EFI_CALL(block_io->read_blocks(block_io,
block_io->media->media_id, 1,
block_io->media->block_size,
gpt_h));
if (ret != EFI_SUCCESS)
goto out2;
@@ -1227,9 +1229,10 @@ tcg2_measure_gpt_data(struct udevice *dev,
goto out2;
}
ret = block_io->read_blocks(block_io, block_io->media->media_id,
gpt_h->partition_entry_lba,
total_gpt_entry_size, entry);
ret = EFI_CALL(block_io->read_blocks(block_io,
block_io->media->media_id,
gpt_h->partition_entry_lba,
total_gpt_entry_size, entry));
if (ret != EFI_SUCCESS)
goto out2;

2
lib/sm3.c
View File

@@ -249,7 +249,7 @@ void sm3_final(struct sm3_context *sctx, uint8_t output[SM3_DIGEST_SIZE])
sctx->buffer[partial++] = 0x80;
if (partial > bit_offset) {
memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial);
memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial - 1);
partial = 0;
sm3_block(sctx, sctx->buffer, 1, W);

3
test/cmd/Makefile
View File

@@ -45,3 +45,6 @@ endif
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
obj-$(CONFIG_CMD_SPAWN) += spawn.o
ifdef CONFIG_CMD_ZIP
obj-$(CONFIG_CMD_UNZIP) += unzip.o
endif

124
test/cmd/unzip.c Normal file
View File

@@ -0,0 +1,124 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Tests for zip/unzip/gzwrite commands
*
* Copyright 2026, Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
#include <command.h>
#include <env.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/test.h>
#include <linux/sizes.h>
#include <mapmem.h>
#include <part.h>
#include <test/cmd.h>
#include <test/test.h>
#include <test/ut.h>
#include <u-boot/crc.h>
/* sys/random.h is not accessible */
extern ssize_t getrandom(void *buf, size_t size, unsigned int flags);
static const ssize_t sizes[] = { 32, SZ_1K, SZ_4K, SZ_1M, SZ_16M, SZ_1M - 1, SZ_1M + 1, 6758401 };
static int do_test_cmd_zip_unzip(struct unit_test_state *uts, ssize_t size,
const bool gzwrite)
{
unsigned long loadaddr = env_get_ulong("loadaddr", 16, 0);
unsigned long encaddr = loadaddr + size + 0x10000;
unsigned long decaddr = encaddr + size + 0x10000;
unsigned char *loadmap = map_sysmem(loadaddr, size);
unsigned char *decmap = map_sysmem(decaddr, size);
unsigned char *encmap = map_sysmem(encaddr, size);
/*
* Prepare three buffers, $loadadd, $encaddr, $decaddr, and
* fill them all with random data. Add slight space between
* the compressed buffer 'encaddr' and uncompressed buffer
* 'decaddr', because the compressed data with gzip header
* might be longer than uncompressed source data 'loadaddr',
* and if the uncompressed data buffer 'decaddr' followed
* 'encaddr', the decompression could corrupt end of 'encaddr'
* buffer.
*/
ut_assert(getrandom(loadmap, size, 0) == size);
ut_assert(getrandom(decmap, size, 0) == size);
ut_assert(getrandom(encmap, size, 0) == size);
/* Compress data in $loadaddr into $encaddr */
ut_assertok(run_commandf("zip $loadaddr %zx %zx", size, encaddr));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_assert(strstr(uts->actual_str, "Compressed size: "));
if (gzwrite) {
unsigned int sectsize = DIV_ROUND_UP(size, 512);
u32 crc = crc32(0, loadmap, size);
struct blk_desc *mmc_dev_desc;
ut_assertok(run_commandf("gzwrite mmc 9 %zx $filesize", encaddr));
ut_assert_skip_to_line("\t%zu bytes, crc 0x%08x", size, crc);
ut_asserteq(9, blk_get_device_by_str("mmc", "9", &mmc_dev_desc));
ut_assertok(run_commandf("mmc dev 9"));
ut_assert_nextline("switch to partitions #0, OK");
ut_assert_nextline("mmc9 is current device");
ut_assertok(run_commandf("mmc read %zx 0 %x", decaddr, sectsize));
ut_assert_nextline("MMC read: dev # 9, block # 0, count %u ... %u blocks read: OK",
sectsize, sectsize);
} else {
/* Decompress data in $encaddr into $decaddr */
ut_assertok(run_commandf("unzip %zx %zx $filesize", encaddr, decaddr));
ut_assert_nextline("Uncompressed size: %zu = 0x%zX", size, size);
}
/* Input data and compressed-decompressed data */
ut_asserteq_mem(loadmap, decmap, size);
ut_assert_console_end();
unmap_sysmem(loadmap);
unmap_sysmem(decmap);
unmap_sysmem(encmap);
return 0;
}
static int dm_test_cmd_zip_unzip(struct unit_test_state *uts)
{
int i, ret;
for (i = 0; i < ARRAY_SIZE(sizes); i++) {
ret = do_test_cmd_zip_unzip(uts, sizes[i], false);
if (ret)
return ret;
}
return 0;
}
DM_TEST(dm_test_cmd_zip_unzip, UTF_CONSOLE);
static int dm_test_cmd_zip_gzwrite(struct unit_test_state *uts)
{
struct udevice *dev;
ofnode root, node;
int i, ret;
/* Enable the mmc9 node for this test */
root = oftree_root(oftree_default());
node = ofnode_find_subnode(root, "mmc9");
ut_assert(ofnode_valid(node));
ut_assertok(lists_bind_fdt(gd->dm_root, node, &dev, NULL, false));
for (i = 0; i < ARRAY_SIZE(sizes); i++) {
ret = do_test_cmd_zip_unzip(uts, sizes[i], true);
if (ret)
return ret;
}
return 0;
}
DM_TEST(dm_test_cmd_zip_gzwrite, UTF_CONSOLE);

2
test/py/conftest.py
View File

@@ -102,7 +102,7 @@ def run_build(config, source_dir, build_dir, board_type, log):
Args:
config: The pytest configuration.
soruce_dir (str): Directory containing source code
source_dir (str): Directory containing source code
build_dir (str): Directory to build in
board_type (str): board_type parameter (e.g. 'sandbox')
log (Logfile): Log file to use

6
test/py/tests/test_ut.py
View File

@@ -522,6 +522,12 @@ def test_ut_dm_init(ubman):
with open(fn, 'wb') as fh:
fh.write(data)
mmc_dev = 9
fn = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
data = b'\x00' * (32 * 1024 * 1024)
with open(fn, 'wb') as fh:
fh.write(data)
def setup_efi_image(ubman):
"""Create a 20MB disk image with an EFI app on it"""