arm64: renesas: Add Cortex-M33 build option to R-Car Gen5

The R-Car Gen5 SoCs contains Cortex-M33, Cortex-R52 and Cortex-A720AE
cores. Add U-Boot build options for the Cortex-M33 core.

Since the Cortex-M33 core is a 32bit core, select V8M and ARM64 for
RCAR64 accordingly. Select TMU timer on the 32bit core, where it is
used instead of the ARMv8 timer. Adjust TMU timer base address to match
the address map of the Cortex-M33 core. Disable unused OF_BOARD_SETUP
as well as unavailable POSITION_INDEPENDENT configuration options.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>

arch/arm/mach-renesas/Kconfig

@@ -1,15 +1,19 @@
 if ARCH_RENESAS
 
-# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
+config TMU_TIMER
+	bool
+
+# Renesas ARM SoCs R-Car Gen3/Gen4/Gen5 (64bit Cortex-A / 32bit Cortex-M/R)
 config RCAR_64
 	bool
-	select ARM64
+	select CPU_V8M if RCAR_64_RSIP
+	select ARM64 if !RCAR_64_RSIP
 	select CMD_CACHE
-	select OF_BOARD_SETUP
+	select OF_BOARD_SETUP if !RCAR_64_RSIP
 	select PHY
 	select PINCONF
 	select PINCTRL
-	select POSITION_INDEPENDENT
+	select POSITION_INDEPENDENT if !RCAR_64_RSIP
 	imply CMD_FS_UUID
 	imply CMD_GPT
 	imply CMD_MMC_SWRITE if MMC

arch/arm/mach-renesas/Kconfig.rcar5

@@ -1,5 +1,13 @@
 if RCAR_GEN5
 
+config RCAR_64_RSIP
+	bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
+	select SKIP_RELOCATE_CODE
+	select TMU_TIMER
+	help
+	  Build U-Boot for the Cortex-M33 RSIP core present on selected SoC.
+	  The default is n, meaning U-Boot is built for the Cortex-A core.
+
 menu "Select Target SoC"
 
 config R8A78000
@@ -23,4 +31,7 @@ endchoice
 
 source "board/renesas/ironhide/Kconfig"
 
+config SKIP_RELOCATE_CODE_DATA_OFFSET
+	default 0xa0000000 if RCAR_64_RSIP
+
 endif

arch/arm/mach-renesas/include/mach/rcar-gen5-base.h

@@ -9,7 +9,13 @@
 /*
  * R-Car (R8A78000) I/O Addresses
  */
+#if defined(CONFIG_RCAR_64_RSIP)
+/* Cortex-M33 address */
+#define TMU_BASE		0xC0680000
+#else
+/* Cortex-A720AE address */
 #define TMU_BASE		0x1C030000
+#endif
 
 /* Arm Generic Timer */
 #define CNTCR_BASE		0x1C000FFF /* Region 0 */

include/configs/rcar-gen5-common.h

@@ -17,6 +17,12 @@
 #define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
 #define CFG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)
 
+/* Timer */
+#if defined(CONFIG_RCAR_64_RSIP)
+#define CFG_SYS_TIMER_COUNTER		(TMU_BASE + 0xc)	/* TCNT0 */
+#define CFG_SYS_TIMER_RATE		(133333333 / 4)
+#endif
+
 /* Environment setting */
 #define CFG_EXTRA_ENV_SETTINGS		\
 	"bootm_size=0x10000000\0"