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net: ftgmac100: Fixed the cache coherency issues of rx memory

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When executing TFTP, the ARP will be replied to after receiving
the ARP. U-boot's ARP routine modifies the data in the receive
packet in response to the ARP packet and then copies it
into the transmit packet.
At this point, the received packet cache is inconsistent.
It is possible that the cache will perform a writeback action to
affect the MAC receiving packets.

Avoid the same problem that occurs in other networking protocols.
In the free_pkt function, ensure cache and memory consistency.

Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Jacky Chou
2024-06-27 14:26:00 +08:00
committed by Leo Yu-Chi Liang
parent aa4a03f2e2
commit 21d5d5e55b
1 changed files with 8 additions and 0 deletions
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8
drivers/net/ftgmac100.c
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@@ -410,6 +410,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
/*
* Make sure there are no stale data in write-back over this area, which
* might get written into the memory while the ftgmac100 also writes
* into the same memory area.
*/
flush_dcache_range((ulong)net_rx_packets[priv->rx_index],
(ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN);
/* Release buffer to DMA and flush descriptor */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
flush_dcache_range(des_start, des_end);