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clk: mediatek: mt8188: fix some clock parents

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Fix a number of clock parent definitions for MT8188 clocks.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
This commit is contained in:
Julien Stephan
2026-02-02 13:41:52 +01:00
committed by Tom Rini
parent 5e9bbbdab0
commit 2797fa3efd
1 changed files with 15 additions and 19 deletions
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34
drivers/clk/mediatek/clk-mt8188.c
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@@ -26,8 +26,6 @@
#define CLK_TOP_CLK32K 209
#define CLK_TOP_IMGPLL 210
#define CLK_TOP_MSDCPLL 211
#define CLK_TOP_ULPOSC1_CK1 212
#define CLK_TOP_ULPOSC_CK1 213
/* apmixedsys */
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
@@ -165,21 +163,21 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR1(CLK_TOP_MMPLL_D6_D2, CLK_TOP_MMPLL_D6, 1, 2),
FACTOR0(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7),
FACTOR0(CLK_TOP_MMPLL_D9, CLK_APMIXED_MMPLL, 1, 9),
FACTOR1(CLK_TOP_TVDPLL1_D2, CLK_TOP_TVDPLL1, 1, 2),
FACTOR1(CLK_TOP_TVDPLL1_D4, CLK_TOP_TVDPLL1, 1, 4),
FACTOR1(CLK_TOP_TVDPLL1_D8, CLK_TOP_TVDPLL1, 1, 8),
FACTOR1(CLK_TOP_TVDPLL1_D16, CLK_TOP_TVDPLL1, 1, 16),
FACTOR1(CLK_TOP_TVDPLL2_D2, CLK_TOP_TVDPLL2, 1, 2),
FACTOR1(CLK_TOP_TVDPLL2_D4, CLK_TOP_TVDPLL2, 1, 4),
FACTOR1(CLK_TOP_TVDPLL2_D8, CLK_TOP_TVDPLL2, 1, 8),
FACTOR1(CLK_TOP_TVDPLL2_D16, CLK_TOP_TVDPLL2, 1, 16),
FACTOR0(CLK_TOP_TVDPLL1_D2, CLK_APMIXED_TVDPLL1, 1, 2),
FACTOR0(CLK_TOP_TVDPLL1_D4, CLK_APMIXED_TVDPLL1, 1, 4),
FACTOR0(CLK_TOP_TVDPLL1_D8, CLK_APMIXED_TVDPLL1, 1, 8),
FACTOR0(CLK_TOP_TVDPLL1_D16, CLK_APMIXED_TVDPLL1, 1, 16),
FACTOR0(CLK_TOP_TVDPLL2_D2, CLK_APMIXED_TVDPLL2, 1, 2),
FACTOR0(CLK_TOP_TVDPLL2_D4, CLK_APMIXED_TVDPLL2, 1, 4),
FACTOR0(CLK_TOP_TVDPLL2_D8, CLK_APMIXED_TVDPLL2, 1, 8),
FACTOR0(CLK_TOP_TVDPLL2_D16, CLK_APMIXED_TVDPLL2, 1, 16),
FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
FACTOR0(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1, 16),
FACTOR1(CLK_TOP_ETHPLL_D2, CLK_TOP_ETHPLL, 1, 2),
FACTOR1(CLK_TOP_ETHPLL_D4, CLK_TOP_ETHPLL, 1, 4),
FACTOR1(CLK_TOP_ETHPLL_D8, CLK_TOP_ETHPLL, 1, 8),
FACTOR1(CLK_TOP_ETHPLL_D10, CLK_TOP_ETHPLL, 1, 10),
FACTOR0(CLK_TOP_ETHPLL_D2, CLK_APMIXED_ETHPLL, 1, 2),
FACTOR0(CLK_TOP_ETHPLL_D4, CLK_APMIXED_ETHPLL, 1, 4),
FACTOR0(CLK_TOP_ETHPLL_D8, CLK_APMIXED_ETHPLL, 1, 8),
FACTOR0(CLK_TOP_ETHPLL_D10, CLK_APMIXED_ETHPLL, 1, 10),
FACTOR0(CLK_TOP_ADSPPLL_D2, CLK_APMIXED_ADSPPLL, 1, 2),
FACTOR0(CLK_TOP_ADSPPLL_D4, CLK_APMIXED_ADSPPLL, 1, 4),
FACTOR0(CLK_TOP_ADSPPLL_D8, CLK_APMIXED_ADSPPLL, 1, 8),
@@ -859,7 +857,7 @@ static const int adsp_parents[] = {
CLK_TOP_UNIVPLL_D4_D4,
CLK_TOP_UNIVPLL_D4,
CLK_TOP_ULPOSC1_D2,
CLK_TOP_ULPOSC1_CK1,
CLK_TOP_ULPOSC1,
CLK_TOP_ADSPPLL,
CLK_TOP_ADSPPLL_D2,
CLK_TOP_ADSPPLL_D4,
@@ -876,7 +874,7 @@ static const int audio_local_bus_parents[] = {
CLK_TOP_MAINPLL_D7,
CLK_TOP_MAINPLL_D4,
CLK_TOP_UNIVPLL_D6,
CLK_TOP_ULPOSC1_CK1,
CLK_TOP_ULPOSC1,
CLK_TOP_ULPOSC1_D4,
CLK_TOP_ULPOSC1_D2
};
@@ -1015,7 +1013,7 @@ static const int spinor_parents[] = {
};
static const int ulposc_parents[] = {
CLK_TOP_ULPOSC_CK1,
CLK_TOP_ULPOSC1,
CLK_TOP_ETHPLL_D2,
CLK_TOP_MAINPLL_D4_D2,
CLK_TOP_ETHPLL_D10
@@ -1356,8 +1354,6 @@ static const int mt8188_id_offs_map[] = {
8, /* CLK_TOP_CLK32K */
-1, /* CLK_TOP_IMGPLL */
72, /* CLK_TOP_MSDCPLL */
-1, /* CLK_TOP_ULPOSC1_CK1 */
-1, /* CLK_TOP_ULPOSC_CK1 */
};
static const struct mtk_gate_regs top0_cg_regs = {