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rockchip: clk: clk_rk3576: Add dummy CLK_REF_PCIEx_PHY support

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Add dummy support for the CLK_REF_PCIEx_PHY clocks to allow probe of the
phy-rockchip-naneng-combphy driver on RK3576.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2025-08-01 20:43:37 +00:00
committed by Kever Yang
parent 0d966d3932
commit 2a6039a209
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk_rk3576.c
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@@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
case CLK_CPLL_DIV10:
case FCLK_DDR_CM0_CORE:
case ACLK_PHP_ROOT:
case CLK_REF_PCIE0_PHY:
case CLK_REF_PCIE1_PHY:
ret = 0;
break;
#ifndef CONFIG_SPL_BUILD