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Subtree merge tag 'v6.15-dts' of dts repo [1] into dts/upstream

Browse Source 
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2025-05-27 09:50:34 -06:00
parent 6015a24a5a a6b479b7ad
commit 2f3766949b
1087 changed files with 47739 additions and 5668 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
dts/upstream/Bindings/arm/apple.yaml
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@@ -57,6 +57,25 @@ description: |
- iPad Pro (2nd Generation) (10.5 Inch)
- iPad Pro (2nd Generation) (12.9 Inch)
Devices based on the "T2" SoC:
- Apple T2 MacBookPro15,2 (j132)
- Apple T2 iMacPro1,1 (j137)
- Apple T2 MacBookAir8,2 (j140a)
- Apple T2 MacBookAir8,1 (j140k)
- Apple T2 MacBookPro16,1 (j152f)
- Apple T2 MacPro7,1 (j160)
- Apple T2 Macmini8,1 (j174)
- Apple T2 iMac20,1 (j185)
- Apple T2 iMac20,2 (j185f)
- Apple T2 MacBookPro15,4 (j213)
- Apple T2 MacBookPro16,2 (j214k)
- Apple T2 MacBookPro16,4 (j215)
- Apple T2 MacBookPro16,3 (j223)
- Apple T2 MacBookAir9,1 (j230k)
- Apple T2 MacBookPro15,1 (j680)
- Apple T2 MacBookPro15,3 (j780)
Devices based on the "A11" SoC:
- iPhone 8
@@ -211,6 +230,28 @@ properties:
- const: apple,t8011
- const: apple,arm-platform
- description: Apple T2 SoC based platforms
items:
- enum:
- apple,j132 # Apple T2 MacBookPro15,2 (j132)
- apple,j137 # Apple T2 iMacPro1,1 (j137)
- apple,j140a # Apple T2 MacBookAir8,2 (j140a)
- apple,j140k # Apple T2 MacBookAir8,1 (j140k)
- apple,j152f # Apple T2 MacBookPro16,1 (j152f)
- apple,j160 # Apple T2 MacPro7,1 (j160)
- apple,j174 # Apple T2 Macmini8,1 (j174)
- apple,j185 # Apple T2 iMac20,1 (j185)
- apple,j185f # Apple T2 iMac20,2 (j185f)
- apple,j213 # Apple T2 MacBookPro15,4 (j213)
- apple,j214k # Apple T2 MacBookPro16,2 (j214k)
- apple,j215 # Apple T2 MacBookPro16,4 (j215)
- apple,j223 # Apple T2 MacBookPro16,3 (j223)
- apple,j230k # Apple T2 MacBookAir9,1 (j230k)
- apple,j680 # Apple T2 MacBookPro15,1 (j680)
- apple,j780 # Apple T2 MacBookPro15,3 (j780)
- const: apple,t8012
- const: apple,arm-platform
- description: Apple A11 SoC based platforms
items:
- enum:

5
dts/upstream/Bindings/arm/apple/apple,pmgr.yaml
View File

@@ -22,6 +22,11 @@ properties:
compatible:
items:
- enum:
- apple,s5l8960x-pmgr
- apple,t7000-pmgr
- apple,s8000-pmgr
- apple,t8010-pmgr
- apple,t8015-pmgr
- apple,t8103-pmgr
- apple,t8112-pmgr
- apple,t6000-pmgr

26
dts/upstream/Bindings/arm/arm,coresight-tmc.yaml
View File

@@ -101,6 +101,29 @@ properties:
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
memory-region:
items:
- description: Reserved trace buffer memory for ETR and ETF sinks.
For ETR, this reserved memory region is used for trace data capture.
Same region is used for trace data retention as well after a panic
or watchdog reset.
This reserved memory region is used as trace buffer or used for trace
data retention only if specifically selected by the user in sysfs
interface.
The default memory usage models for ETR in sysfs/perf modes are
otherwise unaltered.
For ETF, this reserved memory region is used by default for
retention of trace data synced from internal SRAM after a panic
or watchdog reset.
- description: Reserved meta data memory. Used for ETR and ETF sinks
for storing metadata.
memory-region-names:
items:
- const: tracedata
- const: metadata
required:
- compatible
- reg
@@ -115,6 +138,9 @@ examples:
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
memory-region = <&etr_trace_mem_reserved>,
<&etr_mdata_mem_reserved>;
memory-region-names = "tracedata", "metadata";
clocks = <&oscclk6a>;
clock-names = "apb_pclk";

35
dts/upstream/Bindings/arm/arm,morello.yaml Normal file
View File

@@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,morello.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Morello Platforms
maintainers:
- Vincenzo Frascino <vincenzo.frascino@arm.com>
description: |+
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
ARM's Morello Platforms are built as a research project to explore
capability architectures based on arm.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Arm Morello System Platforms
items:
- enum:
- arm,morello-sdp
- arm,morello-fvp
- const: arm,morello
additionalProperties: true
...

33
dts/upstream/Bindings/arm/atmel-at91.yaml
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@@ -22,8 +22,6 @@ properties:
- items:
- const: atmel,at91rm9200
- items:
- enum:
- olimex,sam9-l9260
- enum:
- atmel,at91sam9260
- atmel,at91sam9261
@@ -36,6 +34,37 @@ properties:
- atmel,at91sam9x60
- const: atmel,at91sam9
- description: Olimex SAM9-L9260
items:
- const: olimex,sam9-l9260
- const: atmel,at91sam9260
- const: atmel,at91sam9
- description: Calao USB A9260
items:
- const: calao,usb-a9260
- const: atmel,at91sam9260
- const: atmel,at91sam9
- description: Calao USB A9263
items:
- const: calao,usb-a9263
- const: atmel,at91sam9263
- const: atmel,at91sam9
- description: Calao USB A9G20
items:
- const: calao,usb-a9g20
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- description: Calao USB A9G20-LPW
items:
- const: calao,usb-a9g20-lpw
- const: calao,usb-a9g20
- const: atmel,at91sam9g20
- const: atmel,at91sam9
- items:
- enum:
- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board

1
dts/upstream/Bindings/arm/atmel-sysregs.txt
View File

@@ -2,6 +2,7 @@ Atmel system registers
Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
"microchip,sama7d65-chipid"
- reg : Should contain registers location and length
PIT Timer required properties:

1
dts/upstream/Bindings/arm/cpus.yaml
View File

@@ -177,6 +177,7 @@ properties:
- arm,neoverse-v2
- arm,neoverse-v3
- arm,neoverse-v3ae
- arm,rainier
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan

27
dts/upstream/Bindings/arm/fsl.yaml
View File

@@ -97,6 +97,7 @@ properties:
- i2se,duckbill
- i2se,duckbill-2
- karo,tx28 # Ka-Ro electronics TX28 module
- lwn,imx28-btt3
- lwn,imx28-xea
- msr,m28cu3 # M28 SoM with custom base board
- schulercontrol,imx28-sps1
@@ -296,7 +297,6 @@ properties:
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Modules
- udoo,imx6q-udoo # Udoo i.MX6 Quad Board
- uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
@@ -490,7 +490,6 @@ properties:
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Modules
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
@@ -688,6 +687,12 @@ properties:
- const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL
- const: fsl,imx6ul
- description: i.MX6UL Variscite VAR-SOM-MX6 Boards
items:
- const: variscite,mx6ulconcerto
- const: variscite,var-som-imx6ul
- const: fsl,imx6ul
- description: Kontron BL i.MX6UL (N631X S) Board
items:
- const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board
@@ -730,9 +735,6 @@ properties:
- joz,jozacp # JOZ Access Point
- kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
- toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules
- uni-t,uti260b # UNI-T UTi260B Thermal Camera
- const: fsl,imx6ull
@@ -891,8 +893,6 @@ properties:
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
- technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph
- technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi
- toradex,colibri-imx7d # Colibri iMX7D Module
- toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d
@@ -962,9 +962,6 @@ properties:
- innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM
- kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM
- kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
@@ -1098,12 +1095,12 @@ properties:
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
- skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate
- skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
- const: fsl,imx8mp
@@ -1273,8 +1270,6 @@ properties:
- enum:
- fsl,imx8qm-mek # i.MX8QM MEK Board
- fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board
- toradex,apalis-imx8 # Apalis iMX8 Modules
- toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
- const: fsl,imx8qm
- description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
@@ -1355,6 +1350,7 @@ properties:
- description: i.MX95 based Boards
items:
- enum:
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
- const: fsl,imx95
@@ -1435,7 +1431,6 @@ properties:
- fsl,vf610-twr # VF610 Tower Board
- lwn,bk4 # Liebherr BK4 controller
- phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board
- toradex,vf610-colibri_vf61 # Colibri VF61 Modules
- const: fsl,vf610
- description: Toradex Colibri VF61 Module on Colibri Evaluation Board

3
dts/upstream/Bindings/arm/google.yaml
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@@ -34,10 +34,11 @@ properties:
const: '/'
compatible:
oneOf:
- description: Google Pixel 6 / Oriole
- description: Google Pixel 6 or 6 Pro (Oriole or Raven)
items:
- enum:
- google,gs101-oriole
- google,gs101-raven
- const: google,gs101
# Bootloader requires empty ect node to be present

1
dts/upstream/Bindings/arm/marvell/armada-37xx.yaml
View File

@@ -18,6 +18,7 @@ properties:
items:
- enum:
- cznic,turris-mox
- glinet,gl-mv1000
- globalscale,espressobin
- marvell,armada-3720-db
- methode,edpu

25
dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
View File

@@ -23,6 +23,9 @@ properties:
- description: Armada 7040 SoC
items:
- enum:
- globalscale,mochabin
- marvell,armada7040-db
- const: marvell,armada7040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
@@ -35,10 +38,32 @@ properties:
- description: Armada 8040 SoC
items:
- enum:
- iei,puzzle-m801
- marvell,armada8040-db
- solidrun,clearfog-gt-8k
- const: marvell,armada8040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada 8040 SoC MACCHIATOBin Boards
items:
- enum:
- marvell,armada8040-mcbin-doubleshot
- marvell,armada8040-mcbin-singleshot
- const: marvell,armada8040-mcbin
- const: marvell,armada8040
- const: marvell,armada-ap806-quad
- const: marvell,armada-ap806
- description: Armada 8080 SoC
items:
- enum:
- marvell,armada-8080-db
- const: marvell,armada-8080
- const: marvell,armada-ap810-octa
- const: marvell,armada-ap810
- description: Armada CN9130 SoC with no external CP
items:
- const: marvell,cn9130

15
dts/upstream/Bindings/arm/marvell/armada-8kp.txt
View File

@@ -1,15 +0,0 @@
Marvell Armada 8KPlus Platforms Device Tree Bindings
----------------------------------------------------
Boards using a SoC of the Marvell Armada 8KP families must carry
the following root node property:
- compatible, with one of the following values:
- "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
when the SoC being used is the Armada 8080
Example:
compatible = "marvell,armada-8080-db", "marvell,armada-8080",
"marvell,armada-ap810-octa", "marvell,armada-ap810"

5
dts/upstream/Bindings/arm/mediatek.yaml
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@@ -412,6 +412,11 @@ properties:
- enum:
- mediatek,mt8365-evk
- const: mediatek,mt8365
- items:
- enum:
- mediatek,mt8370-evk
- const: mediatek,mt8370
- const: mediatek,mt8188
- items:
- enum:
- mediatek,mt8390-evk

1
dts/upstream/Bindings/arm/pmu.yaml
View File

@@ -67,6 +67,7 @@ properties:
- arm,neoverse-v2-pmu
- arm,neoverse-v3-pmu
- arm,neoverse-v3ae-pmu
- arm,rainier-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
- nvidia,denver-pmu

84
dts/upstream/Bindings/arm/qcom,coresight-ctcu.yaml Normal file
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@@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight TMC Control Unit
maintainers:
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Jie Gan <quic_jiegan@quicinc.com>
description: |
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.
The configuration mode (ETB, ETF, ETR) is discovered at boot time when
the device is probed.
The Coresight TMC Control unit controls various Coresight behaviors.
It works as a helper device when connected to TMC ETR device.
It is responsible for controlling the data filter function based on
the source device's Trace ID for TMC ETR device. The trace data with
that Trace id can get into ETR's buffer while other trace data gets
ignored.
properties:
compatible:
enum:
- qcom,sa8775p-ctcu
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: apb
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
patternProperties:
'^port(@[0-1])?$':
description: Input connections from CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- in-ports
additionalProperties: false
examples:
- |
ctcu@1001000 {
compatible = "qcom,sa8775p-ctcu";
reg = <0x1001000 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ctcu_in_port0: endpoint {
remote-endpoint = <&etr0_out_port>;
};
};
port@1 {
reg = <1>;
ctcu_in_port1: endpoint {
remote-endpoint = <&etr1_out_port>;
};
};
};
};

3
dts/upstream/Bindings/arm/qcom,coresight-tpda.yaml
View File

@@ -55,8 +55,7 @@ properties:
- const: arm,primecell
reg:
minItems: 1
maxItems: 2
maxItems: 1
clocks:
maxItems: 1

3
dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
View File

@@ -41,8 +41,7 @@ properties:
- const: arm,primecell
reg:
minItems: 1
maxItems: 2
maxItems: 1
qcom,dsb-element-bits:
description:

20
dts/upstream/Bindings/arm/rockchip.yaml
View File

@@ -49,6 +49,11 @@ properties:
- anbernic,rg-arc-s
- const: rockchip,rk3566
- description: Ariaboard Photonicat
items:
- const: ariaboard,photonicat
- const: rockchip,rk3568
- description: ArmSoM Sige5 board
items:
- const: armsom,sige5
@@ -178,6 +183,13 @@ properties:
- const: engicam,px30-core
- const: rockchip,px30
- description: Firefly iCore-3588Q-based boards
items:
- enum:
- mntre,reform2-rcore
- const: firefly,icore-3588q
- const: rockchip,rk3588
- description: Firefly Core-3588J-based boards
items:
- enum:
@@ -867,6 +879,11 @@ properties:
- const: radxa,rock-4c-plus
- const: rockchip,rk3399
- description: Radxa ROCK 4D
items:
- const: radxa,rock-4d
- const: rockchip,rk3576
- description: Radxa ROCK 4SE
items:
- const: radxa,rock-4se
@@ -1141,11 +1158,12 @@ properties:
- const: xunlong,orangepi-3b
- const: rockchip,rk3566
- description: Xunlong Orange Pi 5 Max/Plus
- description: Xunlong Orange Pi 5 Max/Plus/Ultra
items:
- enum:
- xunlong,orangepi-5-max
- xunlong,orangepi-5-plus
- xunlong,orangepi-5-ultra
- const: rockchip,rk3588
- description: Xunlong Orange Pi R1 Plus / LTS

2
dts/upstream/Bindings/arm/stm32/st,stm32-syscon.yaml
View File

@@ -21,6 +21,8 @@ properties:
- st,stm32f4-gcan
- st,stm32mp151-pwr-mcu
- st,stm32mp157-syscfg
- st,stm32mp21-syscfg
- st,stm32mp23-syscfg
- st,stm32mp25-syscfg
- const: syscon
- items:

22
dts/upstream/Bindings/arm/stm32/stm32.yaml
View File

@@ -51,9 +51,16 @@ properties:
- st,stm32mp135f-dk
- const: st,stm32mp135
- description: ST STM32MP133 based Boards
items:
- enum:
- pri,prihmb # Priva E-Measuringbox board
- const: st,stm32mp133
- description: ST STM32MP151 based Boards
items:
- enum:
- ply,plyaqm # Plymovent AQM board
- prt,mecio1r0 # Protonic MECIO1r0
- prt,mect1s # Protonic MECT1S
- prt,prtt1a # Protonic PRTT1A
@@ -94,6 +101,8 @@ properties:
- description: Octavo OSD32MP153 System-in-Package based boards
items:
- enum:
- lxa,stm32mp153c-fairytux2-gen1 # Linux Automation FairyTux 2 (Generation 1)
- lxa,stm32mp153c-fairytux2-gen2 # Linux Automation FairyTux 2 (Generation 2)
- lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3)
- const: oct,stm32mp153x-osd32
- const: st,stm32mp153
@@ -178,9 +187,22 @@ properties:
- description: ST STM32MP257 based Boards
items:
- enum:
- st,stm32mp257f-dk
- st,stm32mp257f-ev1
- const: st,stm32mp257
- description: ST STM32MP235 based Boards
items:
- enum:
- st,stm32mp235f-dk
- const: st,stm32mp235
- description: ST STM32MP215 based Boards
items:
- enum:
- st,stm32mp215f-dk
- const: st,stm32mp215
additionalProperties: true
...

5
dts/upstream/Bindings/arm/sunxi.yaml
View File

@@ -589,6 +589,11 @@ properties:
- const: emlid,neutis-n5h3
- const: allwinner,sun8i-h3
- description: NetCube Systems Kumquat
items:
- const: netcube,kumquat
- const: allwinner,sun8i-v3s
- description: NextThing Co. CHIP
items:
- const: nextthing,chip

7
dts/upstream/Bindings/arm/ti/omap.yaml
View File

@@ -141,6 +141,13 @@ properties:
- const: ti,omap4430
- const: ti,omap4
- description: OMAP4 PandaBoard Revision A4 and later
items:
- const: ti,omap4-panda-a4
- const: ti,omap4-panda
- const: ti,omap4430
- const: ti,omap4
- description: OMAP4 DuoVero with Parlor expansion board/daughter board
items:
- const: gumstix,omap4-duovero-parlor

5
dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml
View File

@@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
@@ -163,11 +162,9 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
#include <dt-bindings/phy/phy.h>
sata: ahci@fd0c0000 {
@@ -175,7 +172,7 @@ examples:
reg = <0xfd0c0000 0x200>;
interrupt-parent = <&gic>;
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk SATA_REF>;
clocks = <&zynqmp_clk 22>;
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;

60
dts/upstream/Bindings/ata/fsl,pq-sata.yaml Normal file
View File

@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale 8xxx/3.0 Gb/s SATA nodes
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,mpc8377-sata
- fsl,mpc8536-sata
- fsl,mpc8315-sata
- fsl,mpc8379-sata
- const: fsl,pq-sata
- const: fsl,pq-sata-v2
reg:
maxItems: 1
interrupts:
maxItems: 1
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
description: |
1 for controller @ 0x18000
2 for controller @ 0x19000
3 for controller @ 0x1a000
4 for controller @ 0x1b000
required:
- compatible
- interrupts
- cell-index
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
sata@18000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
};
...

28
dts/upstream/Bindings/ata/fsl-sata.txt
View File

@@ -1,28 +0,0 @@
* Freescale 8xxx/3.0 Gb/s SATA nodes
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA port should have its own node.
Required properties:
- compatible : compatible list, contains 2 entries, first is
"fsl,CHIP-sata", where CHIP is the processor
(mpc8315, mpc8379, etc.) and the second is
"fsl,pq-sata"
- interrupts : <interrupt mapping for SATA IRQ>
- cell-index : controller index.
1 for controller @ 0x18000
2 for controller @ 0x19000
3 for controller @ 0x1a000
4 for controller @ 0x1b000
Optional properties:
- reg : <registers mapping>
Example:
sata@18000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
cell-index = <1>;
interrupts = <2c 8>;
interrupt-parent = < &ipic >;
};

103
dts/upstream/Bindings/clock/allwinner,sun55i-a523-ccu.yaml Normal file
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@@ -0,0 +1,103 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A523 Clock Control Unit
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
"#clock-cells":
const: 1
"#reset-cells":
const: 1
compatible:
enum:
- allwinner,sun55i-a523-ccu
- allwinner,sun55i-a523-r-ccu
reg:
maxItems: 1
clocks:
minItems: 4
maxItems: 5
clock-names:
minItems: 4
maxItems: 5
required:
- "#clock-cells"
- "#reset-cells"
- compatible
- reg
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
enum:
- allwinner,sun55i-a523-ccu
then:
properties:
clocks:
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Low Frequency Oscillator fanout
clock-names:
items:
- const: hosc
- const: losc
- const: iosc
- const: losc-fanout
- if:
properties:
compatible:
enum:
- allwinner,sun55i-a523-r-ccu
then:
properties:
clocks:
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
- description: Internal Oscillator
- description: Peripherals PLL
- description: Audio PLL
clock-names:
items:
- const: hosc
- const: losc
- const: iosc
- const: pll-periph
- const: pll-audio
additionalProperties: false
examples:
- |
clock-controller@2001000 {
compatible = "allwinner,sun55i-a523-ccu";
reg = <0x02001000 0x1000>;
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>;
clock-names = "hosc", "losc", "iosc", "losc-fanout";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

4
dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
View File

@@ -34,6 +34,8 @@ properties:
- enum:
- atmel,at91rm9200-pmc
- atmel,at91sam9260-pmc
- atmel,at91sam9261-pmc
- atmel,at91sam9263-pmc
- atmel,at91sam9g45-pmc
- atmel,at91sam9n12-pmc
- atmel,at91sam9rl-pmc
@@ -111,6 +113,8 @@ allOf:
enum:
- atmel,at91rm9200-pmc
- atmel,at91sam9260-pmc
- atmel,at91sam9261-pmc
- atmel,at91sam9263-pmc
- atmel,at91sam9g20-pmc
then:
properties:

8
dts/upstream/Bindings/clock/imx8m-clock.yaml
View File

@@ -43,6 +43,13 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
for the full list of i.MX8M clock IDs.
fsl,operating-mode:
$ref: /schemas/types.yaml#/definitions/string
enum: [nominal, overdrive]
description:
The operating mode of the SoC. This affects the maximum clock rates that
can safely be configured by the clock controller.
required:
- compatible
- reg
@@ -109,6 +116,7 @@ examples:
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
fsl,operating-mode = "nominal";
};
- |

10
dts/upstream/Bindings/clock/imx8mp-audiomix.yaml
View File

@@ -24,8 +24,8 @@ properties:
maxItems: 1
clocks:
minItems: 7
maxItems: 7
minItems: 8
maxItems: 8
clock-names:
items:
@@ -36,6 +36,7 @@ properties:
- const: sai5
- const: sai6
- const: sai7
- const: axi
'#clock-cells':
const: 1
@@ -72,10 +73,11 @@ examples:
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
<&clk IMX8MP_CLK_SAI7>;
<&clk IMX8MP_CLK_SAI7>,
<&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
"sai5", "sai6", "sai7", "axi";
power-domains = <&pgc_audio>;
};

21
dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml
View File

@@ -57,6 +57,27 @@ required:
- reg
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8188-camsys-rawa
- mediatek,mt8188-camsys-rawb
- mediatek,mt8188-camsys-yuva
- mediatek,mt8188-camsys-yuvb
- mediatek,mt8188-imgsys-wpe1
- mediatek,mt8188-imgsys-wpe2
- mediatek,mt8188-imgsys-wpe3
- mediatek,mt8188-imgsys1-dip-nr
- mediatek,mt8188-imgsys1-dip-top
- mediatek,mt8188-ipesys
then:
required:
- '#reset-cells'
additionalProperties: false
examples:

11
dts/upstream/Bindings/clock/mediatek,mtmips-sysc.yaml
View File

@@ -18,6 +18,12 @@ description: |
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifiers could be found in:
[1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.
properties:
compatible:
items:
@@ -38,7 +44,8 @@ properties:
'#clock-cells':
description:
The first cell indicates the clock number.
The first cell indicates the clock number, see [1] for available
clocks.
const: 1
'#reset-cells':
@@ -56,6 +63,8 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;

98
dts/upstream/Bindings/clock/qcom,ipq9574-nsscc.yaml Normal file
View File

@@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Anusha Rao <quic_anusha@quicinc.com>
description: |
Qualcomm networking sub system clock control module provides the clocks,
resets on IPQ9574
See also::
include/dt-bindings/clock/qcom,ipq9574-nsscc.h
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
properties:
compatible:
const: qcom,ipq9574-nsscc
clocks:
items:
- description: Board XO source
- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
- description: GCC GPLL0 OUT AUX clock source
- description: Uniphy0 NSS Rx clock source
- description: Uniphy0 NSS Tx clock source
- description: Uniphy1 NSS Rx clock source
- description: Uniphy1 NSS Tx clock source
- description: Uniphy2 NSS Rx clock source
- description: Uniphy2 NSS Tx clock source
- description: GCC NSSCC clock source
'#interconnect-cells':
const: 1
clock-names:
items:
- const: xo
- const: nss_1200
- const: ppe_353
- const: gpll0_out
- const: uniphy0_rx
- const: uniphy0_tx
- const: uniphy1_rx
- const: uniphy1_tx
- const: uniphy2_rx
- const: uniphy2_tx
- const: bus
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
clock-controller@39b00000 {
compatible = "qcom,ipq9574-nsscc";
reg = <0x39b00000 0x80000>;
clocks = <&xo_board_clk>,
<&cmn_pll NSS_1200MHZ_CLK>,
<&cmn_pll PPE_353MHZ_CLK>,
<&gcc GPLL0_OUT_AUX>,
<&uniphy 0>,
<&uniphy 1>,
<&uniphy 2>,
<&uniphy 3>,
<&uniphy 4>,
<&uniphy 5>,
<&gcc GCC_NSSCC_CLK>;
clock-names = "xo",
"nss_1200",
"ppe_353",
"gpll0_out",
"uniphy0_rx",
"uniphy0_tx",
"uniphy1_rx",
"uniphy1_tx",
"uniphy2_rx",
"uniphy2_tx",
"bus";
#clock-cells = <1>;
#reset-cells = <1>;
};
...

2
dts/upstream/Bindings/clock/qcom,rpmcc.yaml
View File

@@ -44,6 +44,7 @@ properties:
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
@@ -123,6 +124,7 @@ allOf:
- qcom,rpmcc-msm8998
- qcom,rpmcc-qcm2290
- qcom,rpmcc-qcs404
- qcom,rpmcc-sdm429
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125

5
dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
View File

@@ -20,6 +20,7 @@ description: |
properties:
compatible:
enum:
- qcom,qcm6490-lpassaudiocc
- qcom,sc7280-lpassaoncc
- qcom,sc7280-lpassaudiocc
- qcom,sc7280-lpasscorecc
@@ -68,7 +69,9 @@ allOf:
properties:
compatible:
contains:
const: qcom,sc7280-lpassaudiocc
enum:
- qcom,qcm6490-lpassaudiocc
- qcom,sc7280-lpassaudiocc
then:
properties:

1
dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
View File

@@ -64,7 +64,6 @@ allOf:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
then:
required:
- required-opps

9
dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
View File

@@ -40,9 +40,9 @@ properties:
- description: A phandle to the MMCX power-domain
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing MMCX performance points.
items:
- description: A phandle to an OPP node describing MXC performance points
- description: A phandle to an OPP node describing MMCX performance points
required:
- compatible
@@ -66,7 +66,8 @@ examples:
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

55
dts/upstream/Bindings/clock/rockchip,rk3562-cru.yaml Normal file
View File

@@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip rk3562 Clock and Reset Control Module
maintainers:
- Elaine Zhang <zhangqing@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description:
The RK3562 clock controller generates the clock and also implements a reset
controller for SoC peripherals. For example it provides SCLK_UART2 and
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
module.
properties:
compatible:
const: rockchip,rk3562-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
maxItems: 2
clock-names:
items:
- const: xin24m
- const: xin32k
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@ff100000 {
compatible = "rockchip,rk3562-cru";
reg = <0xff100000 0x40000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

247
dts/upstream/Bindings/clock/samsung,exynos2200-cmu.yaml Normal file
View File

@@ -0,0 +1,247 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos2200 SoC clock controller
maintainers:
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Exynos2200 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clocks in that root tree
are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be
defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header.
properties:
compatible:
enum:
- samsung,exynos2200-cmu-alive
- samsung,exynos2200-cmu-cmgp
- samsung,exynos2200-cmu-hsi0
- samsung,exynos2200-cmu-peric0
- samsung,exynos2200-cmu-peric1
- samsung,exynos2200-cmu-peric2
- samsung,exynos2200-cmu-peris
- samsung,exynos2200-cmu-top
- samsung,exynos2200-cmu-ufs
- samsung,exynos2200-cmu-vts
clocks:
minItems: 1
maxItems: 6
clock-names:
minItems: 1
maxItems: 6
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- reg
- "#clock-cells"
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-alive
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: CMU_ALIVE NOC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-cmgp
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: CMU_CMGP NOC clock (from CMU_TOP)
- description: CMU_CMGP PERI clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: peri
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-hsi0
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: External RTC clock (32768 Hz)
- description: CMU_HSI0 NOC clock (from CMU_TOP)
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
- description: CMU_HSI0 DPOSC clock (from CMU_TOP)
- description: CMU_HSI0 USB32DRD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: rtcclk
- const: noc
- const: dpgtc
- const: dposc
- const: usb
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos2200-cmu-peric0
- samsung,exynos2200-cmu-peric1
- samsung,exynos2200-cmu-peric2
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: CMU_PERICn NOC clock (from CMU_TOP)
- description: CMU_PERICn IP0 clock (from CMU_TOP)
- description: CMU_PERICn IP1 clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: ip0
- const: ip1
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (25.6 MHz)
- description: CMU_PERIS NOC clock (from CMU_TOP)
- description: CMU_PERIS GIC clock (from CMU_TOP)
clock-names:
items:
- const: tcxo_div3
- const: noc
- const: gic
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-top
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-ufs
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: CMU_UFS NOC clock (from CMU_TOP)
- description: CMU_UFS MMC clock (from CMU_TOP)
- description: CMU_UFS UFS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: mmc
- const: ufs
- if:
properties:
compatible:
contains:
const: samsung,exynos2200-cmu-vts
then:
properties:
clocks:
items:
- description: External reference clock (76.8 MHz)
- description: CMU_VTS DMIC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dmic
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
cmu_vts: clock-controller@15300000 {
compatible = "samsung,exynos2200-cmu-vts";
reg = <0x15300000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
clock-names = "oscclk", "dmic";
};
...

227
dts/upstream/Bindings/clock/samsung,exynos7870-cmu.yaml Normal file
View File

@@ -0,0 +1,227 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7870 SoC clock controller
maintainers:
- Kaustabh Chakraborty <kauschluss@disroot.org>
description: |
Exynos7870 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clock in that root tree
is an external clock: OSCCLK (26 MHz). This external clock must be defined
as a fixed-rate clock in dts.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
include/dt-bindings/clock/samsung,exynos7870-cmu.h header.
properties:
compatible:
enum:
- samsung,exynos7870-cmu-mif
- samsung,exynos7870-cmu-dispaud
- samsung,exynos7870-cmu-fsys
- samsung,exynos7870-cmu-g3d
- samsung,exynos7870-cmu-isp
- samsung,exynos7870-cmu-mfcmscl
- samsung,exynos7870-cmu-peri
clocks:
minItems: 1
maxItems: 10
clock-names:
minItems: 1
maxItems: 10
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- "#clock-cells"
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-mif
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-dispaud
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_DISPAUD bus clock (from CMU_MIF)
- description: DECON external clock (from CMU_MIF)
- description: DECON vertical clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: bus
- const: decon_eclk
- const: decon_vclk
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-fsys
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS bus clock (from CMU_MIF)
- description: USB20DRD clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: bus
- const: usb20drd
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-g3d
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: G3D switch clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: switch
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-isp
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: ISP camera clock (from CMU_MIF)
- description: ISP clock (from CMU_MIF)
- description: ISP VRA clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: cam
- const: isp
- const: vra
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-mfcmscl
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: MSCL clock (from CMU_MIF)
- description: MFC clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: mfc
- const: mscl
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERI bus clock (from CMU_MIF)
- description: SPI0 clock (from CMU_MIF)
- description: SPI1 clock (from CMU_MIF)
- description: SPI2 clock (from CMU_MIF)
- description: SPI3 clock (from CMU_MIF)
- description: SPI4 clock (from CMU_MIF)
- description: UART0 clock (from CMU_MIF)
- description: UART1 clock (from CMU_MIF)
- description: UART2 clock (from CMU_MIF)
clock-names:
items:
- const: oscclk
- const: bus
- const: spi0
- const: spi1
- const: spi2
- const: spi3
- const: spi4
- const: uart0
- const: uart1
- const: uart2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/samsung,exynos7870-cmu.h>
cmu_peri: clock-controller@101f0000 {
compatible = "samsung,exynos7870-cmu-peri";
reg = <0x101f0000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",
"spi3", "spi4", "uart0", "uart1", "uart2";
clocks = <&oscclk>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
};
...

19
dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
View File

@@ -31,6 +31,7 @@ properties:
compatible:
enum:
- samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-peris
- samsung,exynos990-cmu-top
clocks:
@@ -79,6 +80,24 @@ allOf:
- const: usbdp_debug
- const: dpgtc
- if:
properties:
compatible:
contains:
const: samsung,exynos990-cmu-peris
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_PERIS BUS clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: bus
- if:
properties:
compatible:

65
dts/upstream/Bindings/clock/ti,clkctrl.yaml Normal file
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@@ -0,0 +1,65 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments clkctrl clock
maintainers:
- Tony Lindgren <tony@atomide.com>
- Andreas Kemnade <andreas@kemnade.info>
description: |
Texas Instruments SoCs can have a clkctrl clock controller for each
interconnect target module. The clkctrl clock controller manages functional
and interface clocks for each module. Each clkctrl controller can also
gate one or more optional functional clocks for a module, and can have one
or more clock muxes. There is a clkctrl clock controller typically for each
interconnect target module on omap4 and later variants.
The clock consumers can specify the index of the clkctrl clock using
the hardware offset from the clkctrl instance register space. The optional
clocks can be specified by clkctrl hardware offset and the index of the
optional clock.
properties:
compatible:
enum:
- ti,clkctrl
- ti,clkctrl-l4-cfg
- ti,clkctrl-l4-per
- ti,clkctrl-l4-secure
- ti,clkctrl-l4-wkup
"#clock-cells":
const: 2
clock-output-names:
maxItems: 1
reg:
minItems: 1
maxItems: 8 # arbitrary, should be enough
required:
- compatible
- "#clock-cells"
- clock-output-names
- reg
additionalProperties: false
examples:
- |
bus {
#address-cells = <1>;
#size-cells = <1>;
clock@20 {
compatible = "ti,clkctrl";
clock-output-names = "l4_per";
reg = <0x20 0x1b0>;
#clock-cells = <2>;
};
};

63
dts/upstream/Bindings/clock/ti-clkctrl.txt
View File

@@ -1,63 +0,0 @@
Texas Instruments clkctrl clock binding
Texas Instruments SoCs can have a clkctrl clock controller for each
interconnect target module. The clkctrl clock controller manages functional
and interface clocks for each module. Each clkctrl controller can also
gate one or more optional functional clocks for a module, and can have one
or more clock muxes. There is a clkctrl clock controller typically for each
interconnect target module on omap4 and later variants.
The clock consumers can specify the index of the clkctrl clock using
the hardware offset from the clkctrl instance register space. The optional
clocks can be specified by clkctrl hardware offset and the index of the
optional clock.
For more information, please see the Linux clock framework binding at
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Required properties :
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
"ti,clkctrl-l4-cfg"
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
- clock-output-names : from common clock binding
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
clock index
- reg : clock registers
Example: Clock controller node on omap 4430:
&cm2 {
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per_clkctrl: clock@20 {
compatible = "ti,clkctrl";
clock-output-names = "l4_per";
reg = <0x20 0x1b0>;
#clock-cells = <2>;
};
};
};
};
Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h
#define OMAP4_CLKCTRL_OFFSET 0x20
#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET)
#define MODULEMODE_HWCTRL 1
#define MODULEMODE_SWCTRL 2
#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
...
#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
Example: Clock consumer node for GPIO2:
&gpio2 {
clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
};

88
dts/upstream/Bindings/connector/gocontroll,moduline-module-slot.yaml Normal file
View File

@@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/gocontroll,moduline-module-slot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GOcontroll Moduline Module slot
maintainers:
- Maud Spierings <maudspierings@gocontroll.com>
description:
The GOcontroll Moduline module slot represents a connector that fullfills the
Moduline slot specification, and can thus house any IO module that is also
built to this spec.
properties:
compatible:
const: gocontroll,moduline-module-slot
reg:
maxItems: 1
interrupts:
description: indicates readiness, high means busy.
maxItems: 1
reset-gpios:
description: resets the module, active low.
maxItems: 1
sync-gpios:
description: sync line between all module slots.
maxItems: 1
vdd-supply:
description: low power 3v3 supply generally for the microcontroller.
vddp-supply:
description: medium power 5v0 supply for on module low power peripherals.
vddhpp-supply:
description: high power 6v-8v supply for on module high power peripherals.
power-supply:
description: high power 6v-30v supply for high power module circuits.
i2c-bus:
description: i2c bus shared between module slots and the SoC
$ref: /schemas/types.yaml#/definitions/phandle
slot-number:
description:
The number of the module slot representing the location of on the pcb.
This enables access to the modules based on slot location.
$ref: /schemas/types.yaml#/definitions/uint32
spi-max-frequency: true
required:
- compatible
- reg
- reset-gpios
- interrupts
- sync-gpios
- i2c-bus
- slot-number
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
reg = <0>;
compatible = "gocontroll,moduline-module-slot";
reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&reg_3v3_per>;
vddp-supply = <&reg_5v0>;
vddhpp-supply = <&reg_6v4>;
i2c-bus = <&i2c2>;
slot-number = <1>;
};
};

35
dts/upstream/Bindings/cpufreq/cpufreq-qcom-hw.yaml
View File

@@ -34,6 +34,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
- qcom,qcs8300-cpufreq-epss
- qcom,qdu1000-cpufreq-epss
- qcom,sa8255p-cpufreq-epss
- qcom,sa8775p-cpufreq-epss
@@ -111,22 +112,20 @@ allOf:
enum:
- qcom,qcm2290-cpufreq-hw
- qcom,sar2130p-cpufreq-epss
- qcom,sdx75-cpufreq-epss
then:
properties:
reg:
minItems: 1
maxItems: 1
reg-names:
minItems: 1
maxItems: 1
interrupts:
minItems: 1
maxItems: 1
interrupt-names:
minItems: 1
maxItems: 1
- if:
properties:
@@ -135,6 +134,7 @@ allOf:
enum:
- qcom,qdu1000-cpufreq-epss
- qcom,sa8255p-cpufreq-epss
- qcom,sa8775p-cpufreq-epss
- qcom,sc7180-cpufreq-hw
- qcom,sc8180x-cpufreq-hw
- qcom,sc8280xp-cpufreq-epss
@@ -160,12 +160,14 @@ allOf:
interrupt-names:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- qcom,qcs8300-cpufreq-epss
- qcom,sc7280-cpufreq-epss
- qcom,sm8250-cpufreq-epss
- qcom,sm8350-cpufreq-epss
@@ -187,6 +189,7 @@ allOf:
interrupt-names:
minItems: 3
maxItems: 3
- if:
properties:
@@ -211,7 +214,31 @@ allOf:
interrupt-names:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-cpufreq-epss
then:
properties:
reg:
minItems: 4
maxItems: 4
reg-names:
minItems: 4
maxItems: 4
interrupts:
minItems: 4
maxItems: 4
interrupt-names:
minItems: 4
maxItems: 4
examples:
- |

144
dts/upstream/Bindings/crypto/fsl,sec2.0.yaml Normal file
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@@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
properties:
compatible:
description:
Should contain entries for this and backward compatible SEC versions,
high to low. Warning - SEC1 and SEC2 are mutually exclusive.
oneOf:
- items:
- const: fsl,sec3.3
- const: fsl,sec3.1
- const: fsl,sec3.0
- const: fsl,sec2.4
- const: fsl,sec2.2
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec3.1
- const: fsl,sec3.0
- const: fsl,sec2.4
- const: fsl,sec2.2
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec3.0
- const: fsl,sec2.4
- const: fsl,sec2.2
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec2.4
- const: fsl,sec2.2
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec2.2
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec2.1
- const: fsl,sec2.0
- items:
- const: fsl,sec2.0
- items:
- const: fsl,sec1.2
- const: fsl,sec1.0
- items:
- const: fsl,sec1.0
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,num-channels:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 4 ]
description: An integer representing the number of channels available.
fsl,channel-fifo-len:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 100
description:
An integer representing the number of descriptor pointers each channel
fetch fifo can hold.
fsl,exec-units-mask:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xfff
description: |
The bitmask representing what execution units (EUs) are available.
EU information should be encoded following the SEC's Descriptor Header
Dword EU_SEL0 field documentation, i.e. as follows:
bit 0 = reserved - should be 0
bit 1 = set if SEC has the ARC4 EU (AFEU)
bit 2 = set if SEC has the DES/3DES EU (DEU)
bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
bit 4 = set if SEC has the random number generator EU (RNG)
bit 5 = set if SEC has the public key EU (PKEU)
bit 6 = set if SEC has the AES EU (AESU)
bit 7 = set if SEC has the Kasumi EU (KEU)
bit 8 = set if SEC has the CRC EU (CRCU)
bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
remaining bits are reserved for future SEC EUs.
fsl,descriptor-types-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The bitmask representing what descriptors are available. Descriptor type
information should be encoded following the SEC's Descriptor Header Dword
DESC_TYPE field documentation, i.e. as follows:
bit 0 = SEC supports descriptor type aesu_ctr_nonsnoop
bit 1 = SEC supports descriptor type ipsec_esp
bit 2 = SEC supports descriptor type common_nonsnoop
bit 3 = SEC supports descriptor type 802.11i AES ccmp
bit 4 = SEC supports descriptor type hmac_snoop_no_afeu
bit 5 = SEC supports descriptor type srtp
bit 6 = SEC supports descriptor type non_hmac_snoop_no_afeu
bit 7 = SEC supports descriptor type pkeu_assemble
bit 8 = SEC supports descriptor type aesu_key_expand_output
bit 9 = SEC supports descriptor type pkeu_ptmul
bit 10 = SEC supports descriptor type common_nonsnoop_afeu
bit 11 = SEC supports descriptor type pkeu_ptadd_dbl
..and so on and so forth.
required:
- compatible
- reg
- fsl,num-channels
- fsl,channel-fifo-len
- fsl,exec-units-mask
- fsl,descriptor-types-mask
unevaluatedProperties: false
examples:
- |
/* MPC8548E */
crypto@30000 {
compatible = "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <29 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xfe>;
fsl,descriptor-types-mask = <0x12b0ebf>;
};
...

65
dts/upstream/Bindings/crypto/fsl-sec2.txt
View File

@@ -1,65 +0,0 @@
Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
Required properties:
- compatible : Should contain entries for this and backward compatible
SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3)
e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1)
warning: SEC1 and SEC2 are mutually exclusive
- reg : Offset and length of the register set for the device
- interrupts : the SEC's interrupt number
- fsl,num-channels : An integer representing the number of channels
available.
- fsl,channel-fifo-len : An integer representing the number of
descriptor pointers each channel fetch fifo can hold.
- fsl,exec-units-mask : The bitmask representing what execution units
(EUs) are available. It's a single 32-bit cell. EU information
should be encoded following the SEC's Descriptor Header Dword
EU_SEL0 field documentation, i.e. as follows:
bit 0 = reserved - should be 0
bit 1 = set if SEC has the ARC4 EU (AFEU)
bit 2 = set if SEC has the DES/3DES EU (DEU)
bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
bit 4 = set if SEC has the random number generator EU (RNG)
bit 5 = set if SEC has the public key EU (PKEU)
bit 6 = set if SEC has the AES EU (AESU)
bit 7 = set if SEC has the Kasumi EU (KEU)
bit 8 = set if SEC has the CRC EU (CRCU)
bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
remaining bits are reserved for future SEC EUs.
- fsl,descriptor-types-mask : The bitmask representing what descriptors
are available. It's a single 32-bit cell. Descriptor type information
should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
field documentation, i.e. as follows:
bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
bit 1 = set if SEC supports the ipsec_esp descriptor type
bit 2 = set if SEC supports the common_nonsnoop desc. type
bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
bit 5 = set if SEC supports the srtp descriptor type
bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
bit 7 = set if SEC supports the pkeu_assemble descriptor type
bit 8 = set if SEC supports the aesu_key_expand_output desc.type
bit 9 = set if SEC supports the pkeu_ptmul descriptor type
bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
..and so on and so forth.
Example:
/* MPC8548E */
crypto@30000 {
compatible = "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <29 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xfe>;
fsl,descriptor-types-mask = <0x12b0ebf>;
};

67
dts/upstream/Bindings/crypto/inside-secure,safexcel-eip93.yaml Normal file
View File

@@ -0,0 +1,67 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel-eip93.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Inside Secure SafeXcel EIP-93 cryptographic engine
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description: |
The Inside Secure SafeXcel EIP-93 is a cryptographic engine IP block
integrated in varios devices with very different and generic name from
PKTE to simply vendor+EIP93. The real IP under the hood is actually
developed by Inside Secure and given to license to vendors.
The IP block is sold with different model based on what feature are
needed and are identified with the final letter. Each letter correspond
to a specific set of feature and multiple letter reflect the sum of the
feature set.
EIP-93 models:
- EIP-93i: (basic) DES/Triple DES, AES, PRNG, IPsec ESP, SRTP, SHA1
- EIP-93ie: i + SHA224/256, AES-192/256
- EIP-93is: i + SSL/DTLS/DTLS, MD5, ARC4
- EIP-93ies: i + e + s
- EIP-93iw: i + AES-XCB-MAC, AES-CCM
properties:
compatible:
oneOf:
- items:
- const: airoha,en7581-eip93
- const: inside-secure,safexcel-eip93ies
- items:
- not: {}
description: Need a SoC specific compatible
- enum:
- inside-secure,safexcel-eip93i
- inside-secure,safexcel-eip93ie
- inside-secure,safexcel-eip93is
- inside-secure,safexcel-eip93iw
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
crypto@1e004000 {
compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
reg = <0x1fb70000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};

2
dts/upstream/Bindings/crypto/inside-secure,safexcel.yaml
View File

@@ -47,6 +47,8 @@ properties:
- const: core
- const: reg
dma-coherent: true
required:
- reg
- interrupts

1
dts/upstream/Bindings/crypto/qcom,prng.yaml
View File

@@ -20,6 +20,7 @@ properties:
- qcom,ipq5332-trng
- qcom,ipq5424-trng
- qcom,ipq9574-trng
- qcom,qcs615-trng
- qcom,qcs8300-trng
- qcom,sa8255p-trng
- qcom,sa8775p-trng

1
dts/upstream/Bindings/crypto/qcom-qce.yaml
View File

@@ -55,6 +55,7 @@ properties:
- qcom,sm8550-qce
- qcom,sm8650-qce
- qcom,sm8750-qce
- qcom,x1e80100-qce
- const: qcom,sm8150-qce
- const: qcom,qce

83
dts/upstream/Bindings/display/apple,h7-display-pipe-mipi.yaml Normal file
View File

@@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/apple,h7-display-pipe-mipi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple pre-DCP display controller MIPI interface
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
description:
The MIPI controller part of the pre-DCP Apple display controller
allOf:
- $ref: dsi-controller.yaml#
properties:
compatible:
items:
- enum:
- apple,t8112-display-pipe-mipi
- apple,t8103-display-pipe-mipi
- const: apple,h7-display-pipe-mipi
reg:
maxItems: 1
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input port. Always connected to the primary controller
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output MIPI DSI port to the panel
required:
- port@0
- port@1
required:
- compatible
- reg
- ports
unevaluatedProperties: false
examples:
- |
dsi@28200000 {
compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi";
reg = <0x28200000 0xc000>;
power-domains = <&ps_dispdfr_mipi>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dfr_adp_out_mipi: endpoint {
remote-endpoint = <&dfr_adp_out_mipi>;
};
};
port@1 {
reg = <1>;
dfr_panel_in: endpoint {
remote-endpoint = <&dfr_mipi_out_panel>;
};
};
};
};
...

88
dts/upstream/Bindings/display/apple,h7-display-pipe.yaml Normal file
View File

@@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/apple,h7-display-pipe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple pre-DCP display controller
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
description:
A secondary display controller used to drive the "touchbar" on
certain Apple laptops.
properties:
compatible:
items:
- enum:
- apple,t8112-display-pipe
- apple,t8103-display-pipe
- const: apple,h7-display-pipe
reg:
items:
- description: Primary register block, controls planes and blending
- description:
Contains other configuration registers like interrupt
and FIFO control
reg-names:
items:
- const: be
- const: fe
power-domains:
description:
Phandles to pmgr entries that are needed for this controller to turn on.
Aside from that, their specific functions are unknown
maxItems: 2
interrupts:
items:
- description: Unknown function
- description: Primary interrupt. Vsync events are reported via it
interrupt-names:
items:
- const: be
- const: fe
iommus:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: Output port. Always connected to apple,h7-display-pipe-mipi
required:
- compatible
- reg
- interrupts
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/apple-aic.h>
display-pipe@28200000 {
compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe";
reg = <0x28200000 0xc000>,
<0x28400000 0x4000>;
reg-names = "be", "fe";
power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 502 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 506 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "be", "fe";
iommus = <&displaydfr_dart 0>;
port {
dfr_adp_out_mipi: endpoint {
remote-endpoint = <&dfr_mipi_in_adp>;
};
};
};
...

1
dts/upstream/Bindings/display/bridge/lvds-codec.yaml
View File

@@ -41,6 +41,7 @@ properties:
- enum:
- ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- ti,sn65lvds822 # For the SN65LVDS822 FlatLink LVDS Receiver
- ti,sn65lvds94 # For the SN65DS94 LVDS serdes
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:

18
dts/upstream/Bindings/display/bridge/nwl-dsi.yaml
View File

@@ -111,11 +111,27 @@ properties:
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
DSI output port node to the panel or the next bridge
in the chain
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- port@0
- port@1

3
dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
View File

@@ -35,6 +35,9 @@ properties:
vcc-supply:
description: A 1.8V power supply (see regulator/regulator.yaml).
interrupts:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports

7
dts/upstream/Bindings/display/mediatek/mediatek,dpi.yaml
View File

@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
- mediatek,mt8195-dpi
- items:
- enum:
- mediatek,mt6795-dpi
@@ -35,6 +36,10 @@ properties:
- enum:
- mediatek,mt8365-dpi
- const: mediatek,mt8192-dpi
- items:
- enum:
- mediatek,mt8188-dpi
- const: mediatek,mt8195-dpi
reg:
maxItems: 1
@@ -116,11 +121,13 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
dpi: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;

3
dts/upstream/Bindings/display/mediatek/mediatek,dsc.yaml
View File

@@ -22,6 +22,9 @@ properties:
oneOf:
- enum:
- mediatek,mt8195-disp-dsc
- items:
- const: mediatek,mt8188-disp-dsc
- const: mediatek,mt8195-disp-dsc
reg:
maxItems: 1

70
dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
View File

@@ -231,6 +231,7 @@ allOf:
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
@@ -248,29 +249,12 @@ allOf:
contains:
enum:
- qcom,msm8916-dsi-ctrl
then:
properties:
clocks:
maxItems: 6
clock-names:
items:
- const: mdp_core
- const: iface
- const: bus
- const: byte
- const: pixel
- const: core
- if:
properties:
compatible:
contains:
enum:
- qcom,msm8953-dsi-ctrl
- qcom,msm8976-dsi-ctrl
then:
properties:
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
@@ -291,6 +275,7 @@ allOf:
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
@@ -311,6 +296,7 @@ allOf:
then:
properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
@@ -328,28 +314,13 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
- qcom,sm6125-dsi-ctrl
- qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
maxItems: 6
clock-names:
items:
- const: byte
- const: byte_intf
- const: pixel
- const: core
- const: iface
- const: bus
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7180-dsi-ctrl
- qcom,sc7280-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6125-dsi-ctrl
- qcom,sm6350-dsi-ctrl
- qcom,sm6375-dsi-ctrl
- qcom,sm6150-dsi-ctrl
- qcom,sm7150-dsi-ctrl
- qcom,sm8150-dsi-ctrl
@@ -361,6 +332,7 @@ allOf:
then:
properties:
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
@@ -380,6 +352,7 @@ allOf:
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
items:
@@ -393,27 +366,6 @@ allOf:
- const: pixel
- const: core
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6375-dsi-ctrl
then:
properties:
clocks:
maxItems: 6
clock-names:
items:
- const: byte
- const: byte_intf
- const: pixel
- const: core
- const: iface
- const: bus
unevaluatedProperties: false
examples:

2
dts/upstream/Bindings/display/msm/dsi-phy-common.yaml
View File

@@ -15,6 +15,8 @@ description:
properties:
"#clock-cells":
const: 1
description:
See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs.
"#phy-cells":
const: 0

1
dts/upstream/Bindings/display/msm/gmu.yaml
View File

@@ -123,6 +123,7 @@ allOf:
compatible:
contains:
enum:
- qcom,adreno-gmu-623.0
- qcom,adreno-gmu-635.0
- qcom,adreno-gmu-660.1
- qcom,adreno-gmu-663.0

32
dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
View File

@@ -52,6 +52,13 @@ patternProperties:
items:
- const: qcom,sa8775p-dp
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sa8775p-edp-phy
required:
- compatible
@@ -61,6 +68,7 @@ examples:
- |
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -158,6 +166,26 @@ examples:
};
};
mdss0_dp0_phy: phy@aec2a00 {
compatible = "qcom,sa8775p-edp-phy";
reg = <0x0aec2a00 0x200>,
<0x0aec2200 0xd0>,
<0x0aec2600 0xd0>,
<0x0aec2000 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux",
"cfg_ahb";
#clock-cells = <1>;
#phy-cells = <0>;
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l4a>;
};
displayport-controller@af54000 {
compatible = "qcom,sa8775p-dp";
@@ -186,9 +214,9 @@ examples:
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
<&dispcc_mdss_dptx0_pixel0_clk_src>;
assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
phys = <&mdss0_edp_phy>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;

14
dts/upstream/Bindings/display/msm/qcom,sm8550-mdss.yaml
View File

@@ -30,10 +30,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 2
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -91,9 +95,9 @@ examples:
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
interconnect-names = "mdp0-mem", "cpu-cfg";
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

13
dts/upstream/Bindings/display/msm/qcom,sm8650-mdss.yaml
View File

@@ -29,10 +29,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 2
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -75,12 +79,17 @@ examples:
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8650-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
interconnect-names = "mdp0-mem", "cpu-cfg";
resets = <&dispcc_core_bcr>;
power-domains = <&dispcc_gdsc>;

58
dts/upstream/Bindings/display/panel/apple,summit.yaml Normal file
View File

@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/apple,summit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple "Summit" display panel
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
description:
An OLED panel used as a touchbar on certain Apple laptops.
Contains a backlight device, which controls brightness of the panel itself.
The backlight common properties are included for this reason
allOf:
- $ref: panel-common.yaml#
- $ref: /schemas/leds/backlight/common.yaml#
properties:
compatible:
items:
- enum:
- apple,j293-summit
- apple,j493-summit
- const: apple,summit
reg:
maxItems: 1
required:
- compatible
- reg
- max-brightness
- port
unevaluatedProperties: false
examples:
- |
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "apple,j293-summit", "apple,summit";
reg = <0>;
max-brightness = <255>;
port {
endpoint {
remote-endpoint = <&dfr_bridge_out>;
};
};
};
};
...

6
dts/upstream/Bindings/display/panel/himax,hx83102.yaml
View File

@@ -18,8 +18,14 @@ properties:
- enum:
# Boe nv110wum-l60 11.0" WUXGA TFT LCD panel
- boe,nv110wum-l60
# CSOT pna957qt1-1 10.95" WUXGA TFT LCD panel
- csot,pna957qt1-1
# IVO t109nw41 11.0" WUXGA TFT LCD panel
- ivo,t109nw41
# KINGDISPLAY KD110N11-51IE 10.95" WUXGA TFT LCD panel
- kingdisplay,kd110n11-51ie
# STARRY 2082109QFH040022-50E 10.95" WUXGA TFT LCD panel
- starry,2082109qfh040022-50e
# STARRY himax83102-j02 10.51" WUXGA TFT LCD panel
- starry,himax83102-j02
- const: himax,hx83102

6
dts/upstream/Bindings/display/panel/mitsubishi,aa104xd12.yaml
View File

@@ -33,7 +33,9 @@ properties:
description: Reference to the regulator powering the panel VCC pins.
data-mapping:
const: jeida-24
enum:
- jeida-18
- jeida-24
width-mm:
const: 210
@@ -41,6 +43,7 @@ properties:
height-mm:
const: 158
backlight: true
panel-timing: true
port: true
@@ -48,7 +51,6 @@ additionalProperties: false
required:
- compatible
- vcc-supply
- data-mapping
- width-mm
- height-mm

2
dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
View File

@@ -40,6 +40,8 @@ properties:
- auo,g185han01
# AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel
- auo,g190ean01
# BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel
- boe,av123z7m-n17
# Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
- koe,tx26d202vm0bwa
# Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200

2
dts/upstream/Bindings/display/panel/panel-simple.yaml
View File

@@ -63,6 +63,8 @@ properties:
- auo,t215hvn01
# Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
- avic,tm070ddh03
# BOE AV101HDT-a10 10.1" 1280x720 LVDS panel
- boe,av101hdt-a10
# BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel
- boe,bp082wx1-100
# BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel

72
dts/upstream/Bindings/display/panel/raydium,rm67200.yaml Normal file
View File

@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/raydium,rm67200.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Raydium RM67200 based MIPI-DSI panels
maintainers:
- Sebastian Reichel <sebastian.reichel@collabora.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- wanchanglong,w552793baa
- const: raydium,rm67200
reg:
maxItems: 1
vdd-supply:
description: 2.8V Logic voltage
iovcc-supply:
description: 1.8V IO voltage
vsp-supply:
description: positive 5.5V voltage
vsn-supply:
description: negative 5.5V voltage
backlight: true
port: true
reset-gpios: true
required:
- compatible
- port
- reg
- reset-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "wanchanglong,w552793baa", "raydium,rm67200";
reg = <0>;
vdd-supply = <&regulator1>;
iovcc-supply = <&regulator2>;
vsp-supply = <&regulator3>;
vsn-supply = <&regulator4>;
reset-gpios = <&gpiobank 42 GPIO_ACTIVE_LOW>;
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
...

77
dts/upstream/Bindings/display/panel/visionox,rm692e5.yaml Normal file
View File

@@ -0,0 +1,77 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/visionox,rm692e5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Visionox RM692E5 6.55" 2400x1080 120Hz MIPI-DSI Panel
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
description:
The Visionox RM692E5 is a generic DSI Panel IC used to control
AMOLED panels.
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
oneOf:
- enum:
- visionox,rm692e5
- items:
- enum:
- nothing,rm692e5-spacewar
- const: visionox,rm692e5
reg:
maxItems: 1
vdd-supply:
description: 3.3V source voltage rail
vddio-supply:
description: 1.8V I/O source voltage rail
reset-gpios: true
port: true
required:
- compatible
- reg
- reset-gpios
- vdd-supply
- vddio-supply
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "nothing,rm692e5-spacewar",
"visionox,rm692e5";
reg = <0>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
vdd-supply = <&vdd_oled>;
vddio-supply = <&vdd_io_oled>;
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
...

36
dts/upstream/Bindings/display/renesas,du.yaml
View File

@@ -47,12 +47,26 @@ properties:
maxItems: 1
# See compatible-specific constraints below.
clocks: true
clock-names: true
clocks:
minItems: 1
maxItems: 8
clock-names:
minItems: 1
maxItems: 8
interrupts:
minItems: 1
maxItems: 4
description: Interrupt specifiers, one per DU channel
resets: true
reset-names: true
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
@@ -74,7 +88,7 @@ properties:
renesas,cmms:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
minItems: 2
maxItems: 4
items:
maxItems: 1
@@ -174,6 +188,7 @@ allOf:
- pattern: '^dclkin\.[01]$'
interrupts:
minItems: 2
maxItems: 2
resets:
@@ -229,6 +244,7 @@ allOf:
- pattern: '^dclkin\.[01]$'
interrupts:
minItems: 2
maxItems: 2
resets:
@@ -282,6 +298,7 @@ allOf:
- pattern: '^dclkin\.[01]$'
interrupts:
minItems: 2
maxItems: 2
resets:
@@ -336,6 +353,7 @@ allOf:
- pattern: '^dclkin\.[01]$'
interrupts:
minItems: 2
maxItems: 2
resets:
@@ -397,6 +415,7 @@ allOf:
- pattern: '^dclkin\.[012]$'
interrupts:
minItems: 3
maxItems: 3
resets:
@@ -461,9 +480,11 @@ allOf:
- pattern: '^dclkin\.[0123]$'
interrupts:
minItems: 4
maxItems: 4
resets:
minItems: 2
maxItems: 2
reset-names:
@@ -534,9 +555,11 @@ allOf:
- pattern: '^dclkin\.[012]$'
interrupts:
minItems: 3
maxItems: 3
resets:
minItems: 2
maxItems: 2
reset-names:
@@ -605,9 +628,11 @@ allOf:
- pattern: '^dclkin\.[013]$'
interrupts:
minItems: 3
maxItems: 3
resets:
minItems: 2
maxItems: 2
reset-names:
@@ -726,6 +751,7 @@ allOf:
- pattern: '^dclkin\.[01]$'
interrupts:
minItems: 2
maxItems: 2
resets:

3
dts/upstream/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml
View File

@@ -29,6 +29,7 @@ allOf:
properties:
compatible:
enum:
- rockchip,rk3576-dw-hdmi-qp
- rockchip,rk3588-dw-hdmi-qp
reg:
@@ -156,7 +157,7 @@ examples:
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
phys = <&hdptxphy_hdmi0>;
phys = <&hdptxphy0>;
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
reset-names = "ref", "hdp";

115
dts/upstream/Bindings/display/rockchip/rockchip-vop2.yaml
View File

@@ -14,12 +14,14 @@ description:
maintainers:
- Sandy Huang <hjc@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
- Andy Yan <andyshrk@163.com>
properties:
compatible:
enum:
- rockchip,rk3566-vop
- rockchip,rk3568-vop
- rockchip,rk3576-vop
- rockchip,rk3588-vop
reg:
@@ -37,10 +39,21 @@ properties:
- const: gamma-lut
interrupts:
maxItems: 1
minItems: 1
maxItems: 4
description:
The VOP interrupt is shared by several interrupt sources, such as
frame start (VSYNC), line flag and other status interrupts.
For VOP version under rk3576, the interrupt is shared by several interrupt
sources, such as frame start (VSYNC), line flag and other interrupt status.
For VOP version from rk3576 there is a system interrupt for bus error, and
every video port has it's independent interrupts for vsync and other video
port related error interrupts.
interrupt-names:
items:
- const: sys
- const: vp0
- const: vp1
- const: vp2
# See compatible-specific constraints below.
clocks:
@@ -53,6 +66,8 @@ properties:
- description: Pixel clock for video port 2.
- description: Pixel clock for video port 3.
- description: Peripheral(vop grf/dsi) clock.
- description: Alternative pixel clock provided by HDMI0 PHY PLL.
- description: Alternative pixel clock provided by HDMI1 PHY PLL.
clock-names:
minItems: 5
@@ -64,6 +79,8 @@ properties:
- const: dclk_vp2
- const: dclk_vp3
- const: pclk_vop
- const: pll_hdmiphy0
- const: pll_hdmiphy1
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -116,6 +133,72 @@ required:
- ports
allOf:
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3566-vop
- rockchip,rk3568-vop
then:
properties:
clocks:
maxItems: 5
clock-names:
maxItems: 5
interrupts:
maxItems: 1
interrupt-names: false
ports:
required:
- port@0
- port@1
- port@2
rockchip,vo1-grf: false
rockchip,vop-grf: false
rockchip,pmu: false
required:
- rockchip,grf
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3576-vop
then:
properties:
clocks:
maxItems: 5
clock-names:
maxItems: 5
interrupts:
minItems: 4
interrupt-names:
minItems: 4
ports:
required:
- port@0
- port@1
- port@2
rockchip,vo1-grf: false
rockchip,vop-grf: false
required:
- rockchip,grf
- rockchip,pmu
- if:
properties:
compatible:
@@ -125,8 +208,16 @@ allOf:
properties:
clocks:
minItems: 7
maxItems: 9
clock-names:
minItems: 7
maxItems: 9
interrupts:
maxItems: 1
interrupt-names: false
ports:
required:
@@ -141,23 +232,6 @@ allOf:
- rockchip,vop-grf
- rockchip,pmu
else:
properties:
rockchip,vo1-grf: false
rockchip,vop-grf: false
rockchip,pmu: false
clocks:
maxItems: 5
clock-names:
maxItems: 5
ports:
required:
- port@0
- port@1
- port@2
additionalProperties: false
examples:
@@ -184,6 +258,7 @@ examples:
"dclk_vp1",
"dclk_vp2";
power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>;
iommus = <&vop_mmu>;
vop_out: ports {
#address-cells = <1>;

1
dts/upstream/Bindings/display/tegra/nvidia,tegra114-mipi.yaml
View File

@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- nvidia,tegra114-mipi
- nvidia,tegra124-mipi
- nvidia,tegra210-mipi
- nvidia,tegra186-mipi

68
dts/upstream/Bindings/dma/atmel,at91sam9g45-dma.yaml Normal file
View File

@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Direct Memory Access Controller (DMA)
maintainers:
- Ludovic Desroches <ludovic.desroches@microchip.com>
description:
The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
peripheral to a destination peripheral over one or more AMBA buses. One channel
is required for each source/destination pair. In the most basic configuration,
the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are
required for each DMAC data transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
properties:
compatible:
enum:
- atmel,at91sam9g45-dma
- atmel,at91sam9rl-dma
reg:
maxItems: 1
interrupts:
maxItems: 1
"#dma-cells":
description:
Must be <2>, used to represent the number of integer cells in the dma
property of client devices. The two cells in order are
1. The first cell represents the channel number.
2. The second cell is 0 for RX and 1 for TX transfers.
const: 2
clocks:
maxItems: 1
clock-names:
const: dma_clk
required:
- compatible
- reg
- interrupts
- "#dma-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
#dma-cells = <2>;
clocks = <&pmc 2 20>;
clock-names = "dma_clk";
};
...

3
dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
View File

@@ -32,6 +32,9 @@ properties:
- microchip,sam9x60-dma
- microchip,sam9x7-dma
- const: atmel,sama5d4-dma
- items:
- const: microchip,sama7d65-dma
- const: microchip,sama7g5-dma
"#dma-cells":
description: |

42
dts/upstream/Bindings/dma/atmel-dma.txt
View File

@@ -1,42 +0,0 @@
* Atmel Direct Memory Access Controller (DMA)
Required properties:
- compatible: Should be "atmel,<chip>-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <2>, used to represent the number of integer cells in
the dmas property of client devices.
Example:
dma0: dma@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
#dma-cells = <2>;
};
DMA clients connected to the Atmel DMA controller must use the format
described in the dma.txt file, using a three-cell specifier for each channel:
a phandle plus two integer cells.
The three cells in order are:
1. A phandle pointing to the DMA controller.
2. The memory interface (16 most significant bits), the peripheral interface
(16 less significant bits).
3. Parameters for the at91 DMA configuration register which are device
dependent:
- bit 7-0: peripheral identifier for the hardware handshaking interface. The
identifier can be different for tx and rx.
- bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
Example:
i2c0@i2c@f8010000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
interrupts = <9 4 6>;
dmas = <&dma0 1 7>,
<&dma0 1 8>;
dma-names = "tx", "rx";
};

8
dts/upstream/Bindings/dma/fsl,edma.yaml
View File

@@ -27,6 +27,14 @@ properties:
- fsl,imx93-edma4
- fsl,imx95-edma5
- nxp,s32g2-edma
- items:
- enum:
- fsl,imx94-edma3
- const: fsl,imx93-edma3
- items:
- enum:
- fsl,imx94-edma5
- const: fsl,imx95-edma5
- items:
- const: fsl,ls1028a-edma
- const: fsl,vf610-edma

137
dts/upstream/Bindings/dma/fsl,elo-dma.yaml Normal file
View File

@@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Elo DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
series chips such as mpc8315, mpc8349, mpc8379 etc.
properties:
compatible:
items:
- enum:
- fsl,mpc8313-dma
- fsl,mpc8315-dma
- fsl,mpc8323-dma
- fsl,mpc8347-dma
- fsl,mpc8349-dma
- fsl,mpc8360-dma
- fsl,mpc8377-dma
- fsl,mpc8378-dma
- fsl,mpc8379-dma
- const: fsl,elo-dma
reg:
items:
- description:
DMA General Status Register, i.e. DGSR which contains status for
all the 4 DMA channels.
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
description: Controller index. 0 for controller @ 0x8100.
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
description: Controller interrupt.
required:
- compatible
- reg
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
# native DMA channel
- items:
- enum:
- fsl,mpc8315-dma-channel
- fsl,mpc8323-dma-channel
- fsl,mpc8347-dma-channel
- fsl,mpc8349-dma-channel
- fsl,mpc8360-dma-channel
- fsl,mpc8377-dma-channel
- fsl,mpc8378-dma-channel
- fsl,mpc8379-dma-channel
- const: fsl,elo-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- const: fsl,ssi-dma-channel
reg:
maxItems: 1
cell-index:
description: DMA channel index starts at 0.
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@82a8 {
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8100 0x1a4>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
};
...

125
dts/upstream/Bindings/dma/fsl,elo3-dma.yaml Normal file
View File

@@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Elo3 DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
DMA controller which has same function as EloPlus except that Elo3 has 8
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
series chips, such as t1040, t4240, b4860.
properties:
compatible:
const: fsl,elo3-dma
reg:
items:
- description:
DMA General Status Registers starting from DGSR0, for channel 1~4
- description:
DMA General Status Registers starting from DGSR1, for channel 5~8
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
# native DMA channel
- fsl,eloplus-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- fsl,ssi-dma-channel
reg:
maxItems: 1
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@100300 {
compatible = "fsl,elo3-dma";
reg = <0x100300 0x4>,
<0x100600 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x100100 0x500>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@300 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x300 0x80>;
interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@380 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x380 0x80>;
interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@400 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x400 0x80>;
interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@480 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x480 0x80>;
interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
};
};
...

132
dts/upstream/Bindings/dma/fsl,eloplus-dma.yaml Normal file
View File

@@ -0,0 +1,132 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale EloPlus DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
This is a 4-channel DMA controller with extended addresses and chaining,
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
mpc8540, mpc8641 p4080, bsc9131 etc.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,mpc8540-dma
- fsl,mpc8541-dma
- fsl,mpc8548-dma
- fsl,mpc8555-dma
- fsl,mpc8560-dma
- fsl,mpc8572-dma
- fsl,mpc8641-dma
- const: fsl,eloplus-dma
- const: fsl,eloplus-dma
reg:
items:
- description:
DMA General Status Register, i.e. DGSR which contains
status for all the 4 DMA channels
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
description: Controller interrupt.
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
# native DMA channel
- items:
- enum:
- fsl,mpc8540-dma-channel
- fsl,mpc8541-dma-channel
- fsl,mpc8548-dma-channel
- fsl,mpc8555-dma-channel
- fsl,mpc8560-dma-channel
- fsl,mpc8572-dma-channel
- const: fsl,eloplus-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- const: fsl,ssi-dma-channel
reg:
maxItems: 1
cell-index:
description: DMA channel index starts at 0.
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@21300 {
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
reg = <0x21300 4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@80 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@100 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@180 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
};
};
...

6
dts/upstream/Bindings/dma/fsl,mxs-dma.yaml
View File

@@ -31,6 +31,12 @@ properties:
- fsl,imx6q-dma-apbh
- fsl,imx6sx-dma-apbh
- fsl,imx7d-dma-apbh
- fsl,imx8dxl-dma-apbh
- fsl,imx8mm-dma-apbh
- fsl,imx8mn-dma-apbh
- fsl,imx8mp-dma-apbh
- fsl,imx8mq-dma-apbh
- fsl,imx8qm-dma-apbh
- fsl,imx8qxp-dma-apbh
- const: fsl,imx28-dma-apbh
- enum:

2
dts/upstream/Bindings/dma/snps,dw-axi-dmac.yaml
View File

@@ -59,6 +59,8 @@ properties:
minimum: 1
maximum: 8
dma-noncoherent: true
resets:
minItems: 1
maxItems: 2

3
dts/upstream/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
View File

@@ -75,7 +75,6 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
fpd_dma_chan1: dma-controller@fd500000 {
compatible = "xlnx,zynqmp-dma-1.0";
@@ -84,7 +83,7 @@ examples:
interrupts = <0 117 0x4>;
#dma-cells = <1>;
clock-names = "clk_main", "clk_apb";
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
xlnx,bus-width = <128>;
dma-coherent;
};

24
dts/upstream/Bindings/dsp/fsl,dsp.yaml
View File

@@ -82,6 +82,15 @@ properties:
description:
Phandle to syscon block which provide access for processor enablement
resets:
minItems: 1
reset-names:
minItems: 1
items:
- const: runstall
- const: softreset
required:
- compatible
- reg
@@ -164,6 +173,17 @@ allOf:
- const: txdb1
- const: rxdb0
- const: rxdb1
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8mp-dsp
- fsl,imx8mp-hifi4
then:
required:
- resets
- reset-names
additionalProperties: false
@@ -186,6 +206,7 @@ examples:
};
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/reset/imx8mp-reset-audiomix.h>
dsp_reserved: dsp@92400000 {
reg = <0x92400000 0x1000000>;
no-map;
@@ -220,5 +241,6 @@ examples:
<&mu2 3 0>;
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
fsl,dsp-ctrl = <&audio_blk_ctrl>;
resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>;
reset-names = "runstall";
};

8
dts/upstream/Bindings/dts-coding-style.rst
View File

@@ -133,6 +133,9 @@ The above-described ordering follows this approach:
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
The individual properties inside each group shall use natural sort order by
the property name.
Example::
/* SoC DTSI */
@@ -158,7 +161,10 @@ Example::
/* Board DTS */
&device_node {
vdd-supply = <&board_vreg1>;
vdd-0v9-supply = <&board_vreg1>;
vdd-1v8-supply = <&board_vreg4>;
vdd-3v3-supply = <&board_vreg2>;
vdd-12v-supply = <&board_vreg3>;
status = "okay";
}

323
dts/upstream/Bindings/edac/altr,socfpga-ecc-manager.yaml Normal file
View File

@@ -0,0 +1,323 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2025 Altera Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera SoCFPGA ECC Manager
maintainers:
- Matthew Gerlach <matthew.gerlach@altera.com>
description:
This binding describes the device tree nodes required for the Altera SoCFPGA
ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
families.
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-ecc-manager
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
ranges: true
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to Stratix10 System Manager Block with the ECC manager registers
sdramedac:
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,sdram-edac-a10
- altr,sdram-edac-s10
interrupts:
minItems: 1
maxItems: 2
altr,sdr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SDRAM parent
required:
- compatible
- interrupts
- altr,sdr-syscon
patternProperties:
"^ocram-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-ocram-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
iram:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
required:
- compatible
- reg
- interrupts
"^usb[0-9]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-usb-ecc
- const: altr,socfpga-usb-ecc
- const: altr,socfpga-usb-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to USB parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to ethernet parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^sdmmc[a-f]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 4
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^l2-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,socfpga-a10-l2-ecc
- altr,socfpga-l2-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
required:
- compatible
- reg
- interrupts
"^dma-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
const: altr,socfpga-dma-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
if:
properties:
compatible:
contains:
const: altr,socfpga-ecc-manager
then:
required:
- compatible
- "#address-cells"
- "#size-cells"
- ranges
else:
required:
- compatible
- "#address-cells"
- "#size-cells"
- interrupts
- interrupt-controller
- "#interrupt-cells"
- ranges
- altr,sysmgr-syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager",
"altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc",
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc",
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};

383
dts/upstream/Bindings/edac/socfpga-eccmgr.txt
View File

@@ -1,383 +0,0 @@
Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.
Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
Example:
eccmgr: eccmgr@ffd08140 {
compatible = "altr,socfpga-ecc-manager";
#address-cells = <1>;
#size-cells = <1>;
ranges;
l2-ecc@ffd08140 {
compatible = "altr,socfpga-l2-ecc";
reg = <0xffd08140 0x4>;
interrupts = <0 36 1>, <0 37 1>;
};
ocram-ecc@ffd08144 {
compatible = "altr,socfpga-ocram-ecc";
reg = <0xffd08144 0x4>;
iram = <&ocram>;
interrupts = <0 178 1>, <0 179 1>;
};
};
Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.
Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
QSPI FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-qspi-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order for port A, and then single bit error interrupt,
then double bit error interrupt in this order for port B.
Example:
eccmgr: eccmgr@ffd06000 {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
<32 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x90>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH> ;
};
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
<36 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0c00 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0c00 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
nand-buf-ecc@ff8c2000 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2000 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c2400 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2400 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c2800 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2800 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
qspi-ecc@ff8c8400 {
compatible = "altr,socfpga-qspi-ecc";
reg = <0xff8c8400 0x400>;
altr,ecc-parent = <&qspi>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<46 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
Stratix10 SoCFPGA ECC Manager (ARM64)
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, Stratix10 ECC
requires access to registers that can only be read from Secure Monitor
with SMC calls. Therefore the device tree is slightly different. Note
that only 1 interrupt is sent in Stratix10 because the double bit errors
are treated as SErrors in ARM64 instead of IRQs in ARM32.
Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
containing the ECC manager registers.
- interrupts : Should be single bit error interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent OCRAM node.
- interrupts : Should be single bit error interrupt.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt for port A
and then single bit error interrupt for port B.
Example:
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 15 4>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc";
reg = <ff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
};
nand-buf-ecc@ff8c8000 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8000 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c8400 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8400 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c8800 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8800 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c9000 {
compatible = "altr,socfpga-s10-dma-ecc";
reg = <0xff8c9000 0x100>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};

5
dts/upstream/Bindings/eeprom/at24.yaml
View File

@@ -130,10 +130,13 @@ properties:
- const: giantec,gt24c32a
- const: atmel,24c32
- items:
- const: onnn,n24s64b
- enum:
- onnn,n24s64b
- puya,p24c64f
- const: atmel,24c64
- items:
- enum:
- giantec,gt24p128e
- giantec,gt24p128f
- renesas,r1ex24128
- samsung,s524ad0xd1

12
dts/upstream/Bindings/firmware/fsl,scu.yaml
View File

@@ -45,6 +45,18 @@ properties:
Keys provided by the SCU
$ref: /schemas/input/fsl,scu-key.yaml
reset-controller:
type: object
properties:
compatible:
const: fsl,imx-scu-reset
'#reset-cells':
const: 1
required:
- compatible
- '#reset-cells'
additionalProperties: false
mboxes:
description:
A list of phandles of TX MU channels followed by a list of phandles of

50
dts/upstream/Bindings/firmware/google,gs101-acpm-ipc.yaml Normal file
View File

@@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2024 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/google,gs101-acpm-ipc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos ACPM mailbox protocol
maintainers:
- Tudor Ambarus <tudor.ambarus@linaro.org>
description: |
ACPM (Alive Clock and Power Manager) is a firmware that operates on the
APM (Active Power Management) module that handles overall power management
activities. ACPM and masters regard each other as independent hardware
component and communicate with each other using mailbox messages and
shared memory.
This binding is intended to define the interface the firmware implementing
ACPM provides for OSPM in the device tree.
properties:
compatible:
const: google,gs101-acpm-ipc
mboxes:
maxItems: 1
shmem:
description:
List of phandle pointing to the shared memory (SHM) area. The memory
contains channels configuration data and the TX/RX ring buffers that
are used for passing messages to/from the ACPM firmware.
maxItems: 1
required:
- compatible
- mboxes
- shmem
additionalProperties: false
examples:
- |
power-management {
compatible = "google,gs101-acpm-ipc";
mboxes = <&ap2apm_mailbox>;
shmem = <&apm_sram>;
};

53
dts/upstream/Bindings/firmware/thead,th1520-aon.yaml Normal file
View File

@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-HEAD TH1520 AON (Always-On) Firmware
description: |
The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing
low-power states, system wakeup events, and power management tasks. It is
designed to operate independently in a dedicated power domain, allowing it to
remain functional even during the SoC's deep sleep states.
At the heart of the AON subsystem is the E902, a low-power core that executes
firmware responsible for coordinating tasks such as power domain control,
clock management, and system wakeup signaling. Communication between the main
SoC and the AON subsystem is handled through a mailbox interface, which
enables message-based interactions with the AON firmware.
maintainers:
- Michal Wilczynski <m.wilczynski@samsung.com>
properties:
compatible:
const: thead,th1520-aon
mboxes:
maxItems: 1
mbox-names:
items:
- const: aon
"#power-domain-cells":
const: 1
required:
- compatible
- mboxes
- mbox-names
- "#power-domain-cells"
additionalProperties: false
examples:
- |
aon: aon {
compatible = "thead,th1520-aon";
mboxes = <&mbox_910t 1>;
mbox-names = "aon";
#power-domain-cells = <1>;
};

1
dts/upstream/Bindings/fsi/ibm,p9-scom.yaml
View File

@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- ibm,fsi2pib
- ibm,p9-scom
- ibm,i2cr-scom

6
dts/upstream/Bindings/gpio/aspeed,ast2400-gpio.yaml
View File

@@ -46,6 +46,12 @@ properties:
minimum: 12
maximum: 232
patternProperties:
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
required:
- compatible
- reg

10
dts/upstream/Bindings/gpio/gpio-mvebu.yaml
View File

@@ -72,6 +72,9 @@ properties:
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
marvell,pwm-offset:
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset in the register map for the pwm registers (in bytes)
@@ -96,6 +99,13 @@ properties:
- const: axi
minItems: 1
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- compatible
- gpio-controller

1
dts/upstream/Bindings/gpio/gpio-vf610.yaml
View File

@@ -28,6 +28,7 @@ properties:
- items:
- enum:
- fsl,imx93-gpio
- fsl,imx94-gpio
- fsl,imx95-gpio
- const: fsl,imx8ulp-gpio

3
dts/upstream/Bindings/gpio/loongson,ls-gpio.yaml
View File

@@ -20,7 +20,10 @@ properties:
- loongson,ls2k2000-gpio1
- loongson,ls2k2000-gpio2
- loongson,ls3a5000-gpio
- loongson,ls3a6000-gpio # Loongson-3A6000 node GPIO
- loongson,ls7a-gpio
- loongson,ls7a2000-gpio1 # LS7A2000 chipset GPIO
- loongson,ls7a2000-gpio2 # LS7A2000 ACPI GPIO
- items:
- const: loongson,ls2k1000-gpio
- const: loongson,ls2k-gpio

37
dts/upstream/Bindings/gpio/nxp,pcf8575.yaml
View File

@@ -73,6 +73,43 @@ properties:
wakeup-source: true
reset-gpios:
maxItems: 1
description:
GPIO controlling the (reset active LOW) RESET# pin.
The active polarity of the GPIO must translate to the low state of the
RESET# pin on the IC, i.e. if a GPIO is directly routed to the RESET# pin
without any inverter, GPIO_ACTIVE_LOW is expected.
Performing a reset makes all lines initialized to their input (pulled-up)
state.
allOf:
- if:
properties:
compatible:
not:
contains:
enum:
- nxp,pca9670
- nxp,pca9671
- nxp,pca9672
- nxp,pca9673
then:
properties:
reset-gpios: false
# lines-initial-states XOR reset-gpios
# Performing a reset reinitializes all lines to a known state which
# may not match passed lines-initial-states
- if:
required:
- lines-initial-states
then:
properties:
reset-gpios: false
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object

1
dts/upstream/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
View File

@@ -12,7 +12,6 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:

4
dts/upstream/Bindings/gpu/arm,mali-bifrost.yaml
View File

@@ -17,6 +17,7 @@ properties:
oneOf:
- items:
- enum:
- allwinner,sun50i-h616-mali
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- mediatek,mt8183b-mali
@@ -24,7 +25,9 @@ properties:
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
- rockchip,rk3568-mali
- rockchip,rk3576-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -142,6 +145,7 @@ allOf:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
then:
properties:
interrupts:

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