mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-02 09:46:37 +03:00
riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
committed by
Leo Yu-Chi Liang
parent
5ecf9b0b8a
commit
2f5fad0b0d
28
arch/riscv/cpu/jh7110/Kconfig
Normal file
28
arch/riscv/cpu/jh7110/Kconfig
Normal file
@@ -0,0 +1,28 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
|
||||
config STARFIVE_JH7110
|
||||
bool
|
||||
select ARCH_EARLY_INIT_R
|
||||
select CLK_JH7110
|
||||
select CPU
|
||||
select CPU_RISCV
|
||||
select RAM
|
||||
select RESET_JH7110
|
||||
select SUPPORT_SPL
|
||||
select SPL_RAM if SPL
|
||||
select SPL_STARFIVE_DDR
|
||||
select PINCTRL_STARFIVE_JH7110
|
||||
imply MMC
|
||||
imply MMC_BROKEN_CD
|
||||
imply MMC_SPI
|
||||
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
|
||||
imply SIFIVE_CACHE
|
||||
imply SIFIVE_CCACHE
|
||||
imply SMP
|
||||
imply SPI
|
||||
imply SPL_CPU
|
||||
imply SPL_LOAD_FIT
|
||||
imply SPL_OPENSBI
|
||||
imply SPL_SIFIVE_CLINT
|
||||
Reference in New Issue
Block a user