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pwm: tegra: fix pulse_width calculation

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The pulse_width is expressed as N/256. A 100% duty cycle is only possible
when multiplied by 256 instead of 255.

Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Jonas Schwöbel
2025-03-11 23:11:47 +01:00
committed by Svyatoslav Ryhel
parent 0623b8512e
commit 2fcb08a2b4
1 changed files with 1 additions and 1 deletions
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2
drivers/pwm/tegra_pwm.c
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@@ -40,7 +40,7 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
return -EINVAL;
debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
pulse_width = duty_ns * 255 / period_ns;
pulse_width = duty_ns * 256 / period_ns;
if (priv->polarity & BIT(channel))
pulse_width = 256 - pulse_width;