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km/ppc: migrate all mpc83xx to DM_I2C

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Enable DM_I2C and I2C mux to get rid of the usage of the legacy
i2c driver.

Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
This commit is contained in:
Holger Brunck
2022-12-02 18:22:42 +01:00
committed by Tom Rini
parent 400d1a7c94
commit 31464f9455
11 changed files with 23 additions and 126 deletions
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3
board/keymile/Kconfig
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@@ -100,8 +100,7 @@ config KM_MVEXTSW_ADDR
config KM_IVM_BUS
int "IVM I2C Bus"
default 0 if ARCH_SOCFPGA
default 1 if MPC85xx || ARCH_LS1021A
default 2 if MPC83xx
default 1 if PPC || ARCH_LS1021A
help
Identifier number of I2C bus, where the inventory EEPROM is connected to.

2
board/keymile/km83xx/Makefile
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@@ -3,4 +3,4 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
obj-y += km83xx.o ../common/common.o ../common/ivm.o

73
board/keymile/km83xx/km83xx_i2c.c
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@@ -1,73 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
*/
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include "../common/common.h"
static void i2c_write_start_seq(void)
{
struct fsl_i2c_base *base;
base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
CONFIG_SYS_FSL_I2C_OFFSET);
udelay(DELAY_ABORT_SEQ);
out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
out_8(&base->cr, (I2C_CR_MEN));
}
int i2c_make_abort(void)
{
struct fsl_i2c_base *base;
base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR +
CONFIG_SYS_FSL_I2C_OFFSET);
uchar last;
int nbr_read = 0;
int i = 0;
int ret = 0;
/* wait after each operation to finsh with a delay */
out_8(&base->cr, (I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA));
udelay(DELAY_ABORT_SEQ);
in_8(&base->dr);
udelay(DELAY_ABORT_SEQ);
last = in_8(&base->dr);
nbr_read++;
/*
* do read until the last bit is 1, but stop if the full eeprom is
* read.
*/
while (((last & 0x01) != 0x01) &&
(nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
udelay(DELAY_ABORT_SEQ);
last = in_8(&base->dr);
nbr_read++;
}
if ((last & 0x01) != 0x01)
ret = -2;
if ((last != 0xff) || (nbr_read > 1))
printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
nbr_read, last);
udelay(DELAY_ABORT_SEQ);
out_8(&base->cr, (I2C_CR_MEN));
udelay(DELAY_ABORT_SEQ);
/* clear status reg */
out_8(&base->sr, 0);
for (i = 0; i < 5; i++)
i2c_write_start_seq();
if (ret != 0)
printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
nbr_read, last);
return ret;
}

9
configs/kmcoge5ne_defconfig
View File

@@ -219,13 +219,10 @@ CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0xB0000801
CONFIG_SYS_OR4_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/kmeter1_defconfig
View File

@@ -185,13 +185,10 @@ CONFIG_SYS_OR1_PRELIM=0xFC000E25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xA0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/kmopti2_defconfig
View File

@@ -200,13 +200,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/kmsupx5_defconfig
View File

@@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/kmtepr2_defconfig
View File

@@ -199,13 +199,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/tuge1_defconfig
View File

@@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/tuxx1_defconfig
View File

@@ -201,13 +201,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E24
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=200000
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

8
include/configs/km/km-mpc83xx.h
View File

@@ -48,14 +48,6 @@
#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
/* I2C */
#define CFG_SYS_NUM_I2C_BUSES 4
#define CFG_SYS_I2C_MAX_HOPS 1
#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
{1, {I2C_NULL_HOP} } }
#if defined(CONFIG_CMD_NAND)
#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE
#endif