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clk: mediatek: mt8365: fix missing and out of order clocks

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Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2026-01-07 10:21:08 -06:00
committed by Tom Rini
parent 488c396e71
commit 32087f61ad
1 changed files with 17 additions and 15 deletions
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32
drivers/clk/mediatek/clk-mt8365.c
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@@ -80,7 +80,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
static const struct mtk_fixed_factor top_divs[] = {
PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2),
PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1),
PLL_FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", CLK_APMIXED_MAINPLL, 1, 2),
PLL_FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", CLK_APMIXED_MAINPLL, 1, 4),
PLL_FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", CLK_APMIXED_MAINPLL, 1, 8),
@@ -110,7 +110,6 @@ static const struct mtk_fixed_factor top_divs[] = {
PLL_FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", CLK_APMIXED_UNIVPLL, 1, 20),
PLL_FACTOR(CLK_TOP_MMPLL, "mmpll_ck", CLK_APMIXED_MMPLL, 1, 1),
PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
PLL_FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", CLK_APMIXED_MFGPLL, 1, 1),
PLL_FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", CLK_APMIXED_LVDSPLL, 1, 2),
PLL_FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", CLK_APMIXED_LVDSPLL, 1, 4),
PLL_FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", CLK_APMIXED_LVDSPLL, 1, 8),
@@ -128,6 +127,7 @@ static const struct mtk_fixed_factor top_divs[] = {
PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8),
PLL_FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", CLK_XTAL, 1, 2),
PLL_FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", CLK_APMIXED_MSDCPLL, 1, 1),
PLL_FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", CLK_APMIXED_MSDCPLL, 1, 2),
PLL_FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", CLK_APMIXED_DSPPLL, 1, 1),
@@ -484,7 +484,7 @@ static const struct mtk_composite top_muxes[] = {
static const struct mtk_clk_tree mt8365_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.fdivs_offs = CLK_TOP_SYSPLL_D2,
.fdivs_offs = CLK_TOP_MFGPLL,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
.fclks = top_fixed_clks,
@@ -540,16 +540,6 @@ static const struct mtk_gate_regs top2_cg_regs = {
}
static const struct mtk_gate top_clk_gates[] = {
GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0),
GATE_TOP2(CLK_TOP_AUD_I2S1_M, CLK_TOP_APLL12_CK_DIV1, 1),
GATE_TOP2(CLK_TOP_AUD_I2S2_M, CLK_TOP_APLL12_CK_DIV2, 2),
@@ -559,6 +549,16 @@ static const struct mtk_gate top_clk_gates[] = {
GATE_TOP2(CLK_TOP_AUD_TDMIN_M, CLK_TOP_APLL12_CK_DIV5, 6),
GATE_TOP2(CLK_TOP_AUD_TDMIN_B, CLK_TOP_APLL12_CK_DIV5B, 7),
GATE_TOP2(CLK_TOP_AUD_SPDIF_M, CLK_TOP_APLL12_CK_DIV6, 8),
GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4, 8),
GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4, 9),
GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, CLK_TOP_LVDSTX_CLKDIG_CTS, 20),
GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, CLK_TOP_VPLL_DPIX, 21),
GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
};
/* infracfg */
@@ -648,6 +648,7 @@ static const struct mtk_gate ifr_clks[] = {
GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
GATE_IFR3(CLK_IFR_AUXADC, CLK_TOP_CLK26M, 10),
GATE_IFR3(CLK_IFR_CPUM, CLK_TOP_AXI_SEL, 11),
GATE_IFR3(CLK_IFR_AUXADC_MD, CLK_TOP_CLK26M, 14),
GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
@@ -669,6 +670,7 @@ static const struct mtk_gate ifr_clks[] = {
GATE_IFR5(CLK_IFR_PWRAP_TMR, CLK_TOP_CLK26M, 12),
GATE_IFR5(CLK_IFR_PWRAP_SPI, CLK_TOP_CLK26M, 13),
GATE_IFR5(CLK_IFR_PWRAP_SYS, CLK_TOP_CLK26M, 14),
GATE_IFR5(CLK_IFR_MCU_PM_BK, CLK_TOP_AXI_SEL, 16),
GATE_IFR5(CLK_IFR_IRRX_26M, CLK_TOP_CLK26M, 22),
GATE_IFR5(CLK_IFR_IRRX_32K, CLK_TOP_CLK32K, 23),
GATE_IFR5(CLK_IFR_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
@@ -680,8 +682,8 @@ static const struct mtk_gate ifr_clks[] = {
GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
/* IFR6 */
GATE_IFR6(CLK_IFR_NFIECC, CLK_TOP_NFIECC_SEL, 0),
GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 1),
GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 2),
GATE_IFR6(CLK_IFR_NFIECC_BK, CLK_TOP_NFI2X_SEL, 1),
GATE_IFR6(CLK_IFR_NFI1X_BK, CLK_TOP_NFI2X_SEL, 2),
GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),