First set of u-boot-at91 fixes for the 2025.10 cycle:

This set includes smatch fixes for clocks and mmc and one QSPI fix.
This commit is contained in:
Tom Rini
2025-08-26 08:30:21 -06:00
6 changed files with 36 additions and 24 deletions

View File

@@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)
{
struct clk_main *main = to_clk_main(clk);
void __iomem *reg = main->reg;
unsigned int tmp, index;
unsigned int tmp;
int index;
index = at91_clk_mux_val_to_index(main->clk_mux_table,
main->num_parents, AT91_CLK_ID_TO_DID(parent->id));

View File

@@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base,
{
struct clk_master *master;
struct clk *clk;
u32 val, index;
int ret;
u32 val;
int ret, index;
if (!base || !name || !num_parents || !parent_names ||
!mux_table || !clk_mux_table || id > MASTER_MAX_ID)

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@@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
int num_parents)
{
struct clk *clk;
int ret = -ENOMEM;
u32 val, i;
int ret = -ENOMEM, i;
u32 val;
if (!sckc || !name || !parent_names || num_parents != 2)
return ERR_PTR(-EINVAL);
@@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
clk = &sckc->clk;
ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name,
parent_names[val]);
if (ret)
if (ret) {
i--;
goto free;
}
return clk;

View File

@@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout *
atmel_hsmc_get_reg_layout(ofnode np)
{
int i;
const struct udevice_id *match;
const struct udevice_id *match = NULL;
const char *name;
int len;

View File

@@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
goto io_fail;
} while (!(status & MMCI_BIT(RXRDY)));
if (status & MMCI_BIT(RXRDY)) {
*data = readl(&mci->rdr);
status = 0;
}
*data = readl(&mci->rdr);
status = 0;
io_fail:
return status;
}
@@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
goto io_fail;
} while (!(status & MMCI_BIT(TXRDY)));
if (status & MMCI_BIT(TXRDY)) {
writel(*data, &mci->tdr);
status = 0;
}
writel(*data, &mci->tdr);
status = 0;
io_fail:
return status;
}
@@ -265,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
mci_set_blklen(mci, data->blocksize);
if (data) {
mci_set_blklen(mci, data->blocksize);
/* For multi blocks read/write, set the block register */
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
&mci->blkr);
/* For multi blocks read/write, set the block register */
if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
&mci->blkr);
}
/* Send the command */
writel(cmd->cmdarg, &mci->argr);

View File

@@ -615,7 +615,8 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
static int atmel_qspi_transfer(struct atmel_qspi *aq,
const struct spi_mem_op *op, u32 offset)
{
u32 sr, imr;
u32 imr, val = 0;
unsigned long timeout;
/* Skip to the final steps if there is no data */
if (op->data.nbytes) {
@@ -636,8 +637,16 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq,
/* Poll INSTruction End and Chip Select Rise flags. */
imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
ATMEL_QSPI_TIMEOUT);
timeout = timer_get_us() + ATMEL_QSPI_TIMEOUT;
while (1) {
val |= readl(aq->regs + QSPI_SR) & imr;
if ((val & imr) == imr)
return 0;
if (time_after(timer_get_us(), timeout))
return -ETIMEDOUT;
}
}
static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,