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https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge tag 'u-boot-at91-fixes-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2025.10 cycle: This set includes smatch fixes for clocks and mmc and one QSPI fix.
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@@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_main *main = to_clk_main(clk);
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void __iomem *reg = main->reg;
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unsigned int tmp, index;
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unsigned int tmp;
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int index;
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index = at91_clk_mux_val_to_index(main->clk_mux_table,
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main->num_parents, AT91_CLK_ID_TO_DID(parent->id));
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@@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base,
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{
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struct clk_master *master;
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struct clk *clk;
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u32 val, index;
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int ret;
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u32 val;
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int ret, index;
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if (!base || !name || !num_parents || !parent_names ||
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!mux_table || !clk_mux_table || id > MASTER_MAX_ID)
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@@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
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int num_parents)
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{
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struct clk *clk;
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int ret = -ENOMEM;
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u32 val, i;
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int ret = -ENOMEM, i;
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u32 val;
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if (!sckc || !name || !parent_names || num_parents != 2)
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return ERR_PTR(-EINVAL);
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@@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc,
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clk = &sckc->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name,
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parent_names[val]);
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if (ret)
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if (ret) {
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i--;
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goto free;
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}
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return clk;
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@@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout *
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atmel_hsmc_get_reg_layout(ofnode np)
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{
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int i;
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const struct udevice_id *match;
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const struct udevice_id *match = NULL;
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const char *name;
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int len;
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@@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
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goto io_fail;
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} while (!(status & MMCI_BIT(RXRDY)));
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if (status & MMCI_BIT(RXRDY)) {
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*data = readl(&mci->rdr);
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status = 0;
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}
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*data = readl(&mci->rdr);
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status = 0;
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io_fail:
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return status;
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}
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@@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
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goto io_fail;
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} while (!(status & MMCI_BIT(TXRDY)));
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if (status & MMCI_BIT(TXRDY)) {
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writel(*data, &mci->tdr);
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status = 0;
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}
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writel(*data, &mci->tdr);
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status = 0;
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io_fail:
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return status;
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}
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@@ -265,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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/* Figure out the transfer arguments */
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cmdr = mci_encode_cmd(cmd, data, &error_flags);
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mci_set_blklen(mci, data->blocksize);
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if (data) {
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mci_set_blklen(mci, data->blocksize);
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/* For multi blocks read/write, set the block register */
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
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|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
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writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
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&mci->blkr);
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/* For multi blocks read/write, set the block register */
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if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
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cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
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writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
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&mci->blkr);
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}
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/* Send the command */
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writel(cmd->cmdarg, &mci->argr);
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@@ -615,7 +615,8 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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static int atmel_qspi_transfer(struct atmel_qspi *aq,
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const struct spi_mem_op *op, u32 offset)
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{
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u32 sr, imr;
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u32 imr, val = 0;
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unsigned long timeout;
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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@@ -636,8 +637,16 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq,
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/* Poll INSTruction End and Chip Select Rise flags. */
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imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
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return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
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ATMEL_QSPI_TIMEOUT);
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timeout = timer_get_us() + ATMEL_QSPI_TIMEOUT;
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while (1) {
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val |= readl(aq->regs + QSPI_SR) & imr;
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if ((val & imr) == imr)
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return 0;
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if (time_after(timer_get_us(), timeout))
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return -ETIMEDOUT;
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}
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}
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static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
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