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video: Always compile cache flushing code

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The dcache flushing code path was conditional on ARM && !DCACHE config
options. However, dcaches exist on other platforms as well and may need
clearing if their driver requires it.

Simplify the compile logic and always enable the dcache flush logic in
the video core. That way, drivers can always rely on it to call the arch
specific callbacks.

This will increase code size for non-ARM platforms with CONFIG_VIDEO=y
slightly.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/20230821135111.3558478-13-alpernebiyasak@gmail.com/
Added workaround for CONFIG_SYS_CACHELINE_SIZE for ibex-ast2700:
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Alexander Graf
2023-01-03 22:50:03 +01:00
committed by Simon Glass
parent 70dfd67478
commit 369c6a6c35
1 changed files with 13 additions and 12 deletions
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25
drivers/video/video-uclass.c
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@@ -394,18 +394,25 @@ void video_damage(struct udevice *vid, int x, int y, int width, int height)
}
#endif
#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void video_flush_dcache(struct udevice *vid, bool use_copy)
{
struct video_priv *priv = dev_get_uclass_priv(vid);
ulong fb = use_copy ? (ulong)priv->copy_fb : (ulong)priv->fb;
uint cacheline_size = 32;
#ifdef CONFIG_SYS_CACHELINE_SIZE
cacheline_size = CONFIG_SYS_CACHELINE_SIZE;
#endif
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
if (!priv->flush_dcache)
return;
if (!IS_ENABLED(CONFIG_VIDEO_DAMAGE)) {
flush_dcache_range(fb, ALIGN(fb + priv->fb_size,
CONFIG_SYS_CACHELINE_SIZE));
cacheline_size));
return;
}
@@ -419,14 +426,13 @@ static void video_flush_dcache(struct udevice *vid, bool use_copy)
ulong start = fb + (y * priv->line_length) + lstart;
ulong end = start + lend - lstart;
start = ALIGN_DOWN(start, CONFIG_SYS_CACHELINE_SIZE);
end = ALIGN(end, CONFIG_SYS_CACHELINE_SIZE);
start = ALIGN_DOWN(start, cacheline_size);
end = ALIGN(end, cacheline_size);
flush_dcache_range(start, end);
}
}
}
#endif
static void video_flush_copy(struct udevice *vid)
{
@@ -469,17 +475,12 @@ int video_sync(struct udevice *vid, bool force)
get_timer(priv->last_sync) < CONFIG_VIDEO_SYNC_MS)
return 0;
/*
* flush_dcache_range() is declared in common.h but it seems that some
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
video_flush_dcache(vid, false);
if (IS_ENABLED(CONFIG_VIDEO_COPY))
video_flush_dcache(vid, true);
#elif defined(CONFIG_VIDEO_SANDBOX_SDL)
#if defined(CONFIG_VIDEO_SANDBOX_SDL)
sandbox_sdl_sync(priv->fb);
#endif
priv->last_sync = get_timer(0);