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sunxi: mmc: Fix T113-s3 MMC clock divider

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On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
But we have still the hidden divisor of 2 in the MMC mod clock, so
need to explicitly compensate for that on those SoCs.

This leads to the actually programmed clock rate to be double compared
to before, which increases the MMC performance on those SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Andre Przywara
2025-02-26 11:37:11 +00:00
parent c0c122bfa1
commit 46c291e147
1 changed files with 7 additions and 0 deletions
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7
drivers/mmc/sunxi_mmc.c
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@@ -92,6 +92,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
pll = CCM_MMC_CTRL_PLL6;
pll_hz = clock_get_pll6();
#endif
/*
* On the D1/R528/T113 mux source 1 refers to PLL_PERIPH0(1x),
* like for the older SoCs. However we still have the hidden
* divider of 2x, so compensate for that here.
*/
if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
pll_hz /= 2;
}
div = pll_hz / hz;