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sunxi: Parameterize some of H616 DDR3 timings

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Currently twr2rd, trd2wr and twtp are constants, but according to
vendor driver they are calculated from other values. Do that here too,
in preparation for later introduction of new parameter.

While at it, introduce constant for t_wr_lat, which was incorrectly
calculated from tcl before.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Jernej Skrabec
2023-04-10 10:21:18 +02:00
committed by Andre Przywara
parent b3cb03cf79
commit 4a967cb95f
1 changed files with 5 additions and 4 deletions
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9
arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c
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@@ -48,10 +48,11 @@ void mctl_set_timing_params(struct dram_para *para)
u8 tcl = 7; /* JEDEC: CL / 2 => 6 */
u8 tcwl = 5; /* JEDEC: 8 */
u8 t_rdata_en = 9; /* ? */
u8 t_wr_lat = 5; /* ? */
u8 twtp = 14; /* (WL + BL / 2 + tWR) / 2 */
u8 twr2rd = trtp + 7; /* (WL + BL / 2 + tWTR) / 2 */
u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */
u8 twtp = tcl + 2 + tcwl; /* (WL + BL / 2 + tWR) / 2 */
u8 twr2rd = trtp + 2 + tcwl; /* (WL + BL / 2 + tWTR) / 2 */
u8 trd2wr = tcl + 3 - tcwl; /* (RL + BL / 2 + 2 - WL) / 2 */
/* set DRAM timing */
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
@@ -85,7 +86,7 @@ void mctl_set_timing_params(struct dram_para *para)
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
/* Configure DFI timing */
writel((tcl - 2) | 0x2000000 | (t_rdata_en << 16) | 0x808000,
writel(t_wr_lat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
&mctl_ctl->dfitmg0);
writel(0x100202, &mctl_ctl->dfitmg1);