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Merge patch series "arm: mach-k3: j721s2: Provide a way to obtain boot device for non SPLs"

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This series from Dominik Haller <d.haller@phytec.de> provides a way for
TI K3 platforms to determine their boot device outside of SPL and then
adds support for the PHYTEC phyCORE-AM68x/TDA4x SoM.

Link: https://lore.kernel.org/r/20260116014116.767555-1-d.haller@phytec.de
This commit is contained in:
Tom Rini
2026-02-02 13:39:52 -06:00
parent 22129bf473 2a6935eee2
commit 4b287e0a3a
22 changed files with 8666 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4387
arch/arm/dts/k3-am68-ddr-phycore-som-lp4-4266-4gb.dtsi Normal file
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21
arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi Normal file
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@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Dominik Haller <d.haller@phytec.de>
*
* https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/
*/
#include "k3-am68-phycore-som-binman.dtsi"
&cbass_main {
bootph-all;
};
&watchdog1 {
status = "disabled";
};
&mcu_uart0 {
bootph-all;
};

430
arch/arm/dts/k3-am68-phycore-som-binman.dtsi Normal file
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@@ -0,0 +1,430 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Based on k3-j721s2-binman.dtsi
*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Dominik Haller <d.haller@phytec.de>
*/
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_PHYCORE_AM68X_R5
&binman {
tiboot3-am68x-hs-phycore-som.bin {
filename = "tiboot3-am68x-hs-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
<&combined_dm_cfg>, <&sysfw_inner_cert>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_fs_enc>;
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x41c80000>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin";
type = "blob-ext";
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin";
type = "blob-ext";
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-am68x-hs-fs-phycore-som.bin {
filename = "tiboot3-am68x-hs-fs-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_fs_enc_fs>;
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <CONFIG_SPL_TEXT_BASE>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x41c80000>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin";
type = "blob-ext";
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin";
type = "blob-ext";
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-am68x-gp-phycore-som.bin {
filename = "tiboot3-am68x-gp-phycore-som.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <CONFIG_SPL_TEXT_BASE>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x41c80000>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin";
type = "blob-ext";
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM68X_A72
#define SPL_AM68_PHYBOARD_IZAR_DTB "spl/dts/ti/k3-am68-phyboard-izar.dtb"
#define AM68_PHYBOARD_IZAR_DTB "u-boot.dtb"
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
atf {
ti-secure {
auth-in-place = <0xa02>;
firewall-257-0 {
/* cpu_0_cpu_0_msmc Background Firewall */
insert-template = <&firewall_bg_1>;
id = <257>;
region = <0>;
};
firewall-257-1 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <257>;
region = <1>;
};
firewall-284-0 {
/* dru_0_msmc Background Firewall */
insert-template = <&firewall_bg_3>;
id = <284>;
region = <0>;
};
firewall-284-1 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <284>;
region = <1>;
};
/* firewall-5140-0 {
* nb_slv0__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-5140-1 {
/* nb_slv0__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <5140>;
region = <1>;
};
/* firewall-5140-0 {
* nb_slv1__mem0 Background Firewall
* Already configured by the secure entity
* };
*/
firewall-5141-1 {
/* nb_slv1__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_atf_fg>;
id = <5141>;
region = <1>;
};
};
};
tee {
ti-secure {
auth-in-place = <0xa02>;
firewall-257-2 {
/* cpu_0_cpu_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <257>;
region = <2>;
};
firewall-284-2 {
/* dru_0_msmc Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <284>;
region = <2>;
};
firewall-5142-0 {
/* nb_slv2__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5142>;
region = <0>;
};
firewall-5142-1 {
/* nb_slv2__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5142>;
region = <1>;
};
firewall-5143-0 {
/* nb_slv3__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5143>;
region = <0>;
};
firewall-5143-1 {
/* nb_slv3__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5143>;
region = <1>;
};
firewall-5144-0 {
/* nb_slv4__mem0 Background Firewall - 0 */
insert-template = <&firewall_bg_3>;
id = <5144>;
region = <0>;
};
firewall-5144-1 {
/* nb_slv4__mem0 Foreground Firewall */
insert-template = <&firewall_armv8_optee_fg>;
id = <5144>;
region = <1>;
};
};
};
dm {
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: ti-dm {
filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
fdt-0 {
description = "k3-am68-phyboard-izar";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am68_phyboard_izar_dtb>;
keyfile = "custMpk.pem";
};
spl_am68_phyboard_izar_dtb: blob-ext {
filename = SPL_AM68_PHYBOARD_IZAR_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am68-phyboard-izar";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for phyBOARD Izar AM68x";
};
fdt-0 {
description = "k3-am68-phyboard-izar";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am68_phyboard_izar_dtb>;
keyfile = "custMpk.pem";
};
am68_phyboard_izar_dtb: blob-ext {
filename = AM68_PHYBOARD_IZAR_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am68-phyboard-izar";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
ti-dm {
filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
};
};
fdt-0 {
description = "k3-am68-phyboard-izar";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am68_phyboard_izar_dtb_unsigned: blob {
filename = SPL_AM68_PHYBOARD_IZAR_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am68-phyboard-izar";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for phyBOARD Izar AM68x";
};
fdt-0 {
description = "k3-am68-phyboard-izar";
type = "flat_dt";
arch = "arm";
compression = "none";
am68_phyboard_izar_unsigned: blob {
filename = AM68_PHYBOARD_IZAR_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am68-phyboard-izar";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

20
arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts Normal file
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@@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Dominik Haller <d.haller@phytec.de>
*
* https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/
*/
/dts-v1/;
#include "k3-am68-phyboard-izar.dts"
#include "k3-am68-ddr-phycore-som-lp4-4266-4gb.dtsi"
#include "k3-j721s2-ddr.dtsi"
#include "k3-am68-phyboard-izar-u-boot.dtsi"
#include "k3-j721s2-r5.dtsi"
&wkup_vtm0 {
bootph-pre-ram;
vdd-supply-2 = <&vdd_cpu_avs>;
};

20
arch/arm/mach-k3/j721s2/Kconfig
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@@ -29,8 +29,28 @@ config TARGET_J721S2_R5_EVM
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
config TARGET_PHYCORE_AM68X_A72
bool "PHYTEC phyCORE-AM68x running on A72"
select ARM64
select BOARD_LATE_INIT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
imply OF_UPSTREAM
config TARGET_PHYCORE_AM68X_R5
bool "PHYTEC phyCORE-AM68x running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
endchoice
source "board/ti/j721s2/Kconfig"
source "board/phytec/phycore_am68x/Kconfig"
endif

1
arch/arm/mach-k3/j721s2/Makefile
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@@ -5,3 +5,4 @@
obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o
obj-$(CONFIG_XPL_BUILD) += j721s2_init.o
obj-y += boot.o

76
arch/arm/mach-k3/j721s2/boot.c Normal file
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@@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/j721s2_spl.h>
static u32 __get_backup_bootmedia(u32 main_devstat)
{
u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
switch (bkup_boot) {
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC2:
{
u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
if (port == 0x0)
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_MMC2;
}
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
}
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
{
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
BOOT_MODE_B_SHIFT;
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
bootmode == BOOT_DEVICE_XSPI)
bootmode = BOOT_DEVICE_SPI;
if (bootmode == BOOT_DEVICE_MMC2) {
u32 port = (main_devstat &
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
if (port == 0x0)
bootmode = BOOT_DEVICE_MMC1;
}
return bootmode;
}
u32 get_boot_device(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
u32 main_devstat;
u32 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
if (wkup_devstat & WKUP_DEVSTAT_MCU_ONLY_MASK) {
printf("ERROR: MCU only boot is not yet supported\n");
return BOOT_DEVICE_RAM;
}
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
if (bootindex == K3_PRIMARY_BOOTMODE)
return __get_primary_bootmedia(main_devstat, wkup_devstat);
else
return __get_backup_bootmedia(main_devstat);
}

68
arch/arm/mach-k3/j721s2/j721s2_init.c
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@@ -361,73 +361,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
}
}
static u32 __get_backup_bootmedia(u32 main_devstat)
{
u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
switch (bkup_boot) {
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC2:
{
u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
if (port == 0x0)
return BOOT_DEVICE_MMC1;
return BOOT_DEVICE_MMC2;
}
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
}
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
{
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
BOOT_MODE_B_SHIFT;
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
bootmode == BOOT_DEVICE_XSPI)
bootmode = BOOT_DEVICE_SPI;
if (bootmode == BOOT_DEVICE_MMC2) {
u32 port = (main_devstat &
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
if (port == 0x0)
bootmode = BOOT_DEVICE_MMC1;
}
return bootmode;
}
u32 spl_boot_device(void)
{
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
u32 main_devstat;
if (wkup_devstat & WKUP_DEVSTAT_MCU_ONLY_MASK) {
printf("ERROR: MCU only boot is not yet supported\n");
return BOOT_DEVICE_RAM;
}
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
if (bootindex == K3_PRIMARY_BOOTMODE)
return __get_primary_bootmedia(main_devstat, wkup_devstat);
else
return __get_backup_bootmedia(main_devstat);
return get_boot_device();
}

41
board/phytec/phycore_am68x/Kconfig Normal file
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@@ -0,0 +1,41 @@
# SPDX-License-Identifier: GPL-2.0-only OR MIT
#
# Copyright (C) 2025 PHYTEC Messtechnik GmbH
# Author: Dominik Haller <d.haller@phytec.de>
if TARGET_PHYCORE_AM68X_A72
config SYS_BOARD
default "phycore_am68x"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am68x"
config ENV_SOURCE_FILE
default "phycore_am68x"
source "board/phytec/common/Kconfig"
endif
if TARGET_PHYCORE_AM68X_R5
config SYS_BOARD
default "phycore_am68x"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am68x"
config ENV_SOURCE_FILE
default "phycore_am68x"
source "board/phytec/common/Kconfig"
source "board/phytec/common/k3/Kconfig"
endif

14
board/phytec/phycore_am68x/MAINTAINERS Normal file
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@@ -0,0 +1,14 @@
phyCORE-AM68x
M: Dominik Haller <d.haller@phytec.de>
L: upstream@lists.phytec.de
W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
S: Maintained
F: arch/arm/dts/k3-am68-phycore-som-ddr4-4gb.dtsi
F: arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi
F: arch/arm/dts/k3-am68-phycore-som-binman.dtsi
F: arch/arm/dts/k3-am68-r5-phycore-som-4gb.dts
F: board/phytec/phycore_am68x/
F: configs/phycore_am68x_a72_defconfig
F: configs/phycore_am68x_r5_defconfig
F: doc/board/phytec/phycore-am68x.rst
F: include/configs/phycore_am68x.h

6
board/phytec/phycore_am68x/Makefile Normal file
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@@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#
# Copyright (C) 2025 PHYTEC Messtechnik GmbH
# Author: Dominik Haller <d.haller@phytec.de>
obj-y += phycore-am68x.o

36
board/phytec/phycore_am68x/board-cfg.yaml Normal file
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@@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Board configuration for J721S2
#
---
board-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
control:
subhdr:
magic: 0xC1D3
size: 7
main_isolation_enable: 0x5A
main_isolation_hostid: 0x2
secproxy:
subhdr:
magic: 0x1207
size: 7
scaling_factor: 0x1
scaling_profile: 0x1
disable_main_nav_secure_proxy: 0
msmc:
subhdr:
magic: 0xA5C3
size: 5
msmc_cache_size: 0x0
debug_cfg:
subhdr:
magic: 0x020C
size: 8
trace_dst_enables: 0x00
trace_src_enables: 0x00

97
board/phytec/phycore_am68x/phycore-am68x.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2025 PHYTEC Messtechnik GmbH
* Author: Dominik Haller <d.haller@phytec.de>
*
* https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
*/
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <spl.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/root.h>
#include <asm/arch/k3-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
/* Limit RAM used by U-Boot to the DDR low region */
if (gd->ram_top > 0x100000000)
return 0x100000000;
#endif
return gd->ram_top;
}
int dram_init(void)
{
s32 ret;
ret = fdtdec_setup_mem_size_base_lowest();
if (ret)
printf("Error setting up mem size and base. %d\n", ret);
return ret;
}
int dram_init_banksize(void)
{
s32 ret;
ret = fdtdec_setup_memory_banksize();
if (ret)
printf("Error setting up memory banksize. %d\n", ret);
return ret;
}
#if defined(CONFIG_XPL_BUILD)
void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
void spl_board_init(void)
{
struct udevice *dev;
int ret;
if (IS_ENABLED(CONFIG_ESM_K3)) {
const char * const esms[] = {"esm@700000", "esm@40800000", "esm@42080000"};
for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
&dev);
if (ret) {
printf("MISC init for %s failed: %d\n", esms[i], ret);
break;
}
}
}
if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
&dev);
if (ret)
printf("ESM PMIC init failed: %d\n", ret);
}
}

22
board/phytec/phycore_am68x/phycore_am68x.env Normal file
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fdtaddr=0x88000000
loadaddr=0x82000000
scriptaddr=0x89100000
fdt_addr_r=0x88000000
kernel_addr_r=0x82000000
ramdisk_addr_r=0x88080000
fdtoverlay_addr_r=0x89000000
fit_addr_r=0x90000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
mmcdev=1
mmcroot=2
mmcpart=1
console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x02880000
spi_fdt_addr=0x700000
spi_image_addr=0x800000
spi_ramdisk_addr=0x2200000
bootmeths=script efi extlinux pxe
boot_targets=mmc1 mmc0 spi_flash dhcp

12
board/phytec/phycore_am68x/pm-cfg.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Power management configuration for J721S2
#
---
pm-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1

2523
board/phytec/phycore_am68x/rm-cfg.yaml Normal file
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379
board/phytec/phycore_am68x/sec-cfg.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Security management configuration for J721S2
#
---
sec-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
processor_acl_list:
subhdr:
magic: 0xF1EA
size: 164
proc_acl_entries:
- # 1
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 2
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 3
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 4
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 5
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 6
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 7
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 8
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 9
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 10
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 11
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 12
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 13
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 14
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 15
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 16
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 17
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 18
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 19
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 20
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 21
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 22
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 23
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 24
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 25
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 26
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 27
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 28
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 29
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 30
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 31
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 32
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
host_hierarchy:
subhdr:
magic: 0x8D27
size: 68
host_hierarchy_entries:
- # 1
host_id: 0
supervisor_host_id: 0
- # 2
host_id: 0
supervisor_host_id: 0
- # 3
host_id: 0
supervisor_host_id: 0
- # 4
host_id: 0
supervisor_host_id: 0
- # 5
host_id: 0
supervisor_host_id: 0
- # 6
host_id: 0
supervisor_host_id: 0
- # 7
host_id: 0
supervisor_host_id: 0
- # 8
host_id: 0
supervisor_host_id: 0
- # 9
host_id: 0
supervisor_host_id: 0
- # 10
host_id: 0
supervisor_host_id: 0
- # 11
host_id: 0
supervisor_host_id: 0
- # 12
host_id: 0
supervisor_host_id: 0
- # 13
host_id: 0
supervisor_host_id: 0
- # 14
host_id: 0
supervisor_host_id: 0
- # 15
host_id: 0
supervisor_host_id: 0
- # 16
host_id: 0
supervisor_host_id: 0
- # 17
host_id: 0
supervisor_host_id: 0
- # 18
host_id: 0
supervisor_host_id: 0
- # 19
host_id: 0
supervisor_host_id: 0
- # 20
host_id: 0
supervisor_host_id: 0
- # 21
host_id: 0
supervisor_host_id: 0
- # 22
host_id: 0
supervisor_host_id: 0
- # 23
host_id: 0
supervisor_host_id: 0
- # 24
host_id: 0
supervisor_host_id: 0
- # 25
host_id: 0
supervisor_host_id: 0
- # 26
host_id: 0
supervisor_host_id: 0
- # 27
host_id: 0
supervisor_host_id: 0
- # 28
host_id: 0
supervisor_host_id: 0
- # 29
host_id: 0
supervisor_host_id: 0
- # 30
host_id: 0
supervisor_host_id: 0
- # 31
host_id: 0
supervisor_host_id: 0
- # 32
host_id: 0
supervisor_host_id: 0
otp_config:
subhdr:
magic: 0x4081
size: 69
otp_entry:
- # 1
host_id: 0
host_perms: 0
- # 2
host_id: 0
host_perms: 0
- # 3
host_id: 0
host_perms: 0
- # 4
host_id: 0
host_perms: 0
- # 5
host_id: 0
host_perms: 0
- # 6
host_id: 0
host_perms: 0
- # 7
host_id: 0
host_perms: 0
- # 8
host_id: 0
host_perms: 0
- # 9
host_id: 0
host_perms: 0
- # 10
host_id: 0
host_perms: 0
- # 11
host_id: 0
host_perms: 0
- # 12
host_id: 0
host_perms: 0
- # 13
host_id: 0
host_perms: 0
- # 14
host_id: 0
host_perms: 0
- # 15
host_id: 0
host_perms: 0
- # 16
host_id: 0
host_perms: 0
- # 17
host_id: 0
host_perms: 0
- # 18
host_id: 0
host_perms: 0
- # 19
host_id: 0
host_perms: 0
- # 20
host_id: 0
host_perms: 0
- # 21
host_id: 0
host_perms: 0
- # 22
host_id: 0
host_perms: 0
- # 23
host_id: 0
host_perms: 0
- # 24
host_id: 0
host_perms: 0
- # 25
host_id: 0
host_perms: 0
- # 26
host_id: 0
host_perms: 0
- # 27
host_id: 0
host_perms: 0
- # 28
host_id: 0
host_perms: 0
- # 29
host_id: 0
host_perms: 0
- # 30
host_id: 0
host_perms: 0
- # 31
host_id: 0
host_perms: 0
- # 32
host_id: 0
host_perms: 0
write_host_id: 0
dkek_config:
subhdr:
magic: 0x5170
size: 12
allowed_hosts: [128, 0, 0, 0]
allow_dkek_export_tisci: 0x5A
rsvd: [0, 0, 0]
sa2ul_cfg:
subhdr:
magic: 0x23BE
size: 0
auth_resource_owner: 0
enable_saul_psil_global_config_writes: 0
rsvd: [0, 0]
sec_dbg_config:
subhdr:
magic: 0x42AF
size: 16
allow_jtag_unlock: 0x0
allow_wildcard_unlock: 0x0
allowed_debug_level_rsvd: 0
rsvd: 0
min_cert_rev: 0x0
jtag_unlock_hosts: [0, 0, 0, 0]
sec_handover_cfg:
subhdr:
magic: 0x608F
size: 10
handover_msg_sender: 0
handover_to_host_id: 0
rsvd: [0, 0, 0, 0]

204
configs/phycore_am68x_a72_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721S2=y
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_PHYTEC_SOM_DETECTION_BLOCKS=y
CONFIG_TARGET_PHYCORE_AM68X_A72=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-phyboard-izar"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_STACK_R=y
CONFIG_ENV_OFFSET_REDUND=0x6c0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_LOGLEVEL=7
# CONFIG_BOARD_INIT is not set
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_SMC=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_REDUNDANT=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_DEVICE_INDEX=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_SPL_DFU=y

184
configs/phycore_am68x_r5_defconfig Normal file
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CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721S2=y
CONFIG_K3_EARLY_CONS=y
CONFIG_K3_QOS=y
CONFIG_TARGET_PHYCORE_AM68X_R5=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am68-r5-phycore-som-4gb"
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x41c76000
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SIZE_LIMIT=0x80000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_BOARD_INIT is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_CMD_ASKENV=y
CONFIG_ENV_MMC_EMMC_HW_PARTITION=1
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_K3_AVS0=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65941=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_TPS65941=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_PANIC_HANG=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y

1
doc/board/phytec/index.rst
View File

@@ -12,5 +12,6 @@ PHYTEC
phycore-am62x
phycore-am62ax
phycore-am64x
phycore-am68x
phycore-imx8mm
phycore-imx8mp

166
doc/board/phytec/phycore-am68x.rst Normal file
View File

@@ -0,0 +1,166 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Dominik Haller <d.haller@phytec.de>
phyCORE-AM68x/TDA4x
===================
The `phyCORE-AM68x/TDA4x <https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/>`_
is a SoM (System on Module) populated with AM68x or TDA4x SoCs from TI's J721S2
family. It can be used in combination with different carrier boards. This module
can come with different sizes and models for DDR, eMMC, ETH-PHY, SPI NOR Flash
and an optional SN65DSI83 DSI->LVDS transceiver using DSI0.
A development Kit, called `phyBOARD-Izar <https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/>`_
is used as a carrier board reference design around the AM68x/TDA4x SoM.
Quickstart
----------
* Download sources and TI firmware blobs
* Build Trusted Firmware-A
* Build OP-TEE
* Build U-Boot for the R5
* Build U-Boot for the A72
* Create bootable uSD Card
* Boot
Sources
-------
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_firmwares
:end-before: .. k3_rst_include_end_tifsstub
Build procedure
---------------
Setup the environment variables:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. code-block:: bash
$ export UBOOT_CFG_CORTEXR=phycore_am68x_r5_defconfig
$ export UBOOT_CFG_CORTEXA=phycore_am68x_a72_defconfig
$ export TFA_BOARD=generic
$ export TFA_EXTRA_ARGS="K3_USART=0x8"
$ export OPTEE_PLATFORM=k3-j784s4
$ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
1. Trusted Firmware-A:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
3. U-Boot:
* 3.1 R5:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 3.2 A72:
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
uSD Card creation
-----------------
Use fdisk to partition the uSD card. The layout should look similar to:
.. code-block:: bash
$ sudo fdisk -l /dev/mmcblk0
Disk /dev/mmcblk0: 15 GB, 15913189376 bytes, 31080448 sectors
242816 cylinders, 4 heads, 32 sectors/track
Units: sectors of 1 * 512 = 512 bytes
Device Boot StartCHS EndCHS StartLBA EndLBA Sectors Size Id Type
/dev/mmcblk0p1 * 128,0,1 1023,3,32 16384 278527 262144 128M c Win95 FAT32 (LBA)
/dev/mmcblk0p2 1023,3,32 1023,3,32 278528 1693883 1415356 691M 83 Linux
Once partitioned, the boot partition has to be formatted with a FAT filesystem.
Assuming the uSD card is `/dev/mmcblk0`:
.. code-block:: bash
$ mkfs.vfat /dev/mmcblk0p1
To boot from a micro SD card on a HSFS device simply copy the following
artifacts to the FAT partition:
* tiboot3.bin from R5 build
* tispl.bin from Cortex-A build
* u-boot.img from Cortex-A build
Boot
----
Put the uSD card in the slot on the board and apply power. Check the serial
console for output.
Boot Modes
----------
The phyBOARD-Izar development kit supports booting from many different
interfaces. By default, the development kit is set to boot from the micro-SD
card. To change the boot device, DIP switches S8 and S7 can be used.
Boot switches should be changed with power off.
.. list-table:: Boot Modes
:widths: 16 16 16
:header-rows: 1
* - Switch Label
- SW8: 12345678
- SW7: 12345678
* - uSD
- 00000000
- 01000001
* - eMMC (FS/UDA)
- 00000000
- 10001011
* - eMMC (HW partitions)
- 00000010
- 10001011
* - OSPI0
- 00000010
- 00001100
.. include:: k3-common.rst
Further Information
-------------------
Please see :doc:`../ti/j721s2_evm` chapter for further J721S2 SoC family
related documentation.

25
include/configs/phycore_am68x.h Normal file
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
/*
* Configuration header file for PHYTEC phyCORE-AM68x
*
*/
#ifndef __PHYCORE_AM68X_H
#define __PHYCORE_AM68X_H
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
/* SPL Loader Configuration */
#if defined(CONFIG_TARGET_PHYCORE_AM68X_A72)
#define CFG_SYS_UBOOT_BASE 0x50280000
/* Image load address in RAM for DFU boot*/
#else
#define CFG_SYS_UBOOT_BASE 0x50080000
#endif
#define PHYCORE_AM6XX_FW_NAME_TIBOOT3 u"PHYCORE_AM68X_TIBOOT3"
#define PHYCORE_AM6XX_FW_NAME_SPL u"PHYCORE_AM68X_SPL"
#define PHYCORE_AM6XX_FW_NAME_UBOOT u"PHYCORE_AM68X_UBOOT"
#endif /* __PHYCORE_AM62AX_H */