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Merge tag 'u-boot-stm32-20240617' of https://source.denx.de/u-boot/custodians/u-boot-stm

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STM32MP1:
 - Ping IWDG on exit from PSCI suspend code
This commit is contained in:
Tom Rini
2024-06-17 09:26:13 -06:00
parent 7d602334f6 9968e8dbf3
commit 4d07da3333
1 changed files with 21 additions and 0 deletions
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21
arch/arm/mach-stm32mp/stm32mp1/psci.c
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@@ -808,6 +808,27 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
/*
* Make sure the OS would not get any spurious IWDG pretimeout IRQ
* right after the system wakes up. This may happen in case the SoC
* got woken up by another source than the IWDG pretimeout and the
* pretimeout IRQ arrived immediately afterward, but too late to be
* handled by the main loop above. In case either of the IWDG is
* enabled, ping it first and then return to the OS.
*/
/* Ping IWDG1 and ACK pretimer IRQ */
if (gic_enabled[4] & BIT(22)) {
writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR);
writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR);
}
/* Ping IWDG2 and ACK pretimer IRQ */
if (gic_enabled[4] & BIT(23)) {
writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
}
/*
* The system has resumed successfully. Rewrite LR register stored
* on stack with 'ep' value, so that on return from this PSCI call,