Merge tag 'u-boot-imx-next-20251229' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28866 - Swicth imx8ulp-evk to standard boot and OF_UPSTREAM. - Cleanup of the IPUv3 video driver. - Add support for the NXP FRDM-IMX91 board. - Make flash.bin target available on i.MX9. - Fix mxsfb pixel clock polarity.
2026-06-02 09:46:37 +03:00 · 2025-12-29 12:23:35 -06:00
parent 9235da9446 253a96ffb6
commit 4df43f4474
37 changed files with 10787 additions and 1798 deletions
--- a/9
+++ b/9
@@ -1778,14 +1778,18 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE
 SPL: spl/u-boot-spl.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

-#ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
-ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y)
+ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER),y)
+ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8),y)
 u-boot.cnt: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

 flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 else
+flash.bin: spl/u-boot-spl.bin FORCE
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+endif
+else
 ifeq ($(CONFIG_BINMAN),y)
 flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
 	$(call if_changed,binman)
@@ -1794,7 +1798,6 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
 endif
-#endif

 u-boot.uim: u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -881,9 +881,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qxp-mek.dtb \
 	imx8-capricorn-cxg3.dtb \

-dtb-$(CONFIG_ARCH_IMX8ULP) += \
-	imx8ulp-evk.dtb
-
 dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-data-modul-edm-sbc.dtb \
 	imx8mm-icore-mx8mm-ctouch2.dtb \
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -22,6 +22,14 @@
 	bootph-all;
 };

+&mu {
+	status = "disabled";
+};
+
+&wdog3 {
+	status = "disabled";
+};
+
 &per_bridge4 {
 	bootph-pre-ram;
 };
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-/dts-v1/;
-
-#include "imx8ulp.dtsi"
-
-/ {
-	model = "NXP i.MX8ULP EVK";
-	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
-
-	chosen {
-		stdout-path = &lpuart5;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0 0x80000000>;
-	};
-
-	clock_ext_rmii: clock-ext-rmii {
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "ext_rmii_clk";
-		#clock-cells = <0>;
-	};
-
-	clock_ext_ts: clock-ext-ts {
-		compatible = "fixed-clock";
-		/* External ts clock is 50MHZ from PHY on EVK board. */
-		clock-frequency = <50000000>;
-		clock-output-names = "ext_ts_clk";
-		#clock-cells = <0>;
-	};
-};
-
-&lpuart5 {
-	/* console */
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_lpuart5>;
-	pinctrl-1 = <&pinctrl_lpuart5>;
-	status = "okay";
-};
-
-&usdhc0 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_usdhc0>;
-	pinctrl-1 = <&pinctrl_usdhc0>;
-	non-removable;
-	bus-width = <8>;
-	status = "okay";
-};
-
-&fec {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_enet>;
-	pinctrl-1 = <&pinctrl_enet>;
-	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-		 <&pcc4 IMX8ULP_CLK_ENET>,
-		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
-		 <&clock_ext_rmii>;
-	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
-	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
-	assigned-clock-parents = <&clock_ext_ts>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy: ethernet-phy@1 {
-			reg = <1>;
-			micrel,led-mode = <1>;
-		};
-	};
-};
-
-&iomuxc1 {
-	pinctrl_enet: enetgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
-			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
-			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
-			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
-			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
-			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
-			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
-			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
-			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
-			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
-			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
-		>;
-	};
-
-	pinctrl_lpuart5: lpuart5grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
-			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
-		>;
-	};
-
-	pinctrl_usdhc0: usdhc0grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
-			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
-			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
-			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
-			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
-			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
-			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
-			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
-			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
-			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
-			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
-		>;
-	};
-};
-
-&wdog3 {
-	status = "disabled";
-};
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -1,476 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-#include <dt-bindings/clock/imx8ulp-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/imx8ulp-power.h>
-
-#include "imx8ulp-pinfunc.h"
-
-/ {
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		ethernet0 = &fec;
-		gpio0 = &gpiod;
-		gpio1 = &gpioe;
-		gpio2 = &gpiof;
-		mmc0 = &usdhc0;
-		mmc1 = &usdhc1;
-		mmc2 = &usdhc2;
-		serial0 = &lpuart4;
-		serial1 = &lpuart5;
-		serial2 = &lpuart6;
-		serial3 = &lpuart7;
-	};
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		A35_0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			next-level-cache = <&A35_L2>;
-		};
-
-		A35_1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			next-level-cache = <&A35_L2>;
-		};
-
-		A35_L2: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	gic: interrupt-controller@2d400000 {
-		compatible = "arm,gic-v3";
-		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
-		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
-		#interrupt-cells = <3>;
-		interrupt-controller;
-		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	pmu {
-		compatible = "arm,cortex-a35-pmu";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_PPI 7
-			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-		interrupt-affinity = <&A35_0>, <&A35_1>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
-	};
-
-	frosc: clock-frosc {
-		compatible = "fixed-clock";
-		clock-frequency = <192000000>;
-		clock-output-names = "frosc";
-		#clock-cells = <0>;
-	};
-
-	lposc: clock-lposc {
-		compatible = "fixed-clock";
-		clock-frequency = <1000000>;
-		clock-output-names = "lposc";
-		#clock-cells = <0>;
-	};
-
-	rosc: clock-rosc {
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-		clock-output-names = "rosc";
-		#clock-cells = <0>;
-	};
-
-	sosc: clock-sosc {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "sosc";
-		#clock-cells = <0>;
-	};
-
-	sram@2201f000 {
-		compatible = "mmio-sram";
-		reg = <0x0 0x2201f000 0x0 0x1000>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0 0x0 0x2201f000 0x1000>;
-
-		scmi_buf: scmi-sram-section@0 {
-			compatible = "arm,scmi-shmem";
-			reg = <0x0 0x400>;
-		};
-	};
-
-	firmware {
-		scmi {
-			compatible = "arm,scmi-smc";
-			arm,smc-id = <0xc20000fe>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			shmem = <&scmi_buf>;
-
-			scmi_devpd: protocol@11 {
-				reg = <0x11>;
-				#power-domain-cells = <1>;
-			};
-
-			scmi_sensor: protocol@15 {
-				reg = <0x15>;
-				#thermal-sensor-cells = <1>;
-			};
-		};
-	};
-
-	soc: soc@0 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x0 0x40000000>;
-
-		s4muap: mailbox@27020000 {
-			compatible = "fsl,imx8ulp-mu-s4";
-			reg = <0x27020000 0x10000>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			#mbox-cells = <2>;
-		};
-
-		per_bridge3: bus@29000000 {
-			compatible = "simple-bus";
-			reg = <0x29000000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			mu: mailbox@29220000 {
-				compatible = "fsl,imx8ulp-mu";
-				reg = <0x29220000 0x10000>;
-				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-				#mbox-cells = <2>;
-				status = "disabled";
-			};
-
-			mu3: mailbox@29230000 {
-				compatible = "fsl,imx8ulp-mu";
-				reg = <0x29230000 0x10000>;
-				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
-				#mbox-cells = <2>;
-				status = "disabled";
-			};
-
-			wdog3: watchdog@292a0000 {
-				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
-				reg = <0x292a0000 0x10000>;
-				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
-				timeout-sec = <40>;
-			};
-
-			cgc1: clock-controller@292c0000 {
-				compatible = "fsl,imx8ulp-cgc1";
-				reg = <0x292c0000 0x10000>;
-				#clock-cells = <1>;
-			};
-
-			pcc3: clock-controller@292d0000 {
-				compatible = "fsl,imx8ulp-pcc3";
-				reg = <0x292d0000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-
-			tpm5: tpm@29340000 {
-				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
-				reg = <0x29340000 0x1000>;
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
-					 <&pcc3 IMX8ULP_CLK_TPM5>;
-				clock-names = "ipg", "per";
-				status = "disabled";
-			};
-
-			lpi2c4: i2c@29370000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29370000 0x10000>;
-				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
-					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpi2c5: i2c@29380000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29380000 0x10000>;
-				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
-					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpuart4: serial@29390000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29390000 0x1000>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpuart5: serial@293a0000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x293a0000 0x1000>;
-				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpspi4: spi@293b0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
-				reg = <0x293b0000 0x10000>;
-				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
-					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpspi5: spi@293c0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
-				reg = <0x293c0000 0x10000>;
-				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
-					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-		};
-
-		per_bridge4: bus@29800000 {
-			compatible = "simple-bus";
-			reg = <0x29800000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			pcc4: clock-controller@29800000 {
-				compatible = "fsl,imx8ulp-pcc4";
-				reg = <0x29800000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-
-			lpi2c6: i2c@29840000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29840000 0x10000>;
-				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
-					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpi2c7: i2c@29850000 {
-				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
-				reg = <0x29850000 0x10000>;
-				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
-					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
-				clock-names = "per", "ipg";
-				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
-				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
-				assigned-clock-rates = <48000000>;
-				status = "disabled";
-			};
-
-			lpuart6: serial@29860000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29860000 0x1000>;
-				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			lpuart7: serial@29870000 {
-				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
-				reg = <0x29870000 0x1000>;
-				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
-				clock-names = "ipg";
-				status = "disabled";
-			};
-
-			iomuxc1: pinctrl@298c0000 {
-				compatible = "fsl,imx8ulp-iomuxc1";
-				reg = <0x298c0000 0x10000>;
-			};
-
-			usdhc0: mmc@298d0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298d0000 0x10000>;
-				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC0>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			usdhc1: mmc@298e0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298e0000 0x10000>;
-				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC1>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			usdhc2: mmc@298f0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
-				reg = <0x298f0000 0x10000>;
-				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
-					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
-					 <&pcc4 IMX8ULP_CLK_USDHC2>;
-				clock-names = "ipg", "ahb", "per";
-				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
-				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step = <2>;
-				bus-width = <4>;
-				status = "disabled";
-			};
-
-			fec: ethernet@29950000 {
-				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
-				reg = <0x29950000 0x10000>;
-				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "int0";
-				fsl,num-tx-queues = <1>;
-				fsl,num-rx-queues = <1>;
-				status = "disabled";
-			};
-		};
-
-		gpioe: gpio@2d000080 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
-					 <&pcc4 IMX8ULP_CLK_PCTLE>;
-				clock-names = "gpio", "port";
-				gpio-ranges = <&iomuxc1 0 32 24>;
-		};
-
-		gpiof: gpio@2d010080 {
-				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
-					 <&pcc4 IMX8ULP_CLK_PCTLF>;
-				clock-names = "gpio", "port";
-				gpio-ranges = <&iomuxc1 0 64 32>;
-		};
-
-		per_bridge5: bus@2d800000 {
-			compatible = "simple-bus";
-			reg = <0x2d800000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			cgc2: clock-controller@2da60000 {
-				compatible = "fsl,imx8ulp-cgc2";
-				reg = <0x2da60000 0x10000>;
-				#clock-cells = <1>;
-			};
-
-			pcc5: clock-controller@2da70000 {
-				compatible = "fsl,imx8ulp-pcc5";
-				reg = <0x2da70000 0x10000>;
-				#clock-cells = <1>;
-				#reset-cells = <1>;
-			};
-		};
-
-		gpiod: gpio@2e200080 {
-			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
-			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
-				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
-			clock-names = "gpio", "port";
-			gpio-ranges = <&iomuxc1 0 0 24>;
-		};
-	};
-};
--- a/arch/arm/dts/imx91-11x11-frdm-u-boot.dtsi
+++ b/arch/arm/dts/imx91-11x11-frdm-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx91-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
--- a/arch/arm/dts/imx91-11x11-frdm.dts
+++ b/arch/arm/dts/imx91-11x11-frdm.dts
@@ -0,0 +1,773 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+	compatible = "fsl,imx91-11x11-frdm", "fsl,imx91";
+	model = "NXP i.MX91 11X11 FRDM Board";
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+		rtc0 = &pcf2131;
+	};
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	reg_vref_1v8: regulator-adc-vref {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "vref_1v8";
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		off-on-delay-us = <12000>;
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		pinctrl-names = "default";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VSD_3V3";
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	reg_vdd_12v: regulator-vdd-12v {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "reg_vdd_12v";
+		gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_vexp_3v3: regulator-vexp-3v3 {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VEXP_3V3";
+		vin-supply = <&buck4>;
+		gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_vexp_5v: regulator-vexp-5v {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "VEXP_5V";
+		gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x80000000 0 0x40000000>;
+			reusable;
+			size = <0 0x10000000>;
+			linux,cma-default;
+		};
+	};
+
+	soc@0 {
+		bootph-all;
+		bootph-pre-ram;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&eqos {
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_eqos>;
+	pinctrl-1 = <&pinctrl_eqos_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+			eee-broken-1000t;
+			reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+		};
+	};
+};
+
+&fec {
+	phy-handle = <&ethphy2>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_fec>;
+	pinctrl-1 = <&pinctrl_fec_sleep>;
+	pinctrl-names = "default", "sleep";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy2: ethernet-phy@2 {
+			reg = <2>;
+			eee-broken-1000t;
+			reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+		};
+	};
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pcal6524: gpio@22 {
+		compatible = "nxp,pcal6524";
+		reg = <0x22>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gpio3>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		pinctrl-0 = <&pinctrl_pcal6524>;
+		pinctrl-names = "default";
+	};
+
+	pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&pcal6524>;
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+
+			buck1: BUCK1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2237500>;
+				regulator-min-microvolt = <650000>;
+				regulator-name = "BUCK1";
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2187500>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK2";
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK4";
+			};
+
+			buck5: BUCK5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK5";
+			};
+
+			buck6: BUCK6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3400000>;
+				regulator-min-microvolt = <600000>;
+				regulator-name = "BUCK6";
+			};
+
+			ldo1: LDO1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1600000>;
+				regulator-name = "LDO1";
+			};
+
+			ldo4: LDO4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <800000>;
+				regulator-name = "LDO4";
+			};
+
+			ldo5: LDO5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-name = "LDO5";
+			};
+		};
+	};
+
+	eeprom: at24c256@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+		pagesize = <64>;
+	};
+};
+
+&lpi2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x50>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-parent = <&gpio3>;
+		status = "okay";
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			op-sink-microwatt = <15000000>;
+			power-role = "dual";
+			self-powered;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "sink";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					typec1_dr_sw: endpoint {
+						remote-endpoint = <&usb1_drd_sw>;
+					};
+				};
+			};
+		};
+	};
+
+	pcf2131: rtc@53 {
+		compatible = "nxp,pcf2131";
+		reg = <0x53>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&pcal6524>;
+		status = "okay";
+	};
+};
+
+&lpuart1 {
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart5 {
+	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&usbotg1 {
+	adp-disable;
+	disable-over-current;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	usb-role-switch;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
+&usbotg2 {
+	disable-over-current;
+	dr_mode = "host";
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	status = "okay";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	status = "okay";
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+	no-mmc;
+	no-sdio;
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog3 {
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__ENET1_MDC				0x57e
+			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
+			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
+			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
+			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
+			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
+			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC	0x5fe
+			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
+			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
+			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1			0x57e
+			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
+			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
+			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
+			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
+		>;
+	};
+
+	pinctrl_eqos_sleep: eqossleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__GPIO4_IO0				0x31e
+			MX91_PAD_ENET1_MDIO__GPIO4_IO1				0x31e
+			MX91_PAD_ENET1_RD0__GPIO4_IO10				0x31e
+			MX91_PAD_ENET1_RD1__GPIO4_IO11				0x31e
+			MX91_PAD_ENET1_RD2__GPIO4_IO12				0x31e
+			MX91_PAD_ENET1_RD3__GPIO4_IO13				0x31e
+			MX91_PAD_ENET1_RXC__GPIO4_IO9				0x31e
+			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8			0x31e
+			MX91_PAD_ENET1_TD0__GPIO4_IO5				0x31e
+			MX91_PAD_ENET1_TD1__GPIO4_IO4				0x31e
+			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
+			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
+			MX91_PAD_ENET1_TXC__GPIO4_IO7				0x31e
+			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6			0x31e
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDC__ENET2_MDC			0x57e
+			MX91_PAD_ENET2_MDIO__ENET2_MDIO			0x57e
+			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0		0x57e
+			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1		0x57e
+			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2		0x57e
+			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3		0x57e
+			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC		0x5fe
+			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL	0x57e
+			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0		0x57e
+			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1		0x57e
+			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2		0x57e
+			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3		0x57e
+			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC		0x5fe
+			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL	0x57e
+		>;
+	};
+
+	pinctrl_fec_sleep: fecsleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDC__GPIO4_IO14			0x51e
+			MX91_PAD_ENET2_MDIO__GPIO4_IO15			0x51e
+			MX91_PAD_ENET2_RD0__GPIO4_IO24			0x51e
+			MX91_PAD_ENET2_RD1__GPIO4_IO25			0x51e
+			MX91_PAD_ENET2_RD2__GPIO4_IO26			0x51e
+			MX91_PAD_ENET2_RD3__GPIO4_IO27			0x51e
+			MX91_PAD_ENET2_RXC__GPIO4_IO23			0x51e
+			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22		0x51e
+			MX91_PAD_ENET2_TD0__GPIO4_IO19			0x51e
+			MX91_PAD_ENET2_TD1__GPIO4_IO18			0x51e
+			MX91_PAD_ENET2_TD2__GPIO4_IO17			0x51e
+			MX91_PAD_ENET2_TD3__GPIO4_IO16			0x51e
+			MX91_PAD_ENET2_TXC__GPIO4_IO21			0x51e
+			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20		0x51e
+		>;
+	};
+
+	pinctrl_lcdif_gpio: lcdifgpiogrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO00__GPIO2_IO0			0x51e
+			MX91_PAD_GPIO_IO01__GPIO2_IO1			0x51e
+			MX91_PAD_GPIO_IO02__GPIO2_IO2			0x51e
+			MX91_PAD_GPIO_IO03__GPIO2_IO3			0x51e
+		>;
+	};
+
+	pinctrl_lcdif: lcdifgrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK		0x31e
+			MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE		0x31e
+			MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC		0x31e
+			MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC		0x31e
+			MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0		0x31e
+			MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1		0x31e
+			MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2		0x31e
+			MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3		0x31e
+			MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4		0x31e
+			MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5		0x31e
+			MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6		0x31e
+			MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7		0x31e
+			MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8		0x31e
+			MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9		0x31e
+			MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10	0x31e
+			MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11	0x31e
+			MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12	0x31e
+			MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13	0x31e
+			MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14	0x31e
+			MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15	0x31e
+			MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16	0x31e
+			MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17	0x31e
+			MX91_PAD_GPIO_IO27__GPIO2_IO27			0x31e
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			MX91_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
+			MX91_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <
+			MX91_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
+			MX91_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
+			MX91_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_pcal6524: pcal6524grp {
+		fsl,pins = <
+			MX91_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_RESET_B__GPIO3_IO7	0x31e
+		>;
+		bootph-pre-ram;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX91_PAD_UART1_RXD__LPUART1_RX			0x31e
+			MX91_PAD_UART1_TXD__LPUART1_TX			0x31e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX	0x31e
+			MX91_PAD_DAP_TDI__LPUART5_RX		0x31e
+			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B	0x31e
+			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B	0x31e
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x158e
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x138e
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x138e
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x138e
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x138e
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x138e
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x138e
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x138e
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x158e
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x15fe
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x13fe
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK		0x1582
+			MX91_PAD_SD1_CMD__USDHC1_CMD		0x1382
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x1382
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x1382
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x1382
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x1382
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x1382
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x1382
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x1382
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x1382
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x1582
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x158e
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x138e
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x138e
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x138e
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x15fe
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x13fe
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0		0x31e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK		0x1582
+			MX91_PAD_SD2_CMD__USDHC2_CMD		0x1382
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0	0x1382
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1	0x1382
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2	0x1382
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3	0x1382
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__GPIO3_IO1		0x51e
+			MX91_PAD_SD2_CMD__GPIO3_IO2		0x51e
+			MX91_PAD_SD2_DATA0__GPIO3_IO3		0x51e
+			MX91_PAD_SD2_DATA1__GPIO3_IO4		0x51e
+			MX91_PAD_SD2_DATA2__GPIO3_IO5		0x51e
+			MX91_PAD_SD2_DATA3__GPIO3_IO6		0x51e
+			MX91_PAD_SD2_VSELECT__GPIO3_IO19	0x51e
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x158e
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x138e
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x138e
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x138e
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x138e
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x138e
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x15fe
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x13fe
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x13fe
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x13fe
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x13fe
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK		0x1582
+			MX91_PAD_SD3_CMD__USDHC3_CMD		0x1382
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0	0x1382
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1	0x1382
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2	0x1382
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3	0x1382
+		>;
+	};
+
+	pinctrl_usdhc3_sleep: usdhc3sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__GPIO3_IO20		0x31e
+			MX91_PAD_SD3_CMD__GPIO3_IO21		0x31e
+			MX91_PAD_SD3_DATA0__GPIO3_IO22		0x31e
+			MX91_PAD_SD3_DATA1__GPIO3_IO23		0x31e
+			MX91_PAD_SD3_DATA2__GPIO3_IO24		0x31e
+			MX91_PAD_SD3_DATA3__GPIO3_IO25		0x31e
+		>;
+	};
+};
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -226,6 +226,9 @@ ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y)
 ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),)
 SPL: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
+
+flash.bin: spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
 else
 quiet_cmd_cpp_cfg_imx9_check = CHECK    $@
 cmd_cpp_cfg_imx9_check = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -x c -o $@ $< && $(srctree)/tools/imx9_image.sh $@
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -285,10 +285,10 @@ u32 get_ahb_clk(void)

 void arch_preboot_os(void)
 {
-#if defined(CONFIG_IMX_AHCI)
 	struct udevice *dev;
 	int rc;

+#if defined(CONFIG_IMX_AHCI)
 	rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
 	if (!rc && dev) {
 		rc = device_remove(dev, DM_REMOVE_NORMAL);
@@ -308,11 +308,17 @@ void arch_preboot_os(void)
 #endif
 #if defined(CONFIG_VIDEO_IPUV3)
 	/* disable video before launching O/S */
-	ipuv3_fb_shutdown();
+	rc = uclass_find_first_device(UCLASS_VIDEO, &dev);
+	while (!rc && dev) {
+		ipuv3_fb_shutdown(dev);
+		uclass_find_next_device(&dev);
+	}
 #endif
 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
 	lcdif_power_down();
 #endif
+    (void)dev;
+    (void)rc;
 }

 #ifndef CONFIG_IMX8M
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -27,6 +27,7 @@ config TARGET_IMX8ULP_EVK
 	select IMX8ULP
 	select SUPPORT_SPL
 	select IMX8ULP_DRAM
+	imply OF_UPSTREAM

 endchoice

--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -61,6 +61,14 @@ config TARGET_IMX91_11X11_EVK
 	imply BOOTSTD_FULL
 	imply BOOTSTD_BOOTCOMMAND

+config TARGET_IMX91_11X11_FRDM
+	bool "imx91_11x11_frdm"
+	select OF_BOARD_FIXUP
+	select IMX91
+	select IMX9_LPDDR4X
+	imply BOOTSTD_FULL
+	imply BOOTSTD_BOOTCOMMAND
+
 config TARGET_IMX93_9X9_QSB
 	bool "imx93_qsb"
 	select OF_BOARD_FIXUP
@@ -148,6 +156,7 @@ config TARGET_TORADEX_SMARC_IMX95
 endchoice

 source "board/freescale/imx91_evk/Kconfig"
+source "board/freescale/imx91_frdm/Kconfig"
 source "board/freescale/imx93_evk/Kconfig"
 source "board/freescale/imx93_frdm/Kconfig"
 source "board/freescale/imx93_qsb/Kconfig"
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.env
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.env
@@ -0,0 +1,97 @@
+#ifdef CONFIG_AHAB_BOOT
+sec_boot=yes
+#else
+sec_boot=no
+#endif
+
+jh_clk=
+jh_mmcboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run loadimage; \
+	   run mmcboot
+jh_netboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run netboot
+
+initrd_addr=0x83800000
+scriptaddr=0x83500000
+splashimage=0x90000000
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+fdtoverlay_addr_r=0x83040000
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+cntr_addr=0x98000000
+emmc_dev=0
+sd_dev=2
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+image=Image
+cntr_file=os_cntr_signed.bin
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+console=ttyLP1,115200 earlycon
+bootm_size=0x10000000
+boot_fit=no
+mmcroot=/dev/mmcblk0p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}
+netargs=setenv bootargs ${jh_clk} console=${console}
+        root=/dev/nfs
+        ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+bootscript=echo Running bootscript from mmc ...; source
+auth_os=booti ${cntr_addr}
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+mmcboot=echo Booting from mmc ...;
+        run mmcargs;
+        if test ${sec_boot} = yes; then
+                run auth_os;
+        else
+            if test ${boot_fit} = yes || test ${boot_fit} = try; then
+                bootm ${loadaddr};
+            else
+                if run loadfdt loadimage; then
+                    run boot_os;
+                else
+                    echo WARN: Cannot load the fdt and image;
+                fi;
+            fi;
+        fi;
+netboot=echo Booting from net ...;
+        run netargs;
+        if test ${ip_dyn} = yes; then
+            setenv get_cmd dhcp;
+        else
+            setenv get_cmd tftp;
+        fi;
+        if test ${sec_boot} = yes; then
+            ${get_cmd} ${cntr_addr} ${cntr_file};
+            run auth_os;
+        else
+            ${get_cmd} ${loadaddr} ${image};
+            if test ${boot_fit} = yes || test ${boot_fit} = try; then
+                bootm ${loadaddr};
+            else
+                if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+                    run boot_os;
+                else
+                    echo WARN: Cannot load the DT;
+                fi;
+            fi;
+        fi;
+bsp_bootcmd=echo Running BSP bootcmd ...;
+            mmc dev ${mmcdev}; if mmc rescan; then
+            if run loadbootscript; then
+                run bootscript;
+            else
+                if test ${sec_boot} = yes; then
+                    if run loadcntr; then
+                        run mmcboot;
+                    else run netboot;
+                    fi;
+                else
+                    if run loadimage; then
+                        run mmcboot;
+                    else run netboot;
+                    fi;
+                fi;
+            fi;
+        fi;
--- a/board/freescale/imx91_frdm/Kconfig
+++ b/board/freescale/imx91_frdm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX91_11X11_FRDM
+
+config SYS_BOARD
+	default "imx91_frdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx91_frdm"
+
+endif
--- a/board/freescale/imx91_frdm/MAINTAINERS
+++ b/board/freescale/imx91_frdm/MAINTAINERS
@@ -0,0 +1,7 @@
+FRDM-IMX91 BOARD
+M:	Joseph Guo <qijian.guo@nxp.com>
+S:	Maintained
+F:	board/freescale/imx91_frdm/
+F:	include/configs/imx91_frdm.h
+F:	configs/imx91_11x11_frdm_defconfig
+F:	configs/imx91_11x11_frdm_inline_ecc_defconfig
--- a/board/freescale/imx91_frdm/Makefile
+++ b/board/freescale/imx91_frdm/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx91_frdm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_IMX9_DRAM_INLINE_ECC
+obj-y += lpddr4_2400mts_ecc_1gb_timing.o lpddr4_2400mts_ecc_2gb_timing.o
+else
+obj-y += lpddr4_2400mts_1gb_timing.o lpddr4_2400mts_2gb_timing.o
+endif
+endif
--- a/board/freescale/imx91_frdm/imx91_frdm.c
+++ b/board/freescale/imx91_frdm/imx91_frdm.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <env.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <dm.h>
+
+#define TCPC_ALERT 0x10
+#define TCPC_ALERT_MASK 0x12
+#define TCPC_FAULT_STATUS_MASK 0x15
+#define USB_I2C_BUS 2
+#define USB_I2C_ADDR 0x50
+
+/*
+ * Since tcpc driver is not upstream. PTN5110 interrupt will cause
+ * kernel panic because nobody cares the interrupt. So add workaround here.
+ * Clear PTN5110 USB Power Delivery controller alert status by
+ * masking interrupts and clearing pending alerts via I2C communication.
+ * This is typically called during board initialization to ensure the USB PD
+ * controller starts in a clean state without any stale alert conditions.
+ */
+static int clear_pd_alert(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	u8 buffer_0[2] = {0, 0};
+	u8 buffer_1[2] = {0xff, 0xff};
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, USB_I2C_BUS, &bus);
+	if (ret) {
+		printf("Failed to get I2C bus %d\n", USB_I2C_BUS);
+		return ret;
+	}
+
+	ret = dm_i2c_probe(bus, USB_I2C_ADDR, 0, &i2c_dev);
+	if (ret) {
+		printf("Can't find USB PD device at 0x%02x\n", USB_I2C_ADDR);
+		return ret;
+	}
+
+	/* Mask all alert status*/
+	ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2);
+	if (ret) {
+		printf("%s dm_i2c_write failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2);
+	if (ret) {
+		printf("%s dm_i2c_write failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2);
+	if (ret) {
+		printf("%s dm_i2c_write failed: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+		board_late_mmc_env_init();
+
+	env_set("sec_boot", "no");
+
+	if (IS_ENABLED(CONFIG_AHAB_BOOT))
+		env_set("sec_boot", "yes");
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+		env_set("board_name", "11X11_FRDM");
+		env_set("board_rev", "iMX91");
+	}
+
+	clear_pd_alert();
+	return 0;
+}
--- a/board/freescale/imx91_frdm/imx91_frdm.env
+++ b/board/freescale/imx91_frdm/imx91_frdm.env
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+boot_targets=mmc0 mmc1
+boot_fit=no
+bootm_size=0x10000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP0,115200 earlycon
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
+mmcpart=1
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
+auth_os=auth_cntr ${cntr_addr}
+sec_boot=no
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+mmcboot=
+	echo Booting from mmc ...;
+	run mmcargs;
+	if test ${sec_boot} = yes; then
+		if run true; then
+			run boot_os;
+		else
+			echo ERR: failed to authenticate;
+		fi;
+	else
+		if run loadfdt; then
+			run boot_os;
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	fi;
+netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
+	ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+	echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	if test ${sec_boot} = yes; then
+		${get_cmd} ${cntr_addr} ${cntr_file};
+		if true; then
+			run boot_os;
+		else
+			echo ERR: failed to authenticate;
+		fi;
+	else
+		${get_cmd} ${loadaddr} ${image};
+		if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
+			run boot_os;
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	fi;
+bsp_bootcmd=
+	echo Running BSP bootcmd ...;
+	mmc dev ${mmcdev};
+	if mmc rescan; then
+		if run loadbootscript; then
+			run bootscript;
+		else
+			if test ${sec_boot} = yes; then
+				if run loadcntr; then
+					run mmcboot;
+				else
+					run netboot;
+				fi;
+			else
+				if run loadimage; then
+					run mmcboot;
+				else
+					run netboot;
+				fi;
+			fi;
+		fi;
+	fi;
+scriptaddr=0x83500000
--- a/board/freescale/imx91_frdm/lpddr4_2400mts_1gb_timing.c
+++ b/board/freescale/imx91_frdm/lpddr4_2400mts_1gb_timing.c
--- a/board/freescale/imx91_frdm/lpddr4_2400mts_2gb_timing.c
+++ b/board/freescale/imx91_frdm/lpddr4_2400mts_2gb_timing.c
--- a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c
+++ b/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c
--- a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c
+++ b/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c
--- a/board/freescale/imx91_frdm/lpddr4_timing.h
+++ b/board/freescale/imx91_frdm/lpddr4_timing.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1GB;
+extern struct dram_timing_info dram_timing_2GB;
+
+#endif /* __LPDDR4_TIMING_H__ */
--- a/board/freescale/imx91_frdm/spl.c
+++ b/board/freescale/imx91_frdm/spl.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "lpddr4_timing.h"
+
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/trdc.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <linux/delay.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SRC_DDRC_SW_CTRL		(0x44461020)
+#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL	(0x44461424)
+
+static struct _drams {
+	u8 mr8;
+	struct dram_timing_info *pdram_timing;
+	char *name;
+} frdm_drams[2] = {
+	{0x10, &dram_timing_1GB, "1GB DRAM" },
+	{0x18, &dram_timing_2GB, "2GB DRAM" },
+};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+	int ret;
+
+	ret = ele_start_rng();
+	if (ret)
+		printf("Fail to start RNG: %d\n", ret);
+
+	puts("Normal Boot\n");
+}
+
+void spl_dram_init(void)
+{
+	int i;
+	int ret;
+
+	for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) {
+		struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing;
+
+		printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+		ret = ddr_init(ptiming);
+		if (ret == 0) {
+			if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) {
+				printf("found DRAM %s matched\n", frdm_drams[i].name);
+				break;
+			}
+
+			/* Power down and Power up DDR Mixer */
+
+			/* Clear PwrOkIn via DDRMIX register */
+			setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+			/* Power off the DDRMIX */
+			setbits_32(SRC_DDRC_SW_CTRL, BIT(31));
+
+			udelay(50);
+
+			/* Power up the DDRMIX */
+			clrbits_32(SRC_DDRC_SW_CTRL, BIT(31));
+			setbits_32(SRC_DDRC_SW_CTRL, BIT(0));
+			udelay(10);
+			clrbits_32(SRC_DDRC_SW_CTRL, BIT(0));
+			udelay(10);
+		}
+	}
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int val = 0, buck_val;
+
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("ERROR: Get PMIC PCA9451A failed!\n");
+		return ret;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/* enable DVS control through PMIC_STBY_REQ */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+	if (ret < 0)
+		return ret;
+
+	val = ret;
+
+	if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+		buck_val = 0x0c; /* 0.8V for Low drive mode */
+		printf("PMIC: Low Drive Voltage Mode\n");
+	} else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+		buck_val = 0x10; /* 0.85V for Nominal drive mode */
+		printf("PMIC: Nominal Voltage Mode\n");
+	} else {
+		buck_val = 0x14; /* 0.9V for Over drive mode */
+		printf("PMIC: Over Drive Voltage Mode\n");
+	}
+
+	if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+	} else {
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+	}
+
+	/* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
+
+	/* set standby voltage to 0.65V */
+	if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+	else
+		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+	/* I2C_LT_EN*/
+	pmic_reg_write(dev, 0xa, 0x3);
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	timer_init();
+
+	arch_cpu_init();
+
+	spl_early_init();
+
+	preloader_console_init();
+
+	ret = imx9_probe_mu();
+	if (ret) {
+		printf("Fail to init ELE API\n");
+	} else {
+		debug("SOC: 0x%x\n", gd->arch.soc_rev);
+		debug("LC: 0x%x\n", gd->arch.lifecycle);
+	}
+
+	clock_init_late();
+
+	power_init_board();
+
+	if (!is_voltage_mode(VOLT_LOW_DRIVE))
+		set_arm_clk(get_cpu_speed_grade_hz());
+
+	/* Init power of mix */
+	soc_power_init();
+
+	/* Setup TRDC for DDR access */
+	trdc_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg"
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8ulp-evk"
 CONFIG_TARGET_IMX8ULP_EVK=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_SERIAL=y
@@ -26,10 +26,10 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
 CONFIG_REMAKE_ELF=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
 CONFIG_BOOTDELAY=0
-CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
+CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2068
 CONFIG_BOARD_EARLY_INIT_F=y
--- a/configs/imx91_11x11_frdm_defconfig
+++ b/configs/imx91_11x11_frdm_defconfig
@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx91-11x11-frdm"
+CONFIG_TARGET_IMX91_11X11_FRDM=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x204E0000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_TEXT_BASE=0x204A0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20498000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_CMD_DEKBLOB=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx91-11x11-frdm.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+# CONFIG_BOARD_INIT is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_MMC_DEVICE_INDEX=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_ADC_IMX93=y
+CONFIG_CLK_IMX93=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_ADP5585_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHY_ANEG_TIMEOUT=20000
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_SHA384=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
--- a/configs/imx91_11x11_frdm_inline_ecc_defconfig
+++ b/configs/imx91_11x11_frdm_inline_ecc_defconfig
@@ -0,0 +1,3 @@
+#include <configs/imx91_11x11_frdm_defconfig>
+
+CONFIG_IMX9_DRAM_INLINE_ECC=y
--- a/doc/board/nxp/imx91_11x11_frdm.rst
+++ b/doc/board/nxp/imx91_11x11_frdm.rst
@@ -0,0 +1,100 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx91_frdm
+=======================
+
+U-Boot for the NXP i.MX91 11x11 FRDM Board
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot from the SD card
+- Boot using USB serial download (uuu)
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.10
+
+.. code-block:: bash
+
+   $ unset LDFLAGS
+   $ make PLAT=imx91 bl31
+   $ cp build/imx91/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+   $ chmod +x firmware-imx-8.21.bin
+   $ ./firmware-imx-8.21.bin
+   $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+   $ wget  https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
+   $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
+   $ ./firmware-ele-imx-1.3.0-17945fc.bin
+   $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+   $ export CROSS_COMPILE=aarch64-poky-linux-
+   $ make imx91_11x11_frdm_defconfig or imx91_11x11_frdm_inline_ecc_defconfig
+   $ make
+
+- Inline ECC is to enable DDR ECC feature with imx91_11x11_frdm_inline_ecc_defconfig
+  Enable ECC will reduce DDR size by 1/8. For 1GB DRAM, available size will be 896MB.
+
+Burn the flash.bin to MicroSD card offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1k seek=32; sync
+
+Boot from the SD card
+---------------------
+
+- Configure SW1 boot switches to SD boot mode:
+  0011 SW1[3:0] - ("USDHC2 4-bit SD3.0" Boot Mode)
+- Insert the SD card in the SD slot (P13) of the board.
+- Connect a USB Type-C cable into the P16 Debug USB Port and connect
+  using a terminal emulator at 115200 bps, 8n1. The console will show up
+  at /dev/ttyACM0.
+- Power on the board by connecting a USB Type-C cable into the P1
+  Power USB Port.
+
+Boot using USB serial download (uuu)
+------------------------------------
+
+- Configure SW1 boot switches to serial download boot mode:
+  0001 SW1[3:0] - ("Serial downloader (USB)" Boot Mode)
+- Plug USB Type-C cable into the P2 device port.
+- Connect a USB Type-C cable into the P16 Debug USB Port and connect
+  using a terminal emulator at 115200 bps, 8n1. The console will show up
+  at /dev/ttyACM0.
+- Power on the board by connecting a USB Type-C cable into the P1
+  Power USB Port.
+- Use NXP Universal Update Utility `NXP Universal Update Utility`_ to boot or
+  flash the device. E.g. following command can be used to flash an image onto
+  the eMMC storage:
+
+.. code-block:: bash
+
+   $ uuu -V -b emmc_all <image file>
+
+.. _`NXP Universal Update Utility`: https://github.com/nxp-imx/mfgtools
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -13,6 +13,7 @@ NXP Semiconductors
   imx8qxp_mek
   imx8ulp_evk
   imx91_11x11_evk
+   imx91_11x11_frdm
   imx93_9x9_qsb
   imx93_11x11_evk
   imx93_frdm
--- a/drivers/video/imx/ipu.h
+++ b/drivers/video/imx/ipu.h
@@ -1,5 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
+ * Code fixes:
+ *
+ * (C) Copyright 2025
+ * Brian Ruley, GE HealthCare, brian.ruley@gehealthcare.com
+ *
 * Porting to u-boot:
 *
 * (C) Copyright 2010
@@ -13,15 +18,20 @@
 #ifndef __ASM_ARCH_IPU_H__
 #define __ASM_ARCH_IPU_H__

-#include <linux/types.h>
 #include <ipu_pixfmt.h>
+#include <linux/types.h>

-#define IDMA_CHAN_INVALID	0xFF
-#define HIGH_RESOLUTION_WIDTH	1024
+#define IDMA_CHAN_INVALID 0xFF
+#define HIGH_RESOLUTION_WIDTH 1024
+
+struct ipu_ctx;
+struct ipu_di_config;

 struct clk {
 	const char *name;
 	int id;
+	/* The IPU context of this clock */
+	struct ipu_ctx *ctx;
 	/* Source clock this clk depends on */
 	struct clk *parent;
 	/* Secondary clock to enable/disable with this clock */
@@ -39,30 +49,93 @@ struct clk {
 	 * Function ptr to recalculate the clock's rate based on parent
 	 * clock's rate
 	 */
-	void (*recalc) (struct clk *);
+	void (*recalc)(struct clk *clk);
 	/*
 	 * Function ptr to set the clock to a new rate. The rate must match a
 	 * supported rate returned from round_rate. Leave blank if clock is not
 	* programmable
 	 */
-	int (*set_rate) (struct clk *, unsigned long);
+	int (*set_rate)(struct clk *clk, unsigned long rate);
 	/*
 	 * Function ptr to round the requested clock rate to the nearest
 	 * supported rate that is less than or equal to the requested rate.
 	 */
-	unsigned long (*round_rate) (struct clk *, unsigned long);
+	unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
 	/*
 	 * Function ptr to enable the clock. Leave blank if clock can not
 	 * be gated.
 	 */
-	int (*enable) (struct clk *);
+	int (*enable)(struct clk *clk);
 	/*
 	 * Function ptr to disable the clock. Leave blank if clock can not
 	 * be gated.
 	 */
-	void (*disable) (struct clk *);
+	void (*disable)(struct clk *clk);
 	/* Function ptr to set the parent clock of the clock. */
-	int (*set_parent) (struct clk *, struct clk *);
+	int (*set_parent)(struct clk *clk, struct clk *parent);
+};
+
+struct udevice;
+
+/*
+ * Per-IPU context used by ipu_common to manage clocks and channel state.
+ * Lifetime is owned by the IPU DM driver
+ */
+struct ipu_ctx {
+	struct udevice *dev;
+	int dev_id;
+
+	struct clk *ipu_clk;
+	struct clk *ldb_clk;
+	unsigned char ipu_clk_enabled;
+	struct clk *di_clk[2];
+	struct clk *pixel_clk[2];
+
+	u8 dc_di_assignment[10];
+	u32 channel_init_mask;
+	u32 channel_enable_mask;
+
+	int ipu_dc_use_count;
+	int ipu_dp_use_count;
+	int ipu_dmfc_use_count;
+	int ipu_di_use_count[2];
+};
+
+/**
+ * @disp:	    The DI the panel is attached to.
+ * @pixel_clk_rate: Desired pixel clock frequency in Hz.
+ * @pixel_fmt:	    Input parameter for pixel format of buffer.
+ *		    Pixel format is a FOURCC ASCII code.
+ * @width:	    The width of panel in pixels.
+ * @height:	    The height of panel in pixels.
+ * @h_start_width:  The number of pixel clocks between the HSYNC
+ *		    signal pulse and the start of valid data.
+ * @h_sync_width:   The width of the HSYNC signal in units of pixel
+ *		    clocks.
+ * @h_end_width:    The number of pixel clocks between the end of
+ *		    valid data and the HSYNC signal for next line.
+ * @v_start_width:  The number of lines between the VSYNC
+ *		    signal pulse and the start of valid data.
+ * @v_sync_width:   The width of the VSYNC signal in units of lines
+ * @v_end_width:    The number of lines between the end of valid
+ *		    data and the VSYNC signal for next frame.
+ * @ctx:	    The IPU context of the display.
+ */
+struct ipu_di_config {
+	int disp;
+	u32 pixel_clk_rate;
+	u32 pixel_fmt;
+	u16 width;
+	u16 height;
+	u16 h_start_width;
+	u16 h_sync_width;
+	u16 h_end_width;
+	u16 v_start_width;
+	u16 v_sync_width;
+	u16 v_end_width;
+	u32 v_to_h_sync;
+
+	struct ipu_ctx *ctx;
 };

 /*
@@ -77,18 +150,18 @@ typedef enum {
 * IPU Driver channels definitions.
 * Note these are different from IDMA channels
 */
-#define IPU_MAX_CH	32
+#define IPU_MAX_CH 32
 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
 	((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
-#define _MAKE_ALT_CHAN(ch)		(ch | (IPU_MAX_CH << 24))
-#define IPU_CHAN_ID(ch)			(ch >> 24)
-#define IPU_CHAN_ALT(ch)		(ch & 0x02000000)
-#define IPU_CHAN_ALPHA_IN_DMA(ch)	((uint32_t) (ch >> 6) & 0x3F)
-#define IPU_CHAN_GRAPH_IN_DMA(ch)	((uint32_t) (ch >> 12) & 0x3F)
-#define IPU_CHAN_VIDEO_IN_DMA(ch)	((uint32_t) (ch >> 18) & 0x3F)
-#define IPU_CHAN_OUT_DMA(ch)		((uint32_t) (ch & 0x3F))
+#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
+#define IPU_CHAN_ID(ch) (ch >> 24)
+#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((u32)(ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((u32)(ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((u32)(ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch) ((u32)(ch & 0x3F))
 #define NO_DMA 0x3F
-#define ALT	1
+#define ALT 1

 /*
 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
@@ -118,16 +191,16 @@ typedef enum {
 * Enumeration of types of buffers for a logical channel.
 */
 typedef enum {
-	IPU_OUTPUT_BUFFER = 0,	/*< Buffer for output from IPU */
-	IPU_ALPHA_IN_BUFFER = 1,	/*< Buffer for input to IPU */
-	IPU_GRAPH_IN_BUFFER = 2,	/*< Buffer for input to IPU */
-	IPU_VIDEO_IN_BUFFER = 3,	/*< Buffer for input to IPU */
+	IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
+	IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
+	IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
+	IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
 	IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
 	IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
 } ipu_buffer_t;

-#define IPU_PANEL_SERIAL		1
-#define IPU_PANEL_PARALLEL		2
+#define IPU_PANEL_SERIAL 1
+#define IPU_PANEL_PARALLEL 2

 struct ipu_channel {
 	u8 video_in_dma;
@@ -148,27 +221,27 @@ enum ipu_dmfc_type {
 */
 typedef union {
 	struct {
-		uint32_t di;
+		u32 di;
 		unsigned char interlaced;
 	} mem_dc_sync;
 	struct {
-		uint32_t temp;
+		u32 temp;
 	} mem_sdc_fg;
 	struct {
-		uint32_t di;
+		u32 di;
 		unsigned char interlaced;
-		uint32_t in_pixel_fmt;
-		uint32_t out_pixel_fmt;
+		u32 in_pixel_fmt;
+		u32 out_pixel_fmt;
 		unsigned char alpha_chan_en;
 	} mem_dp_bg_sync;
 	struct {
-		uint32_t temp;
+		u32 temp;
 	} mem_sdc_bg;
 	struct {
-		uint32_t di;
+		u32 di;
 		unsigned char interlaced;
-		uint32_t in_pixel_fmt;
-		uint32_t out_pixel_fmt;
+		u32 in_pixel_fmt;
+		u32 out_pixel_fmt;
 		unsigned char alpha_chan_en;
 	} mem_dp_fg_sync;
 } ipu_channel_params_t;
@@ -185,60 +258,45 @@ enum ipu_irq_line {
 * Bitfield of Display Interface signal polarities.
 */
 typedef struct {
-	unsigned datamask_en:1;
-	unsigned ext_clk:1;
-	unsigned interlaced:1;
-	unsigned odd_field_first:1;
-	unsigned clksel_en:1;
-	unsigned clkidle_en:1;
-	unsigned data_pol:1;	/* true = inverted */
-	unsigned clk_pol:1;	/* true = rising edge */
-	unsigned enable_pol:1;
-	unsigned Hsync_pol:1;	/* true = active high */
-	unsigned Vsync_pol:1;
+	unsigned datamask_en : 1;
+	unsigned ext_clk : 1;
+	unsigned interlaced : 1;
+	unsigned odd_field_first : 1;
+	unsigned clksel_en : 1;
+	unsigned clkidle_en : 1;
+	unsigned data_pol : 1; /* true = inverted */
+	unsigned clk_pol : 1; /* true = rising edge */
+	unsigned enable_pol : 1;
+	unsigned hsync_pol : 1; /* true = active high */
+	unsigned vsync_pol : 1;
 } ipu_di_signal_cfg_t;

-typedef enum {
-	RGB,
-	YCbCr,
-	YUV
-} ipu_color_space_t;
+typedef enum { RGB, YCBCR, YUV } ipu_color_space_t;

 /* Common IPU API */
-int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
-void ipu_uninit_channel(ipu_channel_t channel);
+int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel,
+			 ipu_channel_params_t *params);
+void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel);

 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
-				uint32_t pixel_fmt,
-				uint16_t width, uint16_t height,
-				uint32_t stride,
-				dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
-				uint32_t u_offset, uint32_t v_offset);
+				u32 pixel_fmt, u16 width, u16 height,
+				u32 stride, dma_addr_t phyaddr_0,
+				dma_addr_t phyaddr_1, u32 u_offset,
+				u32 v_offset);

-int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
-				  uint32_t bufNum, dma_addr_t phyaddr);
-
-int32_t ipu_is_channel_busy(ipu_channel_t channel);
 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
-		uint32_t bufNum);
-int32_t ipu_enable_channel(ipu_channel_t channel);
-int32_t ipu_disable_channel(ipu_channel_t channel);
+			    u32 buf_num);
+int32_t ipu_enable_channel(struct ipu_ctx *ctx, ipu_channel_t channel);
+int32_t ipu_disable_channel(struct ipu_ctx *ctx, ipu_channel_t channel);

-int32_t ipu_init_sync_panel(int disp,
-			    uint32_t pixel_clk,
-			    uint16_t width, uint16_t height,
-			    uint32_t pixel_fmt,
-			    uint16_t h_start_width, uint16_t h_sync_width,
-			    uint16_t h_end_width, uint16_t v_start_width,
-			    uint16_t v_sync_width, uint16_t v_end_width,
-			    uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+int32_t ipu_init_sync_panel(struct ipu_di_config *di, ipu_di_signal_cfg_t sig);

 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
-				  uint8_t alpha);
+				  u8 alpha);
 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
-			       uint32_t colorKey);
+			       u32 color_key);

-uint32_t bytes_per_pixel(uint32_t fmt);
+u32 bytes_per_pixel(u32 fmt);

 void clk_enable(struct clk *clk);
 void clk_disable(struct clk *clk);
@@ -250,18 +308,18 @@ int clk_get_usecount(struct clk *clk);
 struct clk *clk_get_parent(struct clk *clk);

 void ipu_dump_registers(void);
-int ipu_probe(void);
-bool ipu_clk_enabled(void);
+struct ipu_ctx *ipu_probe(struct udevice *dev);
+bool ipu_clk_enabled(struct ipu_ctx *ctx);

 void ipu_dmfc_init(int dmfc_type, int first);
 void ipu_init_dc_mappings(void);
 void ipu_dmfc_set_wait4eot(int dma_chan, int width);
 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
 void ipu_dc_uninit(int dc_chan);
-void ipu_dp_dc_enable(ipu_channel_t channel);
-int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
-		 uint32_t out_pixel_fmt);
+void ipu_dp_dc_enable(struct ipu_ctx *ctx, ipu_channel_t channel);
+int ipu_dp_init(ipu_channel_t channel, u32 in_pixel_fmt, u32 out_pixel_fmt);
 void ipu_dp_uninit(ipu_channel_t channel);
-void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
-ipu_color_space_t format_to_colorspace(uint32_t fmt);
+void ipu_dp_dc_disable(struct ipu_ctx *ctx, ipu_channel_t channel,
+		       unsigned char swap);
+ipu_color_space_t format_to_colorspace(u32 fmt);
 #endif
--- a/drivers/video/imx/ipu_common.c
+++ b/drivers/video/imx/ipu_common.c
--- a/drivers/video/imx/ipu_disp.c
+++ b/drivers/video/imx/ipu_disp.c
--- a/drivers/video/imx/ipu_regs.h
+++ b/drivers/video/imx/ipu_regs.h
@@ -13,69 +13,71 @@
 #ifndef __IPU_REGS_INCLUDED__
 #define __IPU_REGS_INCLUDED__

-#define IPU_DISP0_BASE		0x00000000
-#define IPU_MCU_T_DEFAULT	8
-#define IPU_DISP1_BASE		(IPU_MCU_T_DEFAULT << 25)
-#define IPU_CM_REG_BASE		0x00000000
-#define IPU_STAT_REG_BASE	0x00000200
-#define IPU_IDMAC_REG_BASE	0x00008000
-#define IPU_ISP_REG_BASE	0x00010000
-#define IPU_DP_REG_BASE		0x00018000
-#define IPU_IC_REG_BASE		0x00020000
-#define IPU_IRT_REG_BASE	0x00028000
-#define IPU_CSI0_REG_BASE	0x00030000
-#define IPU_CSI1_REG_BASE	0x00038000
-#define IPU_DI0_REG_BASE	0x00040000
-#define IPU_DI1_REG_BASE	0x00048000
-#define IPU_SMFC_REG_BASE	0x00050000
-#define IPU_DC_REG_BASE		0x00058000
-#define IPU_DMFC_REG_BASE	0x00060000
-#define IPU_VDI_REG_BASE	0x00680000
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
-#define IPU_CPMEM_REG_BASE	0x01000000
-#define IPU_LUT_REG_BASE	0x01020000
-#define IPU_SRM_REG_BASE	0x01040000
-#define IPU_TPM_REG_BASE	0x01060000
-#define IPU_DC_TMPL_REG_BASE	0x01080000
-#define IPU_ISP_TBPR_REG_BASE	0x010C0000
-#elif defined(CONFIG_MX6)
-#define IPU_CPMEM_REG_BASE	0x00100000
-#define IPU_LUT_REG_BASE	0x00120000
-#define IPU_SRM_REG_BASE	0x00140000
-#define IPU_TPM_REG_BASE	0x00160000
-#define IPU_DC_TMPL_REG_BASE	0x00180000
-#define IPU_ISP_TBPR_REG_BASE	0x001C0000
+#include <asm/arch/imx-regs.h>
+
+#define IPU_DISP0_BASE 0x00000000
+#define IPU_MCU_T_DEFAULT 8
+#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
+#define IPU_CM_REG_BASE 0x00000000
+#define IPU_STAT_REG_BASE 0x00000200
+#define IPU_IDMAC_REG_BASE 0x00008000
+#define IPU_ISP_REG_BASE 0x00010000
+#define IPU_DP_REG_BASE 0x00018000
+#define IPU_IC_REG_BASE 0x00020000
+#define IPU_IRT_REG_BASE 0x00028000
+#define IPU_CSI0_REG_BASE 0x00030000
+#define IPU_CSI1_REG_BASE 0x00038000
+#define IPU_DI0_REG_BASE 0x00040000
+#define IPU_DI1_REG_BASE 0x00048000
+#define IPU_SMFC_REG_BASE 0x00050000
+#define IPU_DC_REG_BASE 0x00058000
+#define IPU_DMFC_REG_BASE 0x00060000
+#define IPU_VDI_REG_BASE 0x00680000
+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)
+#define IPU_CPMEM_REG_BASE 0x01000000
+#define IPU_LUT_REG_BASE 0x01020000
+#define IPU_SRM_REG_BASE 0x01040000
+#define IPU_TPM_REG_BASE 0x01060000
+#define IPU_DC_TMPL_REG_BASE 0x01080000
+#define IPU_ISP_TBPR_REG_BASE 0x010C0000
+#elif CONFIG_IS_ENABLED(MX6)
+#define IPU_CPMEM_REG_BASE 0x00100000
+#define IPU_LUT_REG_BASE 0x00120000
+#define IPU_SRM_REG_BASE 0x00140000
+#define IPU_TPM_REG_BASE 0x00160000
+#define IPU_DC_TMPL_REG_BASE 0x00180000
+#define IPU_ISP_TBPR_REG_BASE 0x001C0000
 #endif

-#define IPU_CTRL_BASE_ADDR	(IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
+#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)

 extern u32 *ipu_dc_tmpl_reg;

-#define DC_EVT_NF		0
-#define DC_EVT_NL		1
-#define DC_EVT_EOF		2
-#define DC_EVT_NFIELD		3
-#define DC_EVT_EOL		4
-#define DC_EVT_EOFIELD		5
-#define DC_EVT_NEW_ADDR		6
-#define DC_EVT_NEW_CHAN		7
-#define DC_EVT_NEW_DATA		8
+#define DC_EVT_NF 0
+#define DC_EVT_NL 1
+#define DC_EVT_EOF 2
+#define DC_EVT_NFIELD 3
+#define DC_EVT_EOL 4
+#define DC_EVT_EOFIELD 5
+#define DC_EVT_NEW_ADDR 6
+#define DC_EVT_NEW_CHAN 7
+#define DC_EVT_NEW_DATA 8

-#define DC_EVT_NEW_ADDR_W_0	0
-#define DC_EVT_NEW_ADDR_W_1	1
-#define DC_EVT_NEW_CHAN_W_0	2
-#define DC_EVT_NEW_CHAN_W_1	3
-#define DC_EVT_NEW_DATA_W_0	4
-#define DC_EVT_NEW_DATA_W_1	5
-#define DC_EVT_NEW_ADDR_R_0	6
-#define DC_EVT_NEW_ADDR_R_1	7
-#define DC_EVT_NEW_CHAN_R_0	8
-#define DC_EVT_NEW_CHAN_R_1	9
-#define DC_EVT_NEW_DATA_R_0	10
-#define DC_EVT_NEW_DATA_R_1	11
+#define DC_EVT_NEW_ADDR_W_0 0
+#define DC_EVT_NEW_ADDR_W_1 1
+#define DC_EVT_NEW_CHAN_W_0 2
+#define DC_EVT_NEW_CHAN_W_1 3
+#define DC_EVT_NEW_DATA_W_0 4
+#define DC_EVT_NEW_DATA_W_1 5
+#define DC_EVT_NEW_ADDR_R_0 6
+#define DC_EVT_NEW_ADDR_R_1 7
+#define DC_EVT_NEW_CHAN_R_0 8
+#define DC_EVT_NEW_CHAN_R_1 9
+#define DC_EVT_NEW_DATA_R_0 10
+#define DC_EVT_NEW_DATA_R_1 11

 /* Software reset for ipu */
-#define SW_IPU_RST	8
+#define SW_IPU_RST 8

 enum {
 	IPU_CONF_DP_EN = 0x00000020,
@@ -296,67 +298,63 @@ struct ipu_dmfc {
 	u32 stat;
 };

-#define IPU_CM_REG		((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
-				IPU_CM_REG_BASE))
-#define IPU_CONF		(&IPU_CM_REG->conf)
-#define IPU_SRM_PRI1		(&IPU_CM_REG->srm_pri1)
-#define IPU_SRM_PRI2		(&IPU_CM_REG->srm_pri2)
-#define IPU_FS_PROC_FLOW1	(&IPU_CM_REG->fs_proc_flow[0])
-#define IPU_FS_PROC_FLOW2	(&IPU_CM_REG->fs_proc_flow[1])
-#define IPU_FS_PROC_FLOW3	(&IPU_CM_REG->fs_proc_flow[2])
-#define IPU_FS_DISP_FLOW1	(&IPU_CM_REG->fs_disp_flow[0])
-#define IPU_DISP_GEN		(&IPU_CM_REG->disp_gen)
-#define IPU_MEM_RST		(&IPU_CM_REG->mem_rst)
-#define IPU_GPR			(&IPU_CM_REG->gpr)
-#define IPU_CHA_DB_MODE_SEL(ch)	(&IPU_CM_REG->ch_db_mode_sel[ch / 32])
+#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + IPU_CM_REG_BASE))
+#define IPU_CONF (&IPU_CM_REG->conf)
+#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
+#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
+#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
+#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
+#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
+#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
+#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
+#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
+#define IPU_GPR (&IPU_CM_REG->gpr)
+#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])

-#define IPU_STAT		((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
-				IPU_STAT_REG_BASE))
-#define IPU_INT_STAT(n)		(&IPU_STAT->int_stat[(n) - 1])
-#define IPU_CHA_CUR_BUF(ch)	(&IPU_STAT->cur_buf[ch / 32])
-#define IPU_CHA_BUF0_RDY(ch)	(&IPU_STAT->ch_buf0_rdy[ch / 32])
-#define IPU_CHA_BUF1_RDY(ch)	(&IPU_STAT->ch_buf1_rdy[ch / 32])
-#define IPUIRQ_2_STATREG(irq)	(IPU_INT_STAT(1) + ((irq) / 32))
-#define IPUIRQ_2_MASK(irq)	(1UL << ((irq) & 0x1F))
+#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + IPU_STAT_REG_BASE))
+#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1])
+#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
+#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
+#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
+#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))

-#define IPU_INT_CTRL(n)		(&IPU_CM_REG->int_ctrl[(n) - 1])
+#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])

-#define IDMAC_REG		((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
-				IPU_IDMAC_REG_BASE))
-#define IDMAC_CONF		(&IDMAC_REG->conf)
-#define IDMAC_CHA_EN(ch)	(&IDMAC_REG->ch_en[ch / 32])
-#define IDMAC_CHA_PRI(ch)	(&IDMAC_REG->ch_pri[ch / 32])
+#define IDMAC_REG \
+	((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + IPU_IDMAC_REG_BASE))
+#define IDMAC_CONF (&IDMAC_REG->conf)
+#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
+#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])

-#define DI_REG(di)		((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
-				((di == 1) ? IPU_DI1_REG_BASE : \
-				IPU_DI0_REG_BASE)))
-#define DI_GENERAL(di)		(&DI_REG(di)->general)
-#define DI_BS_CLKGEN0(di)	(&DI_REG(di)->bs_clkgen0)
-#define DI_BS_CLKGEN1(di)	(&DI_REG(di)->bs_clkgen1)
+#define DI_REG(di)                              \
+	((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
+			   ((di == 1) ? IPU_DI1_REG_BASE : IPU_DI0_REG_BASE)))
+#define DI_GENERAL(di) (&DI_REG(di)->general)
+#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
+#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)

-#define DI_SW_GEN0(di, gen)	(&DI_REG(di)->sw_gen0[gen - 1])
-#define DI_SW_GEN1(di, gen)	(&DI_REG(di)->sw_gen1[gen - 1])
-#define DI_STP_REP(di, gen)	(&DI_REG(di)->stp_rep[(gen - 1) / 2])
-#define DI_STP_REP9(di)		(&DI_REG(di)->stp_rep9)
-#define DI_SYNC_AS_GEN(di)	(&DI_REG(di)->sync_as)
-#define DI_DW_GEN(di, gen)	(&DI_REG(di)->dw_gen[gen])
-#define DI_DW_SET(di, gen, set)	(&DI_REG(di)->dw_set[gen + 12 * set])
-#define DI_POL(di)		(&DI_REG(di)->pol)
-#define DI_SCR_CONF(di)		(&DI_REG(di)->scr_conf)
+#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
+#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
+#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
+#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
+#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
+#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
+#define DI_POL(di) (&DI_REG(di)->pol)
+#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)

-#define DMFC_REG		((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
-				IPU_DMFC_REG_BASE))
-#define DMFC_WR_CHAN		(&DMFC_REG->wr_chan)
-#define DMFC_WR_CHAN_DEF	(&DMFC_REG->wr_chan_def)
-#define DMFC_DP_CHAN		(&DMFC_REG->dp_chan)
-#define DMFC_DP_CHAN_DEF	(&DMFC_REG->dp_chan_def)
-#define DMFC_GENERAL1		(&DMFC_REG->general[0])
-#define DMFC_IC_CTRL		(&DMFC_REG->ic_ctrl)
+#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + IPU_DMFC_REG_BASE))
+#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
+#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
+#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
+#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
+#define DMFC_GENERAL1 (&DMFC_REG->general[0])
+#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)

-#define DC_REG			((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
-				IPU_DC_REG_BASE))
-#define DC_MAP_CONF_PTR(n)	(&DC_REG->dc_map_ptr[n / 2])
-#define DC_MAP_CONF_VAL(n)	(&DC_REG->dc_map_val[n / 2])
+#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + IPU_DC_REG_BASE))
+#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
+#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])

 static inline struct ipu_dc_ch *dc_ch_offset(int ch)
 {
@@ -376,38 +374,36 @@ static inline struct ipu_dc_ch *dc_ch_offset(int ch)
 		printf("%s: invalid channel %d\n", __func__, ch);
 		return NULL;
 	}
-
 }

-#define DC_RL_CH(ch, evt)	(&dc_ch_offset(ch)->rl[evt / 2])
+#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])

-#define DC_WR_CH_CONF(ch)	(&dc_ch_offset(ch)->wr_ch_conf)
-#define DC_WR_CH_ADDR(ch)	(&dc_ch_offset(ch)->wr_ch_addr)
+#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
+#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)

-#define DC_WR_CH_CONF_1		DC_WR_CH_CONF(1)
-#define DC_WR_CH_CONF_5		DC_WR_CH_CONF(5)
+#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
+#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)

-#define DC_GEN			(&DC_REG->gen)
-#define DC_DISP_CONF2(disp)	(&DC_REG->disp_conf2[disp])
-#define DC_STAT			(&DC_REG->stat)
+#define DC_GEN (&DC_REG->gen)
+#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
+#define DC_STAT (&DC_REG->stat)

 #define DP_SYNC 0
 #define DP_ASYNC0 0x60
 #define DP_ASYNC1 0xBC

-#define DP_REG			((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
-				IPU_DP_REG_BASE))
-#define DP_COM_CONF()		(&DP_REG->com_conf_sync)
-#define DP_GRAPH_WIND_CTRL()	(&DP_REG->graph_wind_ctrl_sync)
-#define DP_CSC_A_0()		(&DP_REG->csca_sync[0])
-#define DP_CSC_A_1()		(&DP_REG->csca_sync[1])
-#define DP_CSC_A_2()		(&DP_REG->csca_sync[2])
-#define DP_CSC_A_3()		(&DP_REG->csca_sync[3])
+#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + IPU_DP_REG_BASE))
+#define DP_COM_CONF() (&DP_REG->com_conf_sync)
+#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
+#define DP_CSC_A_0() (&DP_REG->csca_sync[0])
+#define DP_CSC_A_1() (&DP_REG->csca_sync[1])
+#define DP_CSC_A_2() (&DP_REG->csca_sync[2])
+#define DP_CSC_A_3() (&DP_REG->csca_sync[3])

-#define DP_CSC_0()		(&DP_REG->csc_sync[0])
-#define DP_CSC_1()		(&DP_REG->csc_sync[1])
+#define DP_CSC_0() (&DP_REG->csc_sync[0])
+#define DP_CSC_1() (&DP_REG->csc_sync[1])

 /* DC template opcodes */
-#define WROD(lf)		(0x18 | (lf << 1))
+#define WROD(lf) (0x18 | (lf << 1))

 #endif
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -1,5 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Code fixes:
+ *
+ * (C) Copyright 2025
+ * Brian Ruley, GE HealthCare, brian.ruley@gehealthcare.com
+ *
 * Porting to u-boot:
 *
 * (C) Copyright 2010
@@ -10,25 +15,26 @@
 * (C) Copyright 2004-2010 Freescale Semiconductor, Inc.
 */

-#include <log.h>
-#include <part.h>
+#include "../videomodes.h"
+#include "display.h"
+#include "ipu.h"
+#include "ipu_regs.h"
+#include "mxcfb.h"
 #include <asm/cache.h>
-#include <linux/errno.h>
 #include <asm/global_data.h>
-#include <linux/string.h>
-#include <linux/list.h>
-#include <linux/fb.h>
 #include <asm/io.h>
 #include <asm/mach-imx/video.h>
-#include <malloc.h>
-#include "../videomodes.h"
-#include "ipu.h"
-#include "mxcfb.h"
-#include "ipu_regs.h"
-#include "display.h"
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/list.h>
+#include <linux/string.h>
+#include <log.h>
 #include <panel.h>
+#include <part.h>

 #include <dm.h>
+#include <dm/devres.h>
 #include <video.h>

 DECLARE_GLOBAL_DATA_PTR;
@@ -37,11 +43,11 @@ static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);

 static struct fb_videomode const *gmode;
-static uint8_t gdisp;
-static uint32_t gpixfmt;
+static u8 gdisp;
+static u32 gpixfmt;

 static void fb_videomode_to_var(struct fb_var_screeninfo *var,
-			 const struct fb_videomode *mode)
+				const struct fb_videomode *mode)
 {
 	var->xres = mode->xres;
 	var->yres = mode->yres;
@@ -60,6 +66,11 @@ static void fb_videomode_to_var(struct fb_var_screeninfo *var,
 	var->vmode = mode->vmode & FB_VMODE_MASK;
 }

+struct ipuv3_video_priv {
+	struct ipu_ctx *ctx;
+	ulong regs;
+};
+
 /*
 * Structure containing the MXC specific framebuffer information.
 */
@@ -67,7 +78,7 @@ struct mxcfb_info {
 	struct udevice *udev;
 	int blank;
 	ipu_channel_t ipu_ch;
-	int ipu_di;
+	struct ipu_di_config *di;
 	u32 ipu_di_pix_fmt;
 	unsigned char overlay;
 	unsigned char alpha_chan_en;
@@ -75,28 +86,25 @@ struct mxcfb_info {
 	dma_addr_t alpha_phy_addr1;
 	void *alpha_virt_addr0;
 	void *alpha_virt_addr1;
-	uint32_t alpha_mem_len;
-	uint32_t cur_ipu_buf;
-	uint32_t cur_ipu_alpha_buf;
+	u32 alpha_mem_len;
+	u32 cur_ipu_buf;
+	u32 cur_ipu_alpha_buf;

 	u32 pseudo_palette[16];
+
+	struct ipu_ctx *ctx;
 };

-enum {
-	BOTH_ON,
-	SRC_ON,
-	TGT_ON,
-	BOTH_OFF
-};
+enum { BOTH_ON, SRC_ON, TGT_ON, BOTH_OFF };

 static unsigned long default_bpp = 16;
 static unsigned char g_dp_in_use;
 static struct fb_info *mxcfb_info[3];
 static int ext_clk_used;

-static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+static u32 bpp_to_pixfmt(struct fb_info *fbi)
 {
-	uint32_t pixfmt = 0;
+	u32 pixfmt = 0;

 	debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);

@@ -123,7 +131,7 @@ static int setup_disp_channel1(struct fb_info *fbi)
 	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;

 	memset(&params, 0, sizeof(params));
-	params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
+	params.mem_dp_bg_sync.di = mxc_fbi->di->disp;

 	debug("%s called\n", __func__);
 	/*
@@ -132,24 +140,17 @@ static int setup_disp_channel1(struct fb_info *fbi)
 	 */
 	if (fbi->var.vmode & FB_VMODE_INTERLACED) {
 		params.mem_dp_bg_sync.interlaced = 1;
-		params.mem_dp_bg_sync.out_pixel_fmt =
-			IPU_PIX_FMT_YUV444;
+		params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_YUV444;
+	} else if (mxc_fbi->ipu_di_pix_fmt) {
+		params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
 	} else {
-		if (mxc_fbi->ipu_di_pix_fmt) {
-			params.mem_dp_bg_sync.out_pixel_fmt =
-				mxc_fbi->ipu_di_pix_fmt;
-		} else {
-			params.mem_dp_bg_sync.out_pixel_fmt =
-				IPU_PIX_FMT_RGB666;
-		}
+		params.mem_dp_bg_sync.out_pixel_fmt = IPU_PIX_FMT_RGB666;
 	}
 	params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi);
 	if (mxc_fbi->alpha_chan_en)
 		params.mem_dp_bg_sync.alpha_chan_en = 1;

-	ipu_init_channel(mxc_fbi->ipu_ch, &params);
-
-	return 0;
+	return ipu_init_channel(mxc_fbi->ctx, mxc_fbi->ipu_ch, &params);
 }

 static int setup_disp_channel2(struct fb_info *fbi)
@@ -163,24 +164,16 @@ static int setup_disp_channel2(struct fb_info *fbi)

 	fbi->var.xoffset = fbi->var.yoffset = 0;

-	debug("%s: %x %d %d %d %lx %lx\n",
-		__func__,
-		mxc_fbi->ipu_ch,
-		fbi->var.xres,
-		fbi->var.yres,
-		fbi->fix.line_length,
-		fbi->fix.smem_start,
-		fbi->fix.smem_start +
-		(fbi->fix.line_length * fbi->var.yres));
+	debug("%s: %x %d %d %d %lx %lx\n", __func__, mxc_fbi->ipu_ch,
+	      fbi->var.xres, fbi->var.yres, fbi->fix.line_length,
+	      fbi->fix.smem_start,
+	      fbi->fix.smem_start + (fbi->fix.line_length * fbi->var.yres));

-	retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
-					 bpp_to_pixfmt(fbi),
-					 fbi->var.xres, fbi->var.yres,
-					 fbi->fix.line_length,
-					 fbi->fix.smem_start +
-					 (fbi->fix.line_length * fbi->var.yres),
-					 fbi->fix.smem_start,
-					 0, 0);
+	retval = ipu_init_channel_buffer(
+		mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, bpp_to_pixfmt(fbi),
+		fbi->var.xres, fbi->var.yres, fbi->fix.line_length,
+		fbi->fix.smem_start + (fbi->fix.line_length * fbi->var.yres),
+		fbi->fix.smem_start, 0, 0);
 	if (retval)
 		printf("ipu_init_channel_buffer error %d\n", retval);

@@ -190,7 +183,7 @@ static int setup_disp_channel2(struct fb_info *fbi)
 /*
 * Set framebuffer parameters and change the operating mode.
 *
- * @param       info     framebuffer information pointer
+ * @param	info	 framebuffer information pointer
 */
 static int mxcfb_set_par(struct fb_info *fbi)
 {
@@ -198,10 +191,10 @@ static int mxcfb_set_par(struct fb_info *fbi)
 	u32 mem_len;
 	ipu_di_signal_cfg_t sig_cfg;
 	struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
-	uint32_t out_pixel_fmt;
+	u32 out_pixel_fmt;

-	ipu_disable_channel(mxc_fbi->ipu_ch);
-	ipu_uninit_channel(mxc_fbi->ipu_ch);
+	ipu_disable_channel(mxc_fbi->ctx, mxc_fbi->ipu_ch);
+	ipu_uninit_channel(mxc_fbi->ctx, mxc_fbi->ipu_ch);

 	mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
 	if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
@@ -229,9 +222,9 @@ static int mxcfb_set_par(struct fb_info *fbi)
 	if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)
 		sig_cfg.ext_clk = 1;
 	if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
-		sig_cfg.Hsync_pol = 1;
+		sig_cfg.hsync_pol = 1;
 	if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
-		sig_cfg.Vsync_pol = 1;
+		sig_cfg.vsync_pol = 1;
 	if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
 		sig_cfg.clk_pol = 1;
 	if (fbi->var.sync & FB_SYNC_DATA_INVERT)
@@ -243,17 +236,19 @@ static int mxcfb_set_par(struct fb_info *fbi)

 	debug("pixclock = %lu Hz\n", PICOS2KHZ(fbi->var.pixclock) * 1000UL);

-	if (ipu_init_sync_panel(mxc_fbi->ipu_di,
-				(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
-				fbi->var.xres, fbi->var.yres,
-				out_pixel_fmt,
-				fbi->var.left_margin,
-				fbi->var.hsync_len,
-				fbi->var.right_margin,
-				fbi->var.upper_margin,
-				fbi->var.vsync_len,
-				fbi->var.lower_margin,
-				0, sig_cfg) != 0) {
+	mxc_fbi->di->pixel_clk_rate = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL;
+	mxc_fbi->di->pixel_fmt = out_pixel_fmt;
+	mxc_fbi->di->width = fbi->var.xres;
+	mxc_fbi->di->height = fbi->var.yres;
+	mxc_fbi->di->h_start_width = fbi->var.left_margin;
+	mxc_fbi->di->h_sync_width = fbi->var.hsync_len;
+	mxc_fbi->di->h_end_width = fbi->var.right_margin;
+	mxc_fbi->di->v_start_width = fbi->var.upper_margin;
+	mxc_fbi->di->v_sync_width = fbi->var.vsync_len;
+	mxc_fbi->di->v_end_width = fbi->var.lower_margin;
+	mxc_fbi->di->v_to_h_sync = 0;
+
+	if (ipu_init_sync_panel(mxc_fbi->di, sig_cfg) != 0) {
 		puts("mxcfb: Error initializing panel.\n");
 		return -EINVAL;
 	}
@@ -263,7 +258,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
 		return retval;

 	if (mxc_fbi->blank == FB_BLANK_UNBLANK)
-		ipu_enable_channel(mxc_fbi->ipu_ch);
+		ipu_enable_channel(mxc_fbi->ctx, mxc_fbi->ipu_ch);

 	return retval;
 }
@@ -271,9 +266,9 @@ static int mxcfb_set_par(struct fb_info *fbi)
 /*
 * Check framebuffer variable parameters and adjust to valid values.
 *
- * @param       var      framebuffer variable parameters
+ * @param	var	 framebuffer variable parameters
 *
- * @param       info     framebuffer information pointer
+ * @param	info	 framebuffer information pointer
 */
 static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
@@ -362,13 +357,13 @@ static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)

 	if (var->pixclock < 1000) {
 		htotal = var->xres + var->right_margin + var->hsync_len +
-		    var->left_margin;
+			 var->left_margin;
 		vtotal = var->yres + var->lower_margin + var->vsync_len +
-		    var->upper_margin;
+			 var->upper_margin;
 		var->pixclock = (vtotal * htotal * 6UL) / 100UL;
 		var->pixclock = KHZ2PICOS(var->pixclock);
 		printf("pixclock set for 60Hz refresh = %u ps\n",
-			var->pixclock);
+		       var->pixclock);
 	}

 	var->height = -1;
@@ -384,8 +379,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 	struct video_uc_plat *plat = dev_get_uclass_plat(mxc_fbi->udev);

 	if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) {
-		fbi->fix.smem_len = fbi->var.yres_virtual *
-				    fbi->fix.line_length;
+		fbi->fix.smem_len =
+			fbi->var.yres_virtual * fbi->fix.line_length;
 	}
 	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);

@@ -400,7 +395,7 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 	}

 	debug("allocated fb @ paddr=0x%08X, size=%d.\n",
-		(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
+	      (u32)fbi->fix.smem_start, fbi->fix.smem_len);

 	fbi->screen_size = fbi->fix.smem_len;

@@ -422,43 +417,38 @@ static int mxcfb_unmap_video_memory(struct fb_info *fbi)
 * Initializes the framebuffer information pointer. After allocating
 * sufficient memory for the framebuffer structure, the fields are
 * filled with custom information passed in from the configurable
- * structures.  This includes information such as bits per pixel,
+ * structures.	This includes information such as bits per pixel,
 * color maps, screen width/height and RGBA offsets.
 *
- * Return:      Framebuffer structure initialized with our information
+ * @param	dev	The device structure for the IPU passed in by the
+ *			driver framework.
+ *
+ * Return:	Framebuffer structure initialized with our information
 */
-static struct fb_info *mxcfb_init_fbinfo(void)
+static struct fb_info *mxcfb_init_fbinfo(struct udevice *dev)
 {
 #define BYTES_PER_LONG 4
 #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
 	struct fb_info *fbi;
 	struct mxcfb_info *mxcfbi;
 	char *p;
-	int size = sizeof(struct mxcfb_info) + PADDING +
-		sizeof(struct fb_info);
+	int size = sizeof(struct mxcfb_info) + PADDING + sizeof(struct fb_info);

-	debug("%s: %d %d %d %d\n",
-		__func__,
-		PADDING,
-		size,
-		sizeof(struct mxcfb_info),
-		sizeof(struct fb_info));
+	debug("%s: %d %d %d %d\n", __func__, PADDING, size,
+	      sizeof(struct mxcfb_info), sizeof(struct fb_info));
 	/*
 	 * Allocate sufficient memory for the fb structure
 	 */
-
-	p = malloc(size);
+	p = devm_kzalloc(dev, size, GFP_KERNEL);
 	if (!p)
 		return NULL;

-	memset(p, 0, size);
-
 	fbi = (struct fb_info *)p;
 	fbi->par = p + sizeof(struct fb_info) + PADDING;

 	mxcfbi = (struct mxcfb_info *)fbi->par;
 	debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n",
-		(unsigned int)fbi, (unsigned int)mxcfbi);
+	      (unsigned int)fbi, (unsigned int)mxcfbi);

 	fbi->var.activate = FB_ACTIVATE_NOW;

@@ -468,26 +458,26 @@ static struct fb_info *mxcfb_init_fbinfo(void)
 	return fbi;
 }

-extern struct clk *g_ipu_clk;
-
 /*
 * Probe routine for the framebuffer driver. It is called during the
 * driver binding process. The following functions are performed in
 * this routine: Framebuffer initialization, Memory allocation and
 * mapping, Framebuffer registration, IPU initialization.
 *
- * Return:      Appropriate error code to the kernel common code
+ * Return:	Appropriate error code to the kernel common code
 */
-static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,
-		       uint8_t disp, struct fb_videomode const *mode)
+static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, u8 disp,
+		       struct fb_videomode const *mode)
 {
+	struct ipuv3_video_priv *ipu_priv = dev_get_priv(dev);
+	struct ipu_ctx *ctx = ipu_priv->ctx;
 	struct fb_info *fbi;
 	struct mxcfb_info *mxcfbi;

 	/*
 	 * Initialize FB structures
 	 */
-	fbi = mxcfb_init_fbinfo();
+	fbi = mxcfb_init_fbinfo(dev);
 	if (!fbi)
 		return -ENOMEM;

@@ -501,26 +491,32 @@ static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,
 		mxcfbi->blank = FB_BLANK_POWERDOWN;
 	}

-	mxcfbi->ipu_di = disp;
+	mxcfbi->di = devm_kzalloc(ctx->dev, sizeof(*mxcfbi->di), GFP_KERNEL);
+	if (!mxcfbi->di)
+		return -ENOMEM;
+
+	mxcfbi->di->disp = disp;
+	mxcfbi->di->ctx = ctx;
+	mxcfbi->ctx = ctx;
 	mxcfbi->udev = dev;

-	if (!ipu_clk_enabled())
-		clk_enable(g_ipu_clk);
+	if (!ipu_clk_enabled(ctx))
+		clk_enable(ctx->ipu_clk);

 	ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80);
 	ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0);

 	g_dp_in_use = 1;

-	mxcfb_info[mxcfbi->ipu_di] = fbi;
+	mxcfb_info[mxcfbi->di->disp] = fbi;

 	/* Need dummy values until real panel is configured */

 	mxcfbi->ipu_di_pix_fmt = interface_pix_fmt;
 	fb_videomode_to_var(&fbi->var, mode);
 	fbi->var.bits_per_pixel = 16;
-	fbi->fix.line_length = fbi->var.xres_virtual *
-			       (fbi->var.bits_per_pixel / 8);
+	fbi->fix.line_length =
+		fbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);
 	fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length;

 	mxcfb_check_var(&fbi->var, fbi);
@@ -541,20 +537,22 @@ static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt,
 	return 0;
 }

-void ipuv3_fb_shutdown(void)
+void ipuv3_fb_shutdown(struct udevice *dev)
 {
 	int i;
 	struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
+	struct ipuv3_video_priv *ipu_priv = dev_get_priv(dev);
+	struct ipu_ctx *ctx = ipu_priv->ctx;

-	if (!ipu_clk_enabled())
+	if (!ipu_clk_enabled(ctx))
 		return;

 	for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
 		struct fb_info *fbi = mxcfb_info[i];
 		if (fbi) {
 			struct mxcfb_info *mxc_fbi = fbi->par;
-			ipu_disable_channel(mxc_fbi->ipu_ch);
-			ipu_uninit_channel(mxc_fbi->ipu_ch);
+			ipu_disable_channel(ctx, mxc_fbi->ipu_ch);
+			ipu_uninit_channel(ctx, mxc_fbi->ipu_ch);
 		}
 	}
 	for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
@@ -563,9 +561,7 @@ void ipuv3_fb_shutdown(void)
 	}
 }

-int ipuv3_fb_init(struct fb_videomode const *mode,
-		  uint8_t disp,
-		  uint32_t pixfmt)
+int ipuv3_fb_init(struct fb_videomode const *mode, u8 disp, u32 pixfmt)
 {
 	gmode = mode;
 	gdisp = disp;
@@ -576,27 +572,31 @@ int ipuv3_fb_init(struct fb_videomode const *mode,

 enum {
 	/* Maximum display size we support */
-	LCD_MAX_WIDTH		= 1920,
-	LCD_MAX_HEIGHT		= 1080,
-	LCD_MAX_LOG2_BPP	= VIDEO_BPP16,
+	LCD_MAX_WIDTH = 1920,
+	LCD_MAX_HEIGHT = 1080,
+	LCD_MAX_LOG2_BPP = VIDEO_BPP16,
 };

 static int ipuv3_video_probe(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct ipuv3_video_priv *ipu_priv = dev_get_priv(dev);
 #if defined(CONFIG_DISPLAY)
 	struct udevice *disp_dev;
 #endif
+	struct ipu_ctx *ctx;
 	u32 fb_start, fb_end;
 	int ret;

-	debug("%s() plat: base 0x%lx, size 0x%x\n",
-	      __func__, plat->base, plat->size);
+	debug("%s() plat: base 0x%lx, size 0x%x\n", __func__, plat->base,
+	      plat->size);

-	ret = ipu_probe();
-	if (ret)
-		return ret;
+	ctx = ipu_probe(dev);
+	if (IS_ERR(ctx))
+		return PTR_ERR(ctx);
+
+	ipu_priv->ctx = ctx;

 	ret = ipu_displays_init();
 	if (ret < 0)
@@ -636,16 +636,11 @@ static int ipuv3_video_probe(struct udevice *dev)
 	return 0;
 }

-struct ipuv3_video_priv {
-	ulong regs;
-};
-
 static int ipuv3_video_bind(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);

-	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
-		     (1 << VIDEO_BPP32) / 8;
+	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * (1 << VIDEO_BPP32) / 8;

 	return 0;
 }
@@ -657,15 +652,15 @@ static const struct udevice_id ipuv3_video_ids[] = {
 #ifdef CONFIG_ARCH_MX5
 	{ .compatible = "fsl,imx53-ipu" },
 #endif
-	{ }
+	{}
 };

 U_BOOT_DRIVER(fsl_imx6q_ipu) = {
-	.name	= "fsl_imx6q_ipu",
-	.id	= UCLASS_VIDEO,
+	.name = "fsl_imx6q_ipu",
+	.id = UCLASS_VIDEO,
 	.of_match = ipuv3_video_ids,
-	.bind	= ipuv3_video_bind,
-	.probe	= ipuv3_video_probe,
-	.priv_auto	= sizeof(struct ipuv3_video_priv),
-	.flags	= DM_FLAG_PRE_RELOC,
+	.bind = ipuv3_video_bind,
+	.probe = ipuv3_video_probe,
+	.priv_auto = sizeof(struct ipuv3_video_priv),
+	.flags = DM_FLAG_PRE_RELOC,
 };
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -159,7 +159,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 		vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 	if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
 		vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
-	if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+	if (flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
 		vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
 	if(flags & DISPLAY_FLAGS_DE_HIGH)
 		vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -21,30 +21,6 @@
 #define CFG_FEC_MXC_PHYADDR		1
 #endif

-#ifdef CONFIG_DISTRO_DEFAULTS
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0)
-
-#include <config_distro_bootcmd.h>
-#else
-#define BOOTENV
-#endif
-
-/* Initial environment variables */
-#define CFG_EXTRA_ENV_SETTINGS		\
-	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"image=Image\0" \
-	"console=ttyLP1,115200 earlycon\0" \
-	"fdt_addr_r=0x83000000\0"			\
-	"boot_fit=no\0" \
-	"fdtfile=imx8ulp-evk.dtb\0" \
-	"initrd_addr=0x83800000\0"		\
-	"bootm_size=0x10000000\0" \
-	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
-
 /* Link Definitions */

 #define CFG_SYS_INIT_RAM_ADDR	0x80000000
--- a/include/configs/imx91_frdm.h
+++ b/include/configs/imx91_frdm.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX91_FRDM_H
+#define __IMX91_FRDM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE	0x200000
+
+#define CFG_SYS_SDRAM_BASE	0x80000000
+#define PHYS_SDRAM		0x80000000
+#define PHYS_SDRAM_SIZE		SZ_2G /* 2GB DDR */
+
+#define WDOG_BASE_ADDR		WDG3_BASE_ADDR
+
+#endif
--- a/include/ipu_pixfmt.h
+++ b/include/ipu_pixfmt.h
@@ -11,6 +11,7 @@
 #ifndef __IPU_PIXFMT_H__
 #define __IPU_PIXFMT_H__

+#include <dm/device.h>
 #include <linux/list.h>
 #include <linux/fb.h>

@@ -62,6 +63,6 @@
 int ipuv3_fb_init(struct fb_videomode const *mode,
 		  uint8_t disp,
 		  uint32_t pixfmt);
-void ipuv3_fb_shutdown(void);
+void ipuv3_fb_shutdown(struct udevice *dev);

 #endif