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imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

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At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2023-01-31 16:42:21 +08:00
committed by Stefano Babic
parent e01d1b1e30
commit 4e08a510d2
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-imx/imx8ulp/cgc.c
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@@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq)
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
;
clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));