mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
arm: dts: imx8mm: Sync with linux-next 20231019
Sync imx8mm.dtsi with linux-next 20231019. The motivation for doing this sync was a bug when doing "ums 0 mmc 1" on imx8mm-evk. It worked well for the first time, but after doing a CTRL+C and launching the ums again, the command did not work. Adam Ford suggested to sync imx8mm.dtsi with the Linux dts, as there was a recent USB power domain reorganization there. After syncing the imx8mm.dtsi with Linux, the ums command works without problem after a CTRL+C. Suggested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
This commit is contained in:
Fabio Estevam
committed by
Fabio Estevam
Fabio Estevam
parent
ae09edaeec
commit
5037bd532d
@@ -139,6 +139,7 @@
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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@@ -276,6 +277,7 @@
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assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
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clock-names = "main_clk";
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power-domains = <&pgc_otg1>;
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};
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usbphynop2: usbphynop2 {
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@@ -285,6 +287,7 @@
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assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
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clock-names = "main_clk";
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power-domains = <&pgc_otg2>;
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};
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soc: soc@0 {
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@@ -396,6 +399,7 @@
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"pll8k", "pll11k", "clkext3";
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dmas = <&sdma2 24 25 0x80000000>;
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dma-names = "rx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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@@ -493,6 +497,8 @@
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compatible = "fsl,imx8mm-tmu";
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reg = <0x30260000 0x10000>;
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clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
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nvmem-cells = <&tmu_calib>;
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nvmem-cell-names = "calib";
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#thermal-sensor-cells = <0>;
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};
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@@ -547,8 +553,8 @@
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reg = <0x30330000 0x10000>;
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};
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gpr: iomuxc-gpr@30340000 {
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compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
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gpr: syscon@30340000 {
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compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
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reg = <0x30340000 0x10000>;
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};
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@@ -560,22 +566,40 @@
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#address-cells = <1>;
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#size-cells = <1>;
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imx8mm_uid: unique-id@410 {
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/*
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* The register address below maps to the MX8M
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* Fusemap Description Table entries this way.
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* Assuming
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* reg = <ADDR SIZE>;
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* then
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* Fuse Address = (ADDR * 4) + 0x400
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* Note that if SIZE is greater than 4, then
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* each subsequent fuse is located at offset
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* +0x10 in Fusemap Description Table (e.g.
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* reg = <0x4 0x8> describes fuses 0x410 and
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* 0x420).
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*/
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imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
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reg = <0x4 0x8>;
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};
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cpu_speed_grade: speed-grade@10 {
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cpu_speed_grade: speed-grade@10 { /* 0x440 */
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reg = <0x10 4>;
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};
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fec_mac_address: mac-address@90 {
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tmu_calib: calib@3c { /* 0x4f0 */
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reg = <0x3c 4>;
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};
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fec_mac_address: mac-address@90 { /* 0x640 */
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reg = <0x90 6>;
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};
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};
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anatop: anatop@30360000 {
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compatible = "fsl,imx8mm-anatop", "syscon";
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anatop: clock-controller@30360000 {
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compatible = "fsl,imx8mm-anatop";
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reg = <0x30360000 0x10000>;
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#clock-cells = <1>;
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};
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snvs: snvs@30370000 {
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@@ -674,13 +698,11 @@
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pgc_otg1: power-domain@2 {
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#power-domain-cells = <0>;
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reg = <IMX8MM_POWER_DOMAIN_OTG1>;
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power-domains = <&pgc_hsiomix>;
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};
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pgc_otg2: power-domain@3 {
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#power-domain-cells = <0>;
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reg = <IMX8MM_POWER_DOMAIN_OTG2>;
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power-domains = <&pgc_hsiomix>;
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};
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pgc_gpumix: power-domain@4 {
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@@ -1098,6 +1120,61 @@
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#size-cells = <1>;
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ranges = <0x32c00000 0x32c00000 0x400000>;
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lcdif: lcdif@32e00000 {
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compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
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reg = <0x32e00000 0x10000>;
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clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
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<&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
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clock-names = "pix", "axi", "disp_axi";
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assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
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<&clk IMX8MM_CLK_DISP_AXI>,
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<&clk IMX8MM_CLK_DISP_APB>;
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assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
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<&clk IMX8MM_SYS_PLL2_1000M>,
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<&clk IMX8MM_SYS_PLL1_800M>;
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assigned-clock-rates = <594000000>, <500000000>, <200000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
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status = "disabled";
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port {
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lcdif_to_dsim: endpoint {
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remote-endpoint = <&dsim_from_lcdif>;
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};
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};
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};
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mipi_dsi: dsi@32e10000 {
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compatible = "fsl,imx8mm-mipi-dsim";
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reg = <0x32e10000 0x400>;
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clocks = <&clk IMX8MM_CLK_DSI_CORE>,
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<&clk IMX8MM_CLK_DSI_PHY_REF>;
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clock-names = "bus_clk", "sclk_mipi";
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assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
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<&clk IMX8MM_CLK_DSI_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
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<&clk IMX8MM_CLK_24M>;
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assigned-clock-rates = <266000000>, <24000000>;
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samsung,pll-clock-frequency = <24000000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsim_from_lcdif: endpoint {
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remote-endpoint = <&lcdif_to_dsim>;
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};
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};
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};
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};
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csi: csi@32e20000 {
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compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
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reg = <0x32e20000 0x1000>;
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@@ -1145,10 +1222,9 @@
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compatible = "fsl,imx8mm-mipi-csi2";
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reg = <0x32e30000 0x1000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
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<&clk IMX8MM_CLK_CSI1_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
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<&clk IMX8MM_SYS_PLL2_1000M>;
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assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
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clock-frequency = <333000000>;
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clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_CSI1_ROOT>,
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@@ -1177,7 +1253,7 @@
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};
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usbotg1: usb@32e40000 {
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compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
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compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
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reg = <0x32e40000 0x200>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
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@@ -1186,18 +1262,19 @@
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
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phys = <&usbphynop1>;
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fsl,usbmisc = <&usbmisc1 0>;
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power-domains = <&pgc_otg1>;
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power-domains = <&pgc_hsiomix>;
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status = "disabled";
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};
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usbmisc1: usbmisc@32e40200 {
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compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
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compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
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"fsl,imx6q-usbmisc";
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#index-cells = <1>;
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reg = <0x32e40200 0x200>;
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};
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usbotg2: usb@32e50000 {
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compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
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compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
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reg = <0x32e50000 0x200>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
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@@ -1206,12 +1283,13 @@
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
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phys = <&usbphynop2>;
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fsl,usbmisc = <&usbmisc2 0>;
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power-domains = <&pgc_otg2>;
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power-domains = <&pgc_hsiomix>;
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status = "disabled";
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};
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usbmisc2: usbmisc@32e50200 {
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compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
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compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
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"fsl,imx6q-usbmisc";
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#index-cells = <1>;
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reg = <0x32e50200 0x200>;
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};
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@@ -1238,16 +1316,15 @@
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
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};
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gpmi: nand-controller@33002000{
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gpmi: nand-controller@33002000 {
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compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <0>;
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reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1268,8 +1345,8 @@
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
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0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
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ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
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<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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num-viewport = <4>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1282,6 +1359,10 @@
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<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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fsl,max-link-speed = <2>;
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linux,pci-domain = <0>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
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<&clk IMX8MM_CLK_PCIE1_PHY>,
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<&clk IMX8MM_CLK_PCIE1_AUX>;
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clock-names = "pcie", "pcie_bus", "pcie_aux";
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power-domains = <&pgc_pcie>;
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resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
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<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
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@@ -1291,6 +1372,30 @@
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status = "disabled";
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};
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pcie0_ep: pcie-ep@33800000 {
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compatible = "fsl,imx8mm-pcie-ep";
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reg = <0x33800000 0x400000>,
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<0x18000000 0x8000000>;
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reg-names = "dbi", "addr_space";
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num-lanes = <1>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dma";
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fsl,max-link-speed = <2>;
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clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
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<&clk IMX8MM_CLK_PCIE1_PHY>,
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<&clk IMX8MM_CLK_PCIE1_AUX>;
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clock-names = "pcie", "pcie_bus", "pcie_aux";
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power-domains = <&pgc_pcie>;
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resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
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<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
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reset-names = "apps", "turnoff";
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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num-ib-windows = <4>;
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num-ob-windows = <4>;
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status = "disabled";
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};
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gpu_3d: gpu@38000000 {
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compatible = "vivante,gc";
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reg = <0x38000000 0x8000>;
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