Merge patch series "64-bit PCIe for AM64, AM69, J7200, J722S and J784S4"

Siddharth Vadapalli <s-vadapalli@ti.com> says:

Since Linux device-tree has switched to 64-bit Address space for the
PCIe Controllers on TI SoCs, currently, U-Boot needs to support the
same. This series adds support for 64-bit addressing for PCIe along with
enabling Root-Complex mode of operation for AM69 and J784S4 SoCs.

Series has been tested on all platforms being affected by this series.
Test Logs:
1. AM642-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/82512389f8396a51e4f167c7ebe4c2a3
2. AM69-SK
https://gist.github.com/Siddharth-Vadapalli-at-TI/b20b2811804ffc6e6c063564330c0a35
3. J7200-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/c545da68bd28a5e036803bb60f32d8e9
4. J722S-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/3dde05c4c7076076aa20ac47a6e2d176
5. J784S4-EVM
https://gist.github.com/Siddharth-Vadapalli-at-TI/a93c1b2cd5d90f494e885d1831d3d23e

Link: https://lore.kernel.org/r/20260227115841.333073-1-s-vadapalli@ti.com

arch/arm/mach-k3/arm64/arm64-mmu.c

@@ -29,6 +29,22 @@ struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, { /*
+	      * PCIe 4 GB Address Window for AM64 and J722S SoCs starts
+	      * from 0x6_0000_0000 and has a size of 0x1_0000_0000.
+	      * Since this is already enabled by the 'Flash Peripherals'
+	      * region above, we don't need to add it again.
+	      *
+	      * The PCIe 4 GB Address Windows for AM68, AM69, J7200, J721E,
+	      * J721S2, J742S2 and J784S4 SoCs are enabled by the following
+	      * region.
+	      */
+		.virt = 0x4000000000UL,
+		.phys = 0x4000000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	}, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */
 		.virt = CFG_SYS_SDRAM_BASE,
 		.phys = CFG_SYS_SDRAM_BASE,

arch/arm/mach-k3/include/mach/k3-ddr.h

@@ -8,11 +8,14 @@
 
 #include <spl.h>
 
-/* We need 3 extra entries for:
- *   SoC peripherals, flash and the sentinel value.
+/* We need 4 extra entries for:
+ * 1. SoC peripherals
+ * 2. Flash
+ * 3. PCIe 4GB Windows for AM68, AM69, J7200, J721E, J721S2, J742S2 and J784S4 SoCs
+ * 4. Sentinel value
  */
-#define K3_MEM_MAP_LEN			((CONFIG_NR_DRAM_BANKS) + 3)
-#define K3_MEM_MAP_FIRST_BANK_IDX	2
+#define K3_MEM_MAP_LEN			((CONFIG_NR_DRAM_BANKS) + 4)
+#define K3_MEM_MAP_FIRST_BANK_IDX	3
 
 int dram_init(void);
 int dram_init_banksize(void);

configs/am64x_evm_a53_defconfig

@@ -31,6 +31,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTSTD_FULL=y

configs/j7200_evm_a72_defconfig

@@ -30,6 +30,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 # CONFIG_PSCI_RESET is not set
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTSTD_FULL=y

configs/j722s_evm_a53_defconfig

@@ -27,6 +27,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_PCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_BOOTSTD_FULL=y

configs/j784s4_evm_a72_defconfig

@@ -28,6 +28,8 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_EFI_SET_TIME=y
 CONFIG_BOOTSTD_FULL=y
 CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
@@ -56,6 +58,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_OF_CONTROL=y
@@ -123,6 +126,9 @@ CONFIG_MUX_MMIO=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI_CONFIG_HOST_BRIDGE=y
+CONFIG_PCIE_CDNS_TI=y
 CONFIG_PCI_ENDPOINT=y
 CONFIG_PCIE_CDNS_TI_EP=y
 CONFIG_PHY=y

drivers/pci/pcie_cdns_ti.c

@@ -860,6 +860,12 @@ static const struct pcie_cdns_ti_data j722s_pcie_rc_data = {
 	.max_lanes = 1,
 };
 
+static const struct pcie_cdns_ti_data j784s4_pcie_rc_data = {
+	.mode = PCIE_MODE_RC,
+	.quirk_detect_quiet_flag = true,
+	.max_lanes = 4,
+};
+
 static const struct udevice_id pcie_cdns_ti_ids[] = {
 	{
 		.compatible = "ti,j7200-pcie-host",
@@ -873,6 +879,10 @@ static const struct udevice_id pcie_cdns_ti_ids[] = {
 		.compatible = "ti,j722s-pcie-host",
 		.data = (ulong)&j722s_pcie_rc_data,
 	},
+	{
+		.compatible = "ti,j784s4-pcie-host",
+		.data = (ulong)&j784s4_pcie_rc_data,
+	},
 	{},
 };