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clk: at91: Add ACR in all PLL setting.

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Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
This commit is contained in:
Manikandan Muralidharan
2025-09-23 15:28:17 +05:30
committed by Eugen Hristev
parent bf1d8c1fec
commit 57d88e78a8
5 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/at91/pmc.h
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@@ -42,6 +42,7 @@ struct clk_pll_characteristics {
u16 *icpll;
u8 *out;
u8 upll : 1;
u32 acr;
};
struct clk_pll_layout {

2
drivers/clk/at91/sam9x60.c
View File

@@ -123,6 +123,7 @@ static const struct clk_pll_characteristics apll_characteristics = {
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.core_output = core_outputs,
.acr = 0x00020010UL,
};
static const struct clk_pll_characteristics upll_characteristics = {
@@ -131,6 +132,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
.output = upll_outputs,
.core_output = core_outputs,
.upll = true,
.acr = 0x12023010UL, /* fIN = [18 MHz, 32 MHz]*/
};
/* Layout for fractional PLLs. */

5
drivers/clk/at91/sam9x7.c
View File

@@ -164,6 +164,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.core_output = plla_core_outputs,
.acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */
};
static const struct clk_pll_characteristics upll_characteristics = {
@@ -172,6 +173,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
.output = upll_outputs,
.core_output = upll_core_outputs,
.upll = true,
.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
};
static const struct clk_pll_characteristics lvdspll_characteristics = {
@@ -179,6 +181,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
.num_output = ARRAY_SIZE(lvdspll_outputs),
.output = lvdspll_outputs,
.core_output = lvdspll_core_outputs,
.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
};
static const struct clk_pll_characteristics audiopll_characteristics = {
@@ -186,6 +189,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = {
.num_output = ARRAY_SIZE(audiopll_outputs),
.output = audiopll_outputs,
.core_output = audiopll_core_outputs,
.acr = 0x12023010UL, /* fIN=[20 MHz, 32 MHz] */
};
static const struct clk_pll_characteristics plladiv2_characteristics = {
@@ -193,6 +197,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = {
.num_output = ARRAY_SIZE(plladiv2_outputs),
.output = plladiv2_outputs,
.core_output = plladiv2_core_outputs,
.acr = 0x00020010UL, /* Old ACR_DEFAULT_PLLA value */
};
/* Layout for fractional PLLs. */

1
drivers/clk/at91/sama7d65.c
View File

@@ -184,6 +184,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
.num_output = ARRAY_SIZE(pll_outputs),
.output = pll_outputs,
.core_output = core_outputs,
.acr = 0x00070010UL,
};
/* Layout for fractional PLLs. */

1
drivers/clk/at91/sama7g5.c
View File

@@ -169,6 +169,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
.num_output = ARRAY_SIZE(pll_outputs),
.output = pll_outputs,
.core_output = core_outputs,
.acr = 0x00070010UL,
};
/* Layout for fractional PLLs. */