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clk: mediatek: mt8188: add missing fixed clock
CLK_TOP_CLK13M was missing, add it. Signed-off-by: Julien Stephan <jstephan@baylibre.com>
This commit is contained in:
Julien Stephan
@@ -98,6 +98,7 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
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FIXED_CLK0(CLK_TOP_466M_FMEM, 533000000),
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FIXED_CLK0(CLK_TOP_PEXTP_PIPE, 250000000),
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FIXED_CLK0(CLK_TOP_DSI_PHY, 500000000),
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FIXED_CLK0(CLK_TOP_CLK13M, 130000000),
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FIXED_CLK0(CLK_TOP_CLK26M, 260000000),
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FIXED_CLK0(CLK_TOP_CLK32K, 32000),
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};
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@@ -1143,180 +1144,180 @@ static const struct mtk_composite top_muxes[] = {
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};
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static const int mt8188_id_offs_map[] = {
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87, /* CLK_TOP_AXI */
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88, /* CLK_TOP_SPM */
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89, /* CLK_TOP_SCP */
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90, /* CLK_TOP_BUS_AXIMEM */
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91, /* CLK_TOP_VPP */
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92, /* CLK_TOP_ETHDR */
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93, /* CLK_TOP_IPE */
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94, /* CLK_TOP_CAM */
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95, /* CLK_TOP_CCU */
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96, /* CLK_TOP_CCU_AHB */
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97, /* CLK_TOP_IMG */
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98, /* CLK_TOP_CAMTM */
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99, /* CLK_TOP_DSP */
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100, /* CLK_TOP_DSP1 */
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101, /* CLK_TOP_DSP2 */
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102, /* CLK_TOP_DSP3 */
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103, /* CLK_TOP_DSP4 */
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104, /* CLK_TOP_DSP5 */
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105, /* CLK_TOP_DSP6 */
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106, /* CLK_TOP_DSP7 */
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107, /* CLK_TOP_MFG_CORE_TMP */
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108, /* CLK_TOP_CAMTG */
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109, /* CLK_TOP_CAMTG2 */
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110, /* CLK_TOP_CAMTG3 */
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111, /* CLK_TOP_UART */
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112, /* CLK_TOP_SPI */
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113, /* CLK_TOP_MSDC50_0_HCLK */
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114, /* CLK_TOP_MSDC50_0 */
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115, /* CLK_TOP_MSDC30_1 */
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116, /* CLK_TOP_MSDC30_2 */
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117, /* CLK_TOP_INTDIR */
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118, /* CLK_TOP_AUD_INTBUS */
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119, /* CLK_TOP_AUDIO_H */
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120, /* CLK_TOP_PWRAP_ULPOSC */
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121, /* CLK_TOP_ATB */
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122, /* CLK_TOP_SSPM */
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123, /* CLK_TOP_DP */
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124, /* CLK_TOP_EDP */
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125, /* CLK_TOP_DPI */
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126, /* CLK_TOP_DISP_PWM0 */
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127, /* CLK_TOP_DISP_PWM1 */
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128, /* CLK_TOP_USB_TOP */
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129, /* CLK_TOP_SSUSB_XHCI */
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130, /* CLK_TOP_USB_TOP_2P */
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131, /* CLK_TOP_SSUSB_XHCI_2P */
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132, /* CLK_TOP_USB_TOP_3P */
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133, /* CLK_TOP_SSUSB_XHCI_3P */
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134, /* CLK_TOP_I2C */
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135, /* CLK_TOP_SENINF */
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136, /* CLK_TOP_SENINF1 */
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137, /* CLK_TOP_GCPU */
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138, /* CLK_TOP_VENC */
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139, /* CLK_TOP_VDEC */
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140, /* CLK_TOP_PWM */
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141, /* CLK_TOP_MCUPM */
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142, /* CLK_TOP_SPMI_P_MST */
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143, /* CLK_TOP_SPMI_M_MST */
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144, /* CLK_TOP_DVFSRC */
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145, /* CLK_TOP_TL */
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146, /* CLK_TOP_AES_MSDCFDE */
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147, /* CLK_TOP_DSI_OCC */
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148, /* CLK_TOP_WPE_VPP */
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149, /* CLK_TOP_HDCP */
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150, /* CLK_TOP_HDCP_24M */
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151, /* CLK_TOP_HDMI_APB */
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152, /* CLK_TOP_SNPS_ETH_250M */
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153, /* CLK_TOP_SNPS_ETH_62P4M_PTP */
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154, /* CLK_TOP_SNPS_ETH_50M_RMII */
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155, /* CLK_TOP_ADSP */
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156, /* CLK_TOP_AUDIO_LOCAL_BUS */
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157, /* CLK_TOP_ASM_H */
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158, /* CLK_TOP_ASM_L */
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159, /* CLK_TOP_APLL1 */
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160, /* CLK_TOP_APLL2 */
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161, /* CLK_TOP_APLL3 */
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162, /* CLK_TOP_APLL4 */
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163, /* CLK_TOP_APLL5 */
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164, /* CLK_TOP_I2SO1 */
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165, /* CLK_TOP_I2SO2 */
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166, /* CLK_TOP_I2SI1 */
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167, /* CLK_TOP_I2SI2 */
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168, /* CLK_TOP_DPTX */
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169, /* CLK_TOP_AUD_IEC */
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170, /* CLK_TOP_A1SYS_HP */
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171, /* CLK_TOP_A2SYS */
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172, /* CLK_TOP_A3SYS */
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173, /* CLK_TOP_A4SYS */
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174, /* CLK_TOP_ECC */
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175, /* CLK_TOP_SPINOR */
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176, /* CLK_TOP_ULPOSC */
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177, /* CLK_TOP_SRCK */
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88, /* CLK_TOP_AXI */
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89, /* CLK_TOP_SPM */
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90, /* CLK_TOP_SCP */
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91, /* CLK_TOP_BUS_AXIMEM */
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92, /* CLK_TOP_VPP */
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93, /* CLK_TOP_ETHDR */
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94, /* CLK_TOP_IPE */
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95, /* CLK_TOP_CAM */
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96, /* CLK_TOP_CCU */
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97, /* CLK_TOP_CCU_AHB */
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98, /* CLK_TOP_IMG */
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99, /* CLK_TOP_CAMTM */
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100, /* CLK_TOP_DSP */
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101, /* CLK_TOP_DSP1 */
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102, /* CLK_TOP_DSP2 */
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103, /* CLK_TOP_DSP3 */
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104, /* CLK_TOP_DSP4 */
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105, /* CLK_TOP_DSP5 */
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106, /* CLK_TOP_DSP6 */
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107, /* CLK_TOP_DSP7 */
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108, /* CLK_TOP_MFG_CORE_TMP */
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109, /* CLK_TOP_CAMTG */
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110, /* CLK_TOP_CAMTG2 */
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111, /* CLK_TOP_CAMTG3 */
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112, /* CLK_TOP_UART */
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113, /* CLK_TOP_SPI */
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114, /* CLK_TOP_MSDC50_0_HCLK */
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115, /* CLK_TOP_MSDC50_0 */
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116, /* CLK_TOP_MSDC30_1 */
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117, /* CLK_TOP_MSDC30_2 */
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118, /* CLK_TOP_INTDIR */
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119, /* CLK_TOP_AUD_INTBUS */
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120, /* CLK_TOP_AUDIO_H */
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121, /* CLK_TOP_PWRAP_ULPOSC */
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122, /* CLK_TOP_ATB */
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123, /* CLK_TOP_SSPM */
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124, /* CLK_TOP_DP */
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125, /* CLK_TOP_EDP */
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126, /* CLK_TOP_DPI */
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127, /* CLK_TOP_DISP_PWM0 */
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128, /* CLK_TOP_DISP_PWM1 */
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129, /* CLK_TOP_USB_TOP */
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130, /* CLK_TOP_SSUSB_XHCI */
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131, /* CLK_TOP_USB_TOP_2P */
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132, /* CLK_TOP_SSUSB_XHCI_2P */
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133, /* CLK_TOP_USB_TOP_3P */
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134, /* CLK_TOP_SSUSB_XHCI_3P */
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135, /* CLK_TOP_I2C */
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136, /* CLK_TOP_SENINF */
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137, /* CLK_TOP_SENINF1 */
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138, /* CLK_TOP_GCPU */
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139, /* CLK_TOP_VENC */
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140, /* CLK_TOP_VDEC */
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141, /* CLK_TOP_PWM */
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142, /* CLK_TOP_MCUPM */
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143, /* CLK_TOP_SPMI_P_MST */
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144, /* CLK_TOP_SPMI_M_MST */
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145, /* CLK_TOP_DVFSRC */
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146, /* CLK_TOP_TL */
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147, /* CLK_TOP_AES_MSDCFDE */
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148, /* CLK_TOP_DSI_OCC */
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149, /* CLK_TOP_WPE_VPP */
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150, /* CLK_TOP_HDCP */
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151, /* CLK_TOP_HDCP_24M */
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152, /* CLK_TOP_HDMI_APB */
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153, /* CLK_TOP_SNPS_ETH_250M */
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154, /* CLK_TOP_SNPS_ETH_62P4M_PTP */
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155, /* CLK_TOP_SNPS_ETH_50M_RMII */
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156, /* CLK_TOP_ADSP */
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157, /* CLK_TOP_AUDIO_LOCAL_BUS */
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158, /* CLK_TOP_ASM_H */
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159, /* CLK_TOP_ASM_L */
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160, /* CLK_TOP_APLL1 */
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161, /* CLK_TOP_APLL2 */
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162, /* CLK_TOP_APLL3 */
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163, /* CLK_TOP_APLL4 */
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164, /* CLK_TOP_APLL5 */
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165, /* CLK_TOP_I2SO1 */
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166, /* CLK_TOP_I2SO2 */
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167, /* CLK_TOP_I2SI1 */
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168, /* CLK_TOP_I2SI2 */
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169, /* CLK_TOP_DPTX */
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170, /* CLK_TOP_AUD_IEC */
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171, /* CLK_TOP_A1SYS_HP */
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172, /* CLK_TOP_A2SYS */
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173, /* CLK_TOP_A3SYS */
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174, /* CLK_TOP_A4SYS */
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175, /* CLK_TOP_ECC */
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176, /* CLK_TOP_SPINOR */
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177, /* CLK_TOP_ULPOSC */
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178, /* CLK_TOP_SRCK */
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-1, /* CLK_TOP_MFG_CK_FAST_REF */
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8, /* CLK_TOP_MAINPLL_D3 */
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9, /* CLK_TOP_MAINPLL_D4 */
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10, /* CLK_TOP_MAINPLL_D4_D2 */
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11, /* CLK_TOP_MAINPLL_D4_D4 */
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12, /* CLK_TOP_MAINPLL_D4_D8 */
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13, /* CLK_TOP_MAINPLL_D5 */
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14, /* CLK_TOP_MAINPLL_D5_D2 */
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15, /* CLK_TOP_MAINPLL_D5_D4 */
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16, /* CLK_TOP_MAINPLL_D5_D8 */
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17, /* CLK_TOP_MAINPLL_D6 */
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18, /* CLK_TOP_MAINPLL_D6_D2 */
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19, /* CLK_TOP_MAINPLL_D6_D4 */
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20, /* CLK_TOP_MAINPLL_D6_D8 */
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21, /* CLK_TOP_MAINPLL_D7 */
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22, /* CLK_TOP_MAINPLL_D7_D2 */
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23, /* CLK_TOP_MAINPLL_D7_D4 */
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24, /* CLK_TOP_MAINPLL_D7_D8 */
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25, /* CLK_TOP_MAINPLL_D9 */
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26, /* CLK_TOP_UNIVPLL_D2 */
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27, /* CLK_TOP_UNIVPLL_D3 */
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28, /* CLK_TOP_UNIVPLL_D4 */
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29, /* CLK_TOP_UNIVPLL_D4_D2 */
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30, /* CLK_TOP_UNIVPLL_D4_D4 */
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31, /* CLK_TOP_UNIVPLL_D4_D8 */
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32, /* CLK_TOP_UNIVPLL_D5 */
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33, /* CLK_TOP_UNIVPLL_D5_D2 */
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34, /* CLK_TOP_UNIVPLL_D5_D4 */
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35, /* CLK_TOP_UNIVPLL_D5_D8 */
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36, /* CLK_TOP_UNIVPLL_D6 */
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37, /* CLK_TOP_UNIVPLL_D6_D2 */
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38, /* CLK_TOP_UNIVPLL_D6_D4 */
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39, /* CLK_TOP_UNIVPLL_D6_D8 */
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40, /* CLK_TOP_UNIVPLL_D7 */
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41, /* CLK_TOP_UNIVPLL_192M */
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42, /* CLK_TOP_UNIVPLL_192M_D4 */
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43, /* CLK_TOP_UNIVPLL_192M_D8 */
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44, /* CLK_TOP_UNIVPLL_192M_D10 */
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45, /* CLK_TOP_UNIVPLL_192M_D16 */
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46, /* CLK_TOP_UNIVPLL_192M_D32 */
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47, /* CLK_TOP_APLL1_D3 */
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48, /* CLK_TOP_APLL1_D4 */
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49, /* CLK_TOP_APLL2_D3 */
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50, /* CLK_TOP_APLL2_D4 */
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51, /* CLK_TOP_APLL3_D4 */
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52, /* CLK_TOP_APLL4_D4 */
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53, /* CLK_TOP_APLL5_D4 */
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54, /* CLK_TOP_MMPLL_D4 */
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55, /* CLK_TOP_MMPLL_D4_D2 */
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56, /* CLK_TOP_MMPLL_D5 */
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57, /* CLK_TOP_MMPLL_D5_D2 */
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58, /* CLK_TOP_MMPLL_D5_D4 */
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59, /* CLK_TOP_MMPLL_D6 */
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60, /* CLK_TOP_MMPLL_D6_D2 */
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61, /* CLK_TOP_MMPLL_D7 */
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9, /* CLK_TOP_MAINPLL_D3 */
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10, /* CLK_TOP_MAINPLL_D4 */
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11, /* CLK_TOP_MAINPLL_D4_D2 */
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12, /* CLK_TOP_MAINPLL_D4_D4 */
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13, /* CLK_TOP_MAINPLL_D4_D8 */
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14, /* CLK_TOP_MAINPLL_D5 */
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15, /* CLK_TOP_MAINPLL_D5_D2 */
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16, /* CLK_TOP_MAINPLL_D5_D4 */
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17, /* CLK_TOP_MAINPLL_D5_D8 */
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18, /* CLK_TOP_MAINPLL_D6 */
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19, /* CLK_TOP_MAINPLL_D6_D2 */
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20, /* CLK_TOP_MAINPLL_D6_D4 */
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21, /* CLK_TOP_MAINPLL_D6_D8 */
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22, /* CLK_TOP_MAINPLL_D7 */
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23, /* CLK_TOP_MAINPLL_D7_D2 */
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24, /* CLK_TOP_MAINPLL_D7_D4 */
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25, /* CLK_TOP_MAINPLL_D7_D8 */
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26, /* CLK_TOP_MAINPLL_D9 */
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27, /* CLK_TOP_UNIVPLL_D2 */
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28, /* CLK_TOP_UNIVPLL_D3 */
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29, /* CLK_TOP_UNIVPLL_D4 */
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30, /* CLK_TOP_UNIVPLL_D4_D2 */
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31, /* CLK_TOP_UNIVPLL_D4_D4 */
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32, /* CLK_TOP_UNIVPLL_D4_D8 */
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33, /* CLK_TOP_UNIVPLL_D5 */
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34, /* CLK_TOP_UNIVPLL_D5_D2 */
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35, /* CLK_TOP_UNIVPLL_D5_D4 */
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36, /* CLK_TOP_UNIVPLL_D5_D8 */
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37, /* CLK_TOP_UNIVPLL_D6 */
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38, /* CLK_TOP_UNIVPLL_D6_D2 */
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39, /* CLK_TOP_UNIVPLL_D6_D4 */
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40, /* CLK_TOP_UNIVPLL_D6_D8 */
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41, /* CLK_TOP_UNIVPLL_D7 */
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42, /* CLK_TOP_UNIVPLL_192M */
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43, /* CLK_TOP_UNIVPLL_192M_D4 */
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44, /* CLK_TOP_UNIVPLL_192M_D8 */
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45, /* CLK_TOP_UNIVPLL_192M_D10 */
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46, /* CLK_TOP_UNIVPLL_192M_D16 */
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47, /* CLK_TOP_UNIVPLL_192M_D32 */
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48, /* CLK_TOP_APLL1_D3 */
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49, /* CLK_TOP_APLL1_D4 */
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50, /* CLK_TOP_APLL2_D3 */
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51, /* CLK_TOP_APLL2_D4 */
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52, /* CLK_TOP_APLL3_D4 */
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53, /* CLK_TOP_APLL4_D4 */
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54, /* CLK_TOP_APLL5_D4 */
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55, /* CLK_TOP_MMPLL_D4 */
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56, /* CLK_TOP_MMPLL_D4_D2 */
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57, /* CLK_TOP_MMPLL_D5 */
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58, /* CLK_TOP_MMPLL_D5_D2 */
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59, /* CLK_TOP_MMPLL_D5_D4 */
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60, /* CLK_TOP_MMPLL_D6 */
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61, /* CLK_TOP_MMPLL_D6_D2 */
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62, /* CLK_TOP_MMPLL_D7 */
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62, /* CLK_TOP_MMPLL_D9 */
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-1, /* CLK_TOP_TVDPLL1 */
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63, /* CLK_TOP_TVDPLL1_D2 */
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64, /* CLK_TOP_TVDPLL1_D4 */
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65, /* CLK_TOP_TVDPLL1_D8 */
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66, /* CLK_TOP_TVDPLL1_D16 */
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64, /* CLK_TOP_TVDPLL1_D2 */
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65, /* CLK_TOP_TVDPLL1_D4 */
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66, /* CLK_TOP_TVDPLL1_D8 */
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67, /* CLK_TOP_TVDPLL1_D16 */
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-1, /* CLK_TOP_TVDPLL2 */
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67, /* CLK_TOP_TVDPLL2_D2 */
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68, /* CLK_TOP_TVDPLL2_D4 */
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69, /* CLK_TOP_TVDPLL2_D8 */
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70, /* CLK_TOP_TVDPLL2_D16 */
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72, /* CLK_TOP_MSDCPLL_D2 */
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73, /* CLK_TOP_MSDCPLL_D16 */
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68, /* CLK_TOP_TVDPLL2_D2 */
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69, /* CLK_TOP_TVDPLL2_D4 */
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70, /* CLK_TOP_TVDPLL2_D8 */
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71, /* CLK_TOP_TVDPLL2_D16 */
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73, /* CLK_TOP_MSDCPLL_D2 */
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74, /* CLK_TOP_MSDCPLL_D16 */
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-1, /* CLK_TOP_ETHPLL */
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74, /* CLK_TOP_ETHPLL_D2 */
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75, /* CLK_TOP_ETHPLL_D4 */
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76, /* CLK_TOP_ETHPLL_D8 */
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77, /* CLK_TOP_ETHPLL_D10 */
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78, /* CLK_TOP_ADSPPLL_D2 */
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79, /* CLK_TOP_ADSPPLL_D4 */
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80, /* CLK_TOP_ADSPPLL_D8 */
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75, /* CLK_TOP_ETHPLL_D2 */
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76, /* CLK_TOP_ETHPLL_D4 */
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77, /* CLK_TOP_ETHPLL_D8 */
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78, /* CLK_TOP_ETHPLL_D10 */
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79, /* CLK_TOP_ADSPPLL_D2 */
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80, /* CLK_TOP_ADSPPLL_D4 */
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81, /* CLK_TOP_ADSPPLL_D8 */
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0, /* CLK_TOP_ULPOSC1 */
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81, /* CLK_TOP_ULPOSC1_D2 */
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82, /* CLK_TOP_ULPOSC1_D4 */
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83, /* CLK_TOP_ULPOSC1_D8 */
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84, /* CLK_TOP_ULPOSC1_D7 */
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85, /* CLK_TOP_ULPOSC1_D10 */
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||||
86, /* CLK_TOP_ULPOSC1_D16 */
|
||||
82, /* CLK_TOP_ULPOSC1_D2 */
|
||||
83, /* CLK_TOP_ULPOSC1_D4 */
|
||||
84, /* CLK_TOP_ULPOSC1_D8 */
|
||||
85, /* CLK_TOP_ULPOSC1_D7 */
|
||||
86, /* CLK_TOP_ULPOSC1_D10 */
|
||||
87, /* CLK_TOP_ULPOSC1_D16 */
|
||||
1, /* CLK_TOP_MPHONE_SLAVE_BCK */
|
||||
2, /* CLK_TOP_PAD_FPC */
|
||||
3, /* CLK_TOP_466M_FMEM */
|
||||
@@ -1328,33 +1329,33 @@ static const int mt8188_id_offs_map[] = {
|
||||
-1, /* CLK_TOP_APLL12_CK_DIV3 */
|
||||
-1, /* CLK_TOP_APLL12_CK_DIV4 */
|
||||
-1, /* CLK_TOP_APLL12_CK_DIV9 */
|
||||
187, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
|
||||
188, /* CLK_TOP_CFGREG_CLOCK_EN_VPP1 */
|
||||
189, /* CLK_TOP_CFGREG_CLOCK_EN_VDO0 */
|
||||
190, /* CLK_TOP_CFGREG_CLOCK_EN_VDO1 */
|
||||
191, /* CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS */
|
||||
192, /* CLK_TOP_CFGREG_F26M_VPP0 */
|
||||
193, /* CLK_TOP_CFGREG_F26M_VPP1 */
|
||||
194, /* CLK_TOP_CFGREG_F26M_VDO0 */
|
||||
195, /* CLK_TOP_CFGREG_F26M_VDO1 */
|
||||
196, /* CLK_TOP_CFGREG_AUD_F26M_AUD */
|
||||
197, /* CLK_TOP_CFGREG_UNIPLL_SES */
|
||||
198, /* CLK_TOP_CFGREG_F_PCIE_PHY_REF */
|
||||
199, /* CLK_TOP_SSUSB_TOP_REF */
|
||||
200, /* CLK_TOP_SSUSB_PHY_REF */
|
||||
201, /* CLK_TOP_SSUSB_TOP_P1_REF */
|
||||
202, /* CLK_TOP_SSUSB_PHY_P1_REF */
|
||||
203, /* CLK_TOP_SSUSB_TOP_P2_REF */
|
||||
204, /* CLK_TOP_SSUSB_PHY_P2_REF */
|
||||
205, /* CLK_TOP_SSUSB_TOP_P3_REF */
|
||||
223, /* CLK_TOP_SSUSB_PHY_P3_REF */
|
||||
188, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
|
||||
189, /* CLK_TOP_CFGREG_CLOCK_EN_VPP1 */
|
||||
190, /* CLK_TOP_CFGREG_CLOCK_EN_VDO0 */
|
||||
191, /* CLK_TOP_CFGREG_CLOCK_EN_VDO1 */
|
||||
192, /* CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS */
|
||||
193, /* CLK_TOP_CFGREG_F26M_VPP0 */
|
||||
194, /* CLK_TOP_CFGREG_F26M_VPP1 */
|
||||
195, /* CLK_TOP_CFGREG_F26M_VDO0 */
|
||||
196, /* CLK_TOP_CFGREG_F26M_VDO1 */
|
||||
197, /* CLK_TOP_CFGREG_AUD_F26M_AUD */
|
||||
198, /* CLK_TOP_CFGREG_UNIPLL_SES */
|
||||
199, /* CLK_TOP_CFGREG_F_PCIE_PHY_REF */
|
||||
200, /* CLK_TOP_SSUSB_TOP_REF */
|
||||
201, /* CLK_TOP_SSUSB_PHY_REF */
|
||||
202, /* CLK_TOP_SSUSB_TOP_P1_REF */
|
||||
203, /* CLK_TOP_SSUSB_PHY_P1_REF */
|
||||
204, /* CLK_TOP_SSUSB_TOP_P2_REF */
|
||||
205, /* CLK_TOP_SSUSB_PHY_P2_REF */
|
||||
206, /* CLK_TOP_SSUSB_TOP_P3_REF */
|
||||
207, /* CLK_TOP_SSUSB_PHY_P3_REF */
|
||||
-1, /* CLK_TOP_NR_CLK */
|
||||
-1, /* CLK_TOP_ADSPPLL */
|
||||
-1, /* CLK_TOP_CLK13M */
|
||||
6, /* CLK_TOP_CLK26M */
|
||||
7, /* CLK_TOP_CLK32K */
|
||||
6, /* CLK_TOP_CLK13M */
|
||||
7, /* CLK_TOP_CLK26M */
|
||||
8, /* CLK_TOP_CLK32K */
|
||||
-1, /* CLK_TOP_IMGPLL */
|
||||
71, /* CLK_TOP_MSDCPLL */
|
||||
72, /* CLK_TOP_MSDCPLL */
|
||||
-1, /* CLK_TOP_ULPOSC1_CK1 */
|
||||
-1, /* CLK_TOP_ULPOSC_CK1 */
|
||||
};
|
||||
@@ -1417,9 +1418,9 @@ static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
.id_offs_map = mt8188_id_offs_map,
|
||||
.id_offs_map_size = ARRAY_SIZE(mt8188_id_offs_map),
|
||||
.fdivs_offs = 8, /* CLK_TOP_MAINPLL_D3 */
|
||||
.muxes_offs = 87, /* CLK_TOP_AXI */
|
||||
.gates_offs = 187, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
|
||||
.fdivs_offs = 9, /* CLK_TOP_MAINPLL_D3 */
|
||||
.muxes_offs = 88, /* CLK_TOP_AXI */
|
||||
.gates_offs = 188, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
|
||||
.fclks = top_fixed_clks,
|
||||
.fdivs = top_fixed_divs,
|
||||
.muxes = top_muxes,
|
||||
|
||||
Reference in New Issue
Block a user