Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

clk: mediatek: mt8188: fix circular clock dependency

Browse Source 
FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 3)
--> CLK_TOP_APLL1_D4 declares CLK_TOP_APLL1 as it's parents

MUX_GATE(CLK_TOP_APLL1, apll1_parents, 0x0F8, 0, 4, 7)
--> CLK_TOP_APLL1 declares apll1_parents as it's parents

static const int apll1_parents[] = {
	CLK_TOP_CLK26M,
	CLK_TOP_APLL1_D4
};
--> CLK_TOP_APLL1_D4 is a parent of CLK_TOP_APLL1

Fix this, by correctly setting CLK_TOP_APLL1_DX parent to CLK_APMIXED_APLLX

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
This commit is contained in:
Julien Stephan
2026-02-02 13:41:50 +01:00
committed by Tom Rini
parent a04835c0e9
commit 6354f83f43
1 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/clk/mediatek/clk-mt8188.c
View File

@@ -148,13 +148,13 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
FACTOR1(CLK_TOP_UNIVPLL_192M_D10, CLK_TOP_UNIVPLL_192M, 1, 10),
FACTOR1(CLK_TOP_UNIVPLL_192M_D16, CLK_TOP_UNIVPLL_192M, 1, 16),
FACTOR1(CLK_TOP_UNIVPLL_192M_D32, CLK_TOP_UNIVPLL_192M, 1, 32),
FACTOR1(CLK_TOP_APLL1_D3, CLK_TOP_APLL1, 1, 3),
FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
FACTOR1(CLK_TOP_APLL3_D4, CLK_TOP_APLL3, 1, 4),
FACTOR1(CLK_TOP_APLL4_D4, CLK_TOP_APLL4, 1, 4),
FACTOR1(CLK_TOP_APLL5_D4, CLK_TOP_APLL5, 1, 4),
FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
FACTOR0(CLK_TOP_APLL3_D4, CLK_APMIXED_APLL3, 1, 4),
FACTOR0(CLK_TOP_APLL4_D4, CLK_APMIXED_APLL4, 1, 4),
FACTOR0(CLK_TOP_APLL5_D4, CLK_APMIXED_APLL5, 1, 4),
FACTOR0(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4),
FACTOR1(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1, 2),
FACTOR0(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5),