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rpi5: Use devicetree as alternative way to read IO base addresses

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MBOX and Watchdog on RPi5/bcm2712 have a different base IO offsets.
Find them via devicetree blob passed by bootloader.

Signed-off-by: Dmitry Malkin <dmitry@bedrocksystems.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
This commit is contained in:
Dmitry Malkin
2024-01-23 10:07:54 +02:00
committed by Matthias Brugger
parent a5a27eafc4
commit 60878e753c
6 changed files with 43 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-bcm283x/include/mach/base.h
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@@ -6,7 +6,10 @@
#ifndef _BCM283x_BASE_H_
#define _BCM283x_BASE_H_
extern unsigned long rpi_bcm283x_base;
extern unsigned long rpi_mbox_base;
extern unsigned long rpi_timer_base;
extern unsigned long rpi_sdhci_base;
extern unsigned long rpi_wdog_base;
#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B

3
arch/arm/mach-bcm283x/include/mach/mbox.h
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@@ -38,8 +38,7 @@
/* Raw mailbox HW */
#define BCM2835_MBOX_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
rpi_bcm283x_base + 0x0000b880; })
#define BCM2835_MBOX_PHYSADDR rpi_mbox_base
struct bcm2835_mbox_regs {
u32 read;

3
arch/arm/mach-bcm283x/include/mach/sdhci.h
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@@ -8,8 +8,7 @@
#include <asm/arch/base.h>
#define BCM2835_SDHCI_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
rpi_bcm283x_base + 0x00300000; })
#define BCM2835_SDHCI_PHYSADDR rpi_sdhci_base
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);

3
arch/arm/mach-bcm283x/include/mach/timer.h
View File

@@ -11,8 +11,7 @@
#include <linux/bug.h>
#endif
#define BCM2835_TIMER_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
rpi_bcm283x_base + 0x00003000; })
#define BCM2835_TIMER_PHYSADDR rpi_timer_base
#define BCM2835_TIMER_CS_M3 (1 << 3)
#define BCM2835_TIMER_CS_M2 (1 << 2)

3
arch/arm/mach-bcm283x/include/mach/wdog.h
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@@ -8,8 +8,7 @@
#include <asm/arch/base.h>
#define BCM2835_WDOG_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
rpi_bcm283x_base + 0x00100000; })
#define BCM2835_WDOG_PHYSADDR rpi_wdog_base
struct bcm2835_wdog_regs {
u32 unknown0[7];

43
arch/arm/mach-bcm283x/init.c
View File

@@ -146,7 +146,11 @@ static void rpi_update_mem_map(void)
static void rpi_update_mem_map(void) {}
#endif
unsigned long rpi_bcm283x_base = 0x3f000000;
/* Default bcm283x devices addresses */
unsigned long rpi_mbox_base = 0x3f00b880;
unsigned long rpi_sdhci_base = 0x3f300000;
unsigned long rpi_wdog_base = 0x3f100000;
unsigned long rpi_timer_base = 0x3f003000;
int arch_cpu_init(void)
{
@@ -157,22 +161,45 @@ int arch_cpu_init(void)
int mach_cpu_init(void)
{
int ret, soc_offset;
int ret, soc, offset;
u64 io_base, size;
rpi_update_mem_map();
/* Get IO base from device tree */
soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
if (soc_offset < 0)
return soc_offset;
soc = fdt_path_offset(gd->fdt_blob, "/soc");
if (soc < 0)
return soc;
ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
&io_base, &size);
ret = fdt_read_range((void *)gd->fdt_blob, soc, 0, NULL,
&io_base, &size);
if (ret)
return ret;
rpi_bcm283x_base = io_base;
rpi_mbox_base = io_base + 0x00b880;
rpi_sdhci_base = io_base + 0x300000;
rpi_wdog_base = io_base + 0x100000;
rpi_timer_base = io_base + 0x003000;
offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
"brcm,bcm2835-mbox");
if (offset > soc)
rpi_mbox_base = fdt_get_base_address(gd->fdt_blob, offset);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
"brcm,bcm2835-sdhci");
if (offset > soc)
rpi_sdhci_base = fdt_get_base_address(gd->fdt_blob, offset);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
"brcm,bcm2835-system-timer");
if (offset > soc)
rpi_timer_base = fdt_get_base_address(gd->fdt_blob, offset);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, soc,
"brcm,bcm2712-pm");
if (offset > soc)
rpi_wdog_base = fdt_get_base_address(gd->fdt_blob, offset);
return 0;
}