driver: cache: Remove SiFive PL2 driver

Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

arch/riscv/lib/sifive_cache.c

@@ -41,8 +41,5 @@ static inline void probe_cache_device(struct driver *driver, struct udevice *dev
 
 void enable_caches(void)
 {
-	struct udevice *dev = NULL;
-
-	probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
 }
 #endif /* !CONFIG_XPL_BUILD */

drivers/cache/Kconfig

@@ -46,11 +46,5 @@ config SIFIVE_CCACHE
 	  This driver is for SiFive Composable L2/L3 cache. It enables cache
 	  ways of composable cache.
 
-config SIFIVE_PL2
-	bool "SiFive private L2 cache"
-	select CACHE
-	help
-	  This driver is for SiFive Private L2 cache. It configures registers
-	  to enable the clock gating feature.
 
 endmenu

drivers/cache/Makefile

@@ -5,4 +5,3 @@ obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_ANDES_L2_CACHE) += cache-andes-l2.o
 obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
-obj-$(CONFIG_SIFIVE_PL2) += cache-sifive-pl2.o