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docs: board: ti: j784s4_evm: Add PCIe boot documentation
Add PCIe boot documentation for J784S4-EVM including boot mode switch settings, hardware setup requirements, endpoint configuration details and step-by-step boot procedure. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> [s-vadapalli@ti.com: simplified and documented the pcie_boot_util program] Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
This commit is contained in:
Hrushikesh Salunke
committed by
Tom Rini
Tom Rini
parent
078200f1ee
commit
6230a595a7
@@ -299,6 +299,10 @@ http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section.
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- 00000000
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- 01110000
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* - PCIe
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- 10001000
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- 01010000
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For SW7 and SW11, the switch state in the "ON" position = 1.
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Boot Mode Pins for AM69-SK
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@@ -330,6 +334,307 @@ section.
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For SW2, the switch state in the "ON" position = 1.
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PCIe Boot
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---------
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The J784S4 SoC supports booting over PCIe, allowing the device to function
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as a PCIe endpoint and receive boot loader images from a PCIe Root Complex.
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The PCIe1 instance of PCIe is configured by Boot ROM for Endpoint Mode of
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operation. Hence, the PCIe Connector on the EVM corresponding to PCIe1
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should be utilized for PCIe Boot.
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Hardware Setup
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^^^^^^^^^^^^^^
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To boot the J784S4 EVM via PCIe, the following hardware setup is required:
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1. Configure the boot mode switches on J784S4-EVM for PCIe boot:
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.. code-block:: text
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SW7: 01010000
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SW11: 10001000
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2. Connect the J784S4-EVM (endpoint) to a PCIe Root Complex (e.g., x86 host)
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using a PCIe cable. Both boards should be powered off before making the
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connection.
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Endpoint Configuration
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^^^^^^^^^^^^^^^^^^^^^^
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The following configuration options are enabled by default in
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``j784s4_evm_r5_defconfig`` and ``j784s4_evm_a72_defconfig``:
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- ``CONFIG_SPL_PCI_DFU_BAR_SIZE``: Size of the PCIe BAR for DFU/boot image download
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- ``CONFIG_SPL_PCI_DFU_VENDOR_ID``: PCIe vendor ID advertised by the endpoint
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- ``CONFIG_SPL_PCI_DFU_DEVICE_ID``: PCIe device ID advertised by the endpoint
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- ``CONFIG_SPL_PCI_DFU_MAGIC_WORD``: Magic word written by Root Complex to signal image transfer completion
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- ``CONFIG_SPL_PCI_DFU_BOOT_PHASE``: Current boot phase indicator for Root Complex
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By default, PCIe Root Complex mode is enabled in the device tree. For PCIe Boot,
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build the Bootloaders with the following content added to k3-j784s4-evm-u-boot.dtsi:
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.. code-block:: devicetree
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&serdes0 {
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/delete-property/ serdes0_usb_link;
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};
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&serdes_refclk {
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bootph-all;
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};
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&serdes0_pcie1_link {
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bootph-all;
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};
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&serdes_ln_ctrl {
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bootph-all;
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};
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&pcie1_ctrl {
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bootph-all;
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};
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&pcie1_rc {
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status = "disabled";
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};
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&cbass_main {
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pcie1_ep: pcie-ep@2910000 {
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compatible = "ti,j784s4-pcie-ep";
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reg = <0x00 0x02910000 0x00 0x1000>,
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<0x00 0x02917000 0x00 0x400>,
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<0x00 0x0d800000 0x00 0x00800000>,
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<0x00 0x18000000 0x00 0x08000000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "mem";
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
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ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
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max-link-speed = <3>;
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num-lanes = <2>;
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power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 333 0>;
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clock-names = "fck";
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max-functions = /bits/ 8 <6>;
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max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
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dma-coherent;
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phys = <&serdes0_pcie1_link>;
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phy-names = "pcie-phy";
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bootph-all;
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};
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};
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PCIe Boot Procedure
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^^^^^^^^^^^^^^^^^^^
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The following steps describe the process of booting J784S4-EVM over PCIe:
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1. Compile the sample host program (provided after this section):
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.. prompt:: bash
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gcc -o pcie_boot_util pcie_boot_util.c
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2. Power on the J784S4-EVM (endpoint) after configuring boot mode switches
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for PCIe Boot.
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3. Copy the compiled sample host program (pcie_boot_util) and the bootloader
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images to the Root Complex. Check PCIe enumeration on Root Complex to ensure
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that the J784S4 EVM shows up as the PCIe Endpoint:
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.. prompt:: bash
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lspci
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The endpoint will appear as a RAM device or with multiple functions:
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.. code-block:: text
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0000:00:00.0 PCI bridge: Texas Instruments Device b012
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0000:01:00.0 RAM memory: Texas Instruments Device b012
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0000:01:00.1 Non-VGA unclassified device: Texas Instruments Device 0100
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0000:01:00.2 Non-VGA unclassified device: Texas Instruments Device 0100
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4. Copy ``tiboot3.bin`` to the endpoint. Use ``lspci -vv`` to identify the BAR
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address:
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.. prompt:: bash
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sudo ./pcie_boot_util 0x4007100000 tiboot3.bin
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The sample program automatically writes the image start address to
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``0x41CF3FE0`` and the magic word ``0xB17CEAD9`` to ``0x41CF3FE4``.
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5. After ``tiboot3.bin`` is processed, the PCIe link will go down briefly.
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Remove the PCIe device and rescan the bus:
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.. prompt:: bash
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echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove
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echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan
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lspci
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The enumeration will change to something similar:
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.. code-block:: text
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0000:00:00.0 PCI bridge: Texas Instruments Device b012
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0000:01:00.0 RAM memory: Texas Instruments Device b010 (rev dc)
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.. note::
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When the Root-Complex enumerates the PCIe Endpoint after a 'remove-rescan' sequence,
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it is possible that the 'BAR' appears 'disabled'. If so, writing to the BAR via the
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'pcie_boot_util' to transfer the bootloader image will have no effect. In such cases,
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run 'setpci -s 0000:01:00.0 COMMAND=0x02' on the Root-Complex after enumeration
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(with appropriate DOMAIN:BUS:DEVICE.FUNCTION corresponding to the Endpoint) to enable
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the BAR.
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6. Copy ``tispl.bin`` to the new BAR address (use ``lspci -vv`` to find):
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.. prompt:: bash
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sudo ./pcie_boot_util 0x4000400000 tispl.bin
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7. After ``tispl.bin`` is processed, the PCIe link will go down again. Remove
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and rescan the PCIe device:
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.. prompt:: bash
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echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove
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echo 1 > /sys/bus/pci/devices/0000\:00\:00.0/rescan
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8. Copy ``u-boot.img``:
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.. prompt:: bash
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sudo ./pcie_boot_util 0x4000400000 u-boot.img
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9. After ``u-boot.img`` is successfully loaded, the boot process is complete
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and endpoint should boot till U-Boot prompt.
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.. note::
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During the boot process, "PCIe LINK DOWN" messages might appear in kernel
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logs. This is expected as the endpoint resets and re-initializes the PCIe
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link after processing each boot stage.
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Sample Host Program
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^^^^^^^^^^^^^^^^^^^
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The following C program can be used on the Root Complex to copy bootloader images
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to the J784S4 endpoint:
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.. code-block:: c
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#include <stdio.h>
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#include <stdlib.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#include <string.h>
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#define MAP_SIZE 0x400000
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/*
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* bootloader_file: Path to the bootloader image (tiboot3.bin, tispl.bin and u-boot.img)
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* bootloader_mem: Memory allocated in RAM for reading the bootloader image file
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* bar_address: Address of BAR to which bootloader image will be written
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* bar_map_base: Mapping of the BAR Base Address for the program
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* load_address: Address in BAR region where bootloader is being transferred
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* transfer_completion_offset: Offset in BAR region to write to notify completion of transfer
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* fd_mem: File descriptor for opening /dev/mem
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* fptr: File pointer for bootloader image in filesystem
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* magic_word: Magic word to notify completion of tiboot3.bin transfer to Boot ROM
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* use_magic_word: Flag to indicate if Magic Word has to be written
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* file_size: Size of bootloader image
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* i: Iterator used during bootloader image transfer
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*/
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int main(int argc, char *argv[])
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{
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off_t bar_address, load_address, transfer_completion_offset;
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unsigned char *bootloader_mem;
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const char *bootloader_file;
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int fd_mem, i, use_magic_word;
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unsigned int magic_word;
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void *bar_map_base;
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long file_size;
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FILE * fptr;
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if (argc != 3) {
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printf("Usage: %s <bar_address> <bootloader_file>\n", argv[0]);
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return 0;
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}
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bar_address = strtoul(argv[1], NULL, 16);
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bootloader_file = argv[2];
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printf("Bootloader File: %s\n", bootloader_file);
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printf("BAR Address: 0x%lx\n", bar_address);
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if(!strcmp(bootloader_file,"tiboot3.bin")) {
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transfer_completion_offset = 0xF3FE0;
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load_address = 0x41C00000;
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magic_word = 0xB17CEAD9;
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use_magic_word = 1;
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} else {
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transfer_completion_offset = MAP_SIZE - 0x4;
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load_address = 0xDEADBEEF;
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use_magic_word = 0;
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}
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fd_mem = open("/dev/mem", O_RDWR | O_SYNC);
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if(fd_mem == -1) {
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printf("failed to open /dev/mem\n");
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return -1;
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}
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bar_map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, bar_address);
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if(bar_map_base == (void *)-1) {
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printf("failed to map BAR\n");
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return -1;
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}
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fptr = fopen(bootloader_file, "rb");
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if (!fptr) {
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printf("failed to read bootloader file\n");
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return -1;
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}
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fseek(fptr, 0, SEEK_END);
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file_size = ftell(fptr);
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rewind(fptr);
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bootloader_mem = (unsigned char *)malloc(sizeof(char) * file_size);
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if(!bootloader_mem) {
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printf("failed to allocate local memory for bootloader file\n");
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return -1;
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}
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if (fread(bootloader_mem, 1, file_size, fptr) != file_size) {
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printf("failed to read bootloader file into local memory\n");
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return -1;
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}
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for(i = 0; i < file_size; i++) {
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*((char *)(bar_map_base) + i) = bootloader_mem[i];
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}
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*(unsigned int *)(bar_map_base + transfer_completion_offset) = (unsigned int)(load_address);
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if(use_magic_word) {
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*(unsigned int *)(bar_map_base + transfer_completion_offset + 4) = magic_word;
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printf("Magic word written for Boot ROM\n");
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}
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printf("Transferred %s to Endpoint\n", bootloader_file);
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return 0;
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}
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This program copies the boot image to the PCIe endpoint's memory region and
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writes the necessary control words to signal image transfer completion.
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Debugging U-Boot
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----------------
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