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board: nxp: common: fix PFUZE100 DM build and unify DM/non-DM handling

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Switch PFUZE100 object linkage to be phase-aware and fix build issues
when using driver model PMIC support.

The PFUZE100 helper code is reworked to:
- Build pfuze.o only when CONFIG_(SPL_)DM_PMIC_PFUZE100 is enabled
- Use CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) for proper DM/non-DM selection
- Align function signatures and implementations with DM PMIC APIs
- Use udevice-based pmic access for DM and legacy pmic for non-DM
- Avoid mixing struct pmic and struct udevice in the same build
  configuration

No functional change intended beyond fixing DM support and build
consistency.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2026-04-21 21:41:21 +08:00
committed by Fabio Estevam
parent b29ce12fc2
commit 64e9956764
3 changed files with 82 additions and 82 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/nxp/common/Makefile
View File

@@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
endif
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
ifneq (,$(filter $(SOC), imx8m imx8ulp imx9))
obj-y += mmc.o

160
board/nxp/common/pfuze.c
View File

@@ -7,7 +7,86 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#ifndef CONFIG_DM_PMIC_PFUZE100
#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct udevice *pfuze_common_init(void)
{
struct udevice *dev;
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Set SW1AB stanby volage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
return dev;
}
#else
int pfuze_mode_init(struct pmic *p, u32 mode)
{
unsigned char offset, i, switch_num;
@@ -90,83 +169,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
return p;
}
#elif defined(CONFIG_DM_PMIC)
int pfuze_mode_init(struct udevice *dev, u32 mode)
{
unsigned char offset, i, switch_num;
u32 id;
int ret;
id = pmic_reg_read(dev, PFUZE100_DEVICEID);
id = id & 0xf;
if (id == 0) {
switch_num = 6;
offset = PFUZE100_SW1CMODE;
} else if (id == 1) {
switch_num = 4;
offset = PFUZE100_SW2MODE;
} else {
printf("Not supported, id=%d\n", id);
return -EINVAL;
}
ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
if (ret < 0) {
printf("Set SW1AB mode error!\n");
return ret;
}
for (i = 0; i < switch_num - 1; i++) {
ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
if (ret < 0) {
printf("Set switch 0x%x mode error!\n",
offset + i * SWITCH_SIZE);
return ret;
}
}
return ret;
}
struct udevice *pfuze_common_init(void)
{
struct udevice *dev;
int ret;
unsigned int reg, dev_id, rev_id;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return NULL;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Set SW1AB stanby volage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
return dev;
}
#endif

2
board/nxp/common/pfuze.h
View File

@@ -6,7 +6,7 @@
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
#ifdef CONFIG_DM_PMIC_PFUZE100
#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
struct udevice *pfuze_common_init(void);
int pfuze_mode_init(struct udevice *dev, u32 mode);
#else