Merge tag 'u-boot-amlogic-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

- set reversed bit when using internal phy on GXL SoCs
- support gpio toggle command for amlogic gpio
- fix saradc
- remove unreachable in meson clk driver
- Stop premature exit from for loop in meson pwm driver
- fix JetHub D1 eth mac fallback generation
This commit is contained in:
Tom Rini
2025-09-30 16:01:05 -06:00
6 changed files with 36 additions and 22 deletions

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@@ -19,21 +19,17 @@ int misc_init_r(void)
{
u8 mac_addr[ARP_HLEN + 1];
char serial[SM_SERIAL_SIZE];
u32 sid;
u16 sid;
if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
/* Ensure the NIC specific bytes of the mac are not all 0 */
if ((sid & 0xffff) == 0)
sid |= 0x800000;
/* OUI registered MAC address */
mac_addr[0] = 0x10;
mac_addr[1] = 0x27;
mac_addr[2] = 0xBE;
mac_addr[3] = (sid >> 16) & 0xff;
mac_addr[4] = (sid >> 8) & 0xff;
mac_addr[5] = (sid >> 0) & 0xff;
sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE) & 0xFFFF;
/* OUI registered fallback MAC address */
mac_addr[0] = 0xF0;
mac_addr[1] = 0x57;
mac_addr[2] = 0x8D;
mac_addr[3] = 0x00;
mac_addr[4] = (sid >> 8) & 0xFF;
mac_addr[5] = sid & 0xFF;
mac_addr[ARP_HLEN] = '\0';
eth_env_set_enetaddr("ethaddr", mac_addr);

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@@ -205,9 +205,9 @@ static int meson_saradc_lock(struct meson_saradc_priv *priv)
do {
udelay(1);
regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && --timeout);
if (timeout < 0) {
if (!timeout) {
printf("Timeout while waiting for BL30 unlock\n");
return -ETIMEDOUT;
}
@@ -256,9 +256,9 @@ static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
do {
udelay(1);
regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && --timeout);
if (timeout < 0)
if (!timeout)
return -ETIMEDOUT;
return 0;

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@@ -916,8 +916,6 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
return -EINVAL;
case CLKID_PCIE_PLL:
return meson_pcie_pll_set_rate(clk, rate);
return 0;
case CLKID_VPU:
return meson_clk_set_rate_by_id(clk,
meson_mux_get_parent(clk, CLKID_VPU), rate,

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@@ -19,6 +19,7 @@
#define REG2_LEDACT GENMASK(23, 22)
#define REG2_LEDLINK GENMASK(25, 24)
#define REG2_DIV4SEL BIT(27)
#define REG2_REVERSED BIT(28)
#define REG2_ADCBYPASS BIT(30)
#define REG2_CLKINSEL BIT(31)
#define ETH_REG3 0x4
@@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
* The only constraint is that it must match the one in
* drivers/net/phy/meson-gxl.c to properly match the PHY.
*/
writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
priv->regs + ETH_REG2);
/* Enable the internal phy */

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@@ -117,8 +117,26 @@ int meson_gpio_get(struct udevice *dev, unsigned int offset)
struct meson_pinctrl *priv = dev_get_priv(dev->parent);
unsigned int reg, bit;
int ret;
enum gpio_func_t direction;
enum meson_reg_type reg_type;
ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, &reg,
direction = meson_gpio_get_direction(dev, offset);
switch (direction) {
case GPIOF_INPUT:
reg_type = REG_IN;
break;
case GPIOF_OUTPUT:
reg_type = REG_OUT;
break;
default:
dev_warn(dev, "Failed to get current direction of Pin %u\n", offset);
return -EINVAL;
}
ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, reg_type, &reg,
&bit);
if (ret)
return ret;

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@@ -359,8 +359,9 @@ static int meson_pwm_probe(struct udevice *dev)
/* We have our source clock, do not alter HW clock mux */
continue;
} else
} else if (err) {
return err;
}
/* Get id in list */
for (p = 0 ; p < data->num_parents ; ++p) {