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https://source.denx.de/u-boot/u-boot.git
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Merge tag 'u-boot-amlogic-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- set reversed bit when using internal phy on GXL SoCs - support gpio toggle command for amlogic gpio - fix saradc - remove unreachable in meson clk driver - Stop premature exit from for loop in meson pwm driver - fix JetHub D1 eth mac fallback generation
This commit is contained in:
@@ -19,21 +19,17 @@ int misc_init_r(void)
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{
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u8 mac_addr[ARP_HLEN + 1];
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char serial[SM_SERIAL_SIZE];
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u32 sid;
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u16 sid;
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if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
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sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
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/* Ensure the NIC specific bytes of the mac are not all 0 */
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if ((sid & 0xffff) == 0)
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sid |= 0x800000;
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/* OUI registered MAC address */
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mac_addr[0] = 0x10;
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mac_addr[1] = 0x27;
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mac_addr[2] = 0xBE;
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mac_addr[3] = (sid >> 16) & 0xff;
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mac_addr[4] = (sid >> 8) & 0xff;
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mac_addr[5] = (sid >> 0) & 0xff;
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sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE) & 0xFFFF;
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/* OUI registered fallback MAC address */
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mac_addr[0] = 0xF0;
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mac_addr[1] = 0x57;
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mac_addr[2] = 0x8D;
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mac_addr[3] = 0x00;
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mac_addr[4] = (sid >> 8) & 0xFF;
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mac_addr[5] = sid & 0xFF;
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mac_addr[ARP_HLEN] = '\0';
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eth_env_set_enetaddr("ethaddr", mac_addr);
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@@ -205,9 +205,9 @@ static int meson_saradc_lock(struct meson_saradc_priv *priv)
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do {
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udelay(1);
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regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
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} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
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} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && --timeout);
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if (timeout < 0) {
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if (!timeout) {
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printf("Timeout while waiting for BL30 unlock\n");
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return -ETIMEDOUT;
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}
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@@ -256,9 +256,9 @@ static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
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do {
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udelay(1);
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regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val);
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} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
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} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && --timeout);
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if (timeout < 0)
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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@@ -916,8 +916,6 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
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return -EINVAL;
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case CLKID_PCIE_PLL:
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return meson_pcie_pll_set_rate(clk, rate);
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return 0;
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case CLKID_VPU:
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return meson_clk_set_rate_by_id(clk,
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meson_mux_get_parent(clk, CLKID_VPU), rate,
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@@ -19,6 +19,7 @@
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#define REG2_LEDACT GENMASK(23, 22)
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#define REG2_LEDLINK GENMASK(25, 24)
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#define REG2_DIV4SEL BIT(27)
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#define REG2_REVERSED BIT(28)
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#define REG2_ADCBYPASS BIT(30)
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#define REG2_CLKINSEL BIT(31)
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#define ETH_REG3 0x4
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@@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv)
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* The only constraint is that it must match the one in
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* drivers/net/phy/meson-gxl.c to properly match the PHY.
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*/
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writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
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writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
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priv->regs + ETH_REG2);
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/* Enable the internal phy */
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@@ -117,8 +117,26 @@ int meson_gpio_get(struct udevice *dev, unsigned int offset)
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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enum gpio_func_t direction;
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enum meson_reg_type reg_type;
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, ®,
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direction = meson_gpio_get_direction(dev, offset);
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switch (direction) {
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case GPIOF_INPUT:
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reg_type = REG_IN;
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break;
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case GPIOF_OUTPUT:
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reg_type = REG_OUT;
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break;
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default:
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dev_warn(dev, "Failed to get current direction of Pin %u\n", offset);
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return -EINVAL;
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}
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ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, reg_type, ®,
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&bit);
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if (ret)
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return ret;
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@@ -359,8 +359,9 @@ static int meson_pwm_probe(struct udevice *dev)
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/* We have our source clock, do not alter HW clock mux */
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continue;
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} else
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} else if (err) {
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return err;
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}
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/* Get id in list */
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for (p = 0 ; p < data->num_parents ; ++p) {
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