Merge tag 'u-boot-rockchip-20240525' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/20844 - new board: rk3566 Powkiddy X55, rk3588s Indiedroid Nova; - rv1126 migrate to OF_UPSTREAM; - Fix for px30 ringneck board; - Fix for rk3588 SPLL clock init;
2026-06-13 15:03:58 +03:00 · 2024-05-25 08:01:20 -06:00
parent a7f0154c41 5c7caa9598
commit 6c012d6a2f
37 changed files with 310 additions and 2908 deletions
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -97,9 +97,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \

-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-	rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
 	s5p4418-nanopi2.dtb

--- a/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = &sdmmc0, &sdhci;
+	};
+};
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-	model = "Edgeble Neu2 IO Board";
-	compatible = "edgeble,neural-compute-module-2-io",
-		     "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-	aliases {
-		serial2 = &uart2;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	vcc12v_dcin: vcc12v-dcin-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc12v_dcin";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	v3v3_sys: v3v3-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "v3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-};
-
-&gmac {
-	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
-			  <&cru CLK_GMAC_ETHERNET_OUT>;
-	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-	assigned-clock-rates = <125000000>, <0>, <25000000>;
-	clock_in_out = "input";
-	phy-handle = <&phy>;
-	phy-mode = "rgmii";
-	phy-supply = <&vcc_3v3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
-	tx_delay = <0x2a>;
-	rx_delay = <0x1a>;
-	status = "okay";
-};
-
-&mdio {
-	phy: ethernet-phy@0 {
-		compatible = "ethernet-phy-id001c.c916",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eth_phy_rst>;
-		reset-assert-us = <20000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	ethernet {
-		eth_phy_rst: eth-phy-rst {
-			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-};
-
-&pwm11 {
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
-	compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-	aliases {
-		mmc0 = &emmc;
-	};
-
-	vccio_flash: vccio-flash-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&flash_vol_sel>;
-		regulator-name = "vccio_flash";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc_3v3>;
-	};
-
-	sdio_pwrseq: pwrseq-sdio {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
-	bus-width = <8>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
-	rockchip,default-sample-phase = <90>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vccio_flash>;
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc_buck5>;
-		vcc6-supply = <&vcc_buck5>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-
-		regulators {
-			vdd_npu_vepu: DCDC_REG1 {
-				regulator-name = "vdd_npu_vepu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <650000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_arm: DCDC_REG2 {
-				regulator-name = "vdd_arm";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <725000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc3v3_sys: DCDC_REG4 {
-				regulator-name = "vcc3v3_sys";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcc_buck5: DCDC_REG5 {
-				regulator-name = "vcc_buck5";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <2200000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2200000>;
-				};
-			};
-
-			vcc_0v8: LDO_REG1 {
-				regulator-name = "vcc_0v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_pmu: LDO_REG2 {
-				regulator-name = "vcc1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd0v8_pmu: LDO_REG3 {
-				regulator-name = "vcc0v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <800000>;
-				};
-			};
-
-			vcc_1v8: LDO_REG4 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_dovdd: LDO_REG5 {
-				regulator-name = "vcc_dovdd";
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_dvdd: LDO_REG6 {
-				regulator-name = "vcc_dvdd";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_avdd: LDO_REG7 {
-				regulator-name = "vcc_avdd";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG8 {
-				regulator-name = "vccio_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: LDO_REG9 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_5v0: SWITCH_REG1 {
-				regulator-name = "vcc_5v0";
-			};
-
-			vcc_3v3: SWITCH_REG2 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-			};
-		};
-	};
-};
-
-&pinctrl {
-	bt {
-		bt_enable: bt-enable {
-			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	flash {
-		flash_vol_sel: flash-vol-sel {
-			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	wifi {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio0-supply = <&vcc1v8_pmu>;
-	pmuio1-supply = <&vcc3v3_sys>;
-	vccio1-supply = <&vccio_flash>;
-	vccio2-supply = <&vccio_sd>;
-	vccio3-supply = <&vcc_1v8>;
-	vccio4-supply = <&vcc_dovdd>;
-	vccio5-supply = <&vcc_1v8>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_dovdd>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sfc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&fspi_pins>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <1>;
-	};
-};
-
-&sdio {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	max-frequency = <100000000>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sys>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "qcom,qca9377-bt";
-		clocks = <&rk809 1>;
-		enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
-		max-speed = <2000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&bt_enable>;
-		vddxo-supply = <&vcc3v3_sys>;
-		vddio-supply = <&vcc_1v8>;
-	};
-};
--- a/arch/arm/dts/rv1126-pinctrl.dtsi
+++ b/arch/arm/dts/rv1126-pinctrl.dtsi
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
-	clk_out_ethernet {
-		/omit-if-no-ref/
-		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
-			rockchip,pins =
-				/* clk_out_ethernet_m1 */
-				<2 RK_PC5 2 &pcfg_pull_none>;
-		};
-	};
-	emmc {
-		/omit-if-no-ref/
-		emmc_rstnout: emmc-rstnout {
-			rockchip,pins =
-				/* emmc_rstn */
-				<1 RK_PA3 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		emmc_bus8: emmc-bus8 {
-			rockchip,pins =
-				/* emmc_d0 */
-				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d1 */
-				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d2 */
-				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d3 */
-				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d4 */
-				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d5 */
-				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d6 */
-				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d7 */
-				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		emmc_clk: emmc-clk {
-			rockchip,pins =
-				/* emmc_clko */
-				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		emmc_cmd: emmc-cmd {
-			rockchip,pins =
-				/* emmc_cmd */
-				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
-		};
-	};
-	fspi {
-		/omit-if-no-ref/
-		fspi_pins: fspi-pins {
-			rockchip,pins =
-				/* fspi_clk */
-				<1 RK_PA3 3 &pcfg_pull_down>,
-				/* fspi_cs0n */
-				<0 RK_PD4 3 &pcfg_pull_up>,
-				/* fspi_d0 */
-				<1 RK_PA0 3 &pcfg_pull_up>,
-				/* fspi_d1 */
-				<1 RK_PA1 3 &pcfg_pull_up>,
-				/* fspi_d2 */
-				<0 RK_PD6 3 &pcfg_pull_up>,
-				/* fspi_d3 */
-				<1 RK_PA2 3 &pcfg_pull_up>;
-		};
-	};
-	i2c0 {
-		/omit-if-no-ref/
-		i2c0_xfer: i2c0-xfer {
-			rockchip,pins =
-				/* i2c0_scl */
-				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
-				/* i2c0_sda */
-				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
-		};
-	};
-	i2c2 {
-		/omit-if-no-ref/
-		i2c2_xfer: i2c2-xfer {
-			rockchip,pins =
-				/* i2c2_scl */
-				<0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
-				/* i2c2_sda */
-				<0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
-		};
-	};
-	pwm2 {
-		/omit-if-no-ref/
-		pwm2m0_pins: pwm2m0-pins {
-			rockchip,pins =
-				/* pwm2_pin_m0 */
-				<0 RK_PC0 3 &pcfg_pull_none>;
-		};
-	};
-	pwm11 {
-		/omit-if-no-ref/
-		pwm11m0_pins: pwm11m0-pins {
-			rockchip,pins =
-				/* pwm11_pin_m0 */
-				<3 RK_PA7 6 &pcfg_pull_none>;
-		};
-	};
-	rgmii {
-		/omit-if-no-ref/
-		rgmiim1_miim: rgmiim1-miim {
-			rockchip,pins =
-				/* rgmii_mdc_m1 */
-				<2 RK_PC2 2 &pcfg_pull_none>,
-				/* rgmii_mdio_m1 */
-				<2 RK_PC1 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_rxer: rgmiim1-rxer {
-			rockchip,pins =
-				/* rgmii_rxer_m1 */
-				<2 RK_PC0 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_bus2: rgmiim1-bus2 {
-			rockchip,pins =
-				/* rgmii_rxd0_m1 */
-				<2 RK_PB5 2 &pcfg_pull_none>,
-				/* rgmii_rxd1_m1 */
-				<2 RK_PB6 2 &pcfg_pull_none>,
-				/* rgmii_rxdv_m1 */
-				<2 RK_PB4 2 &pcfg_pull_none>,
-				/* rgmii_txd0_m1 */
-				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd1_m1 */
-				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txen_m1 */
-				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_bus4: rgmiim1-bus4 {
-			rockchip,pins =
-				/* rgmii_rxclk_m1 */
-				<2 RK_PD3 2 &pcfg_pull_none>,
-				/* rgmii_rxd2_m1 */
-				<2 RK_PC7 2 &pcfg_pull_none>,
-				/* rgmii_rxd3_m1 */
-				<2 RK_PD0 2 &pcfg_pull_none>,
-				/* rgmii_txclk_m1 */
-				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd2_m1 */
-				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd3_m1 */
-				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_mclkinout: rgmiim1-mclkinout {
-			rockchip,pins =
-				/* rgmii_clk_m1 */
-				<2 RK_PB7 2 &pcfg_pull_none>;
-		};
-	};
-	sdmmc0 {
-		/omit-if-no-ref/
-		sdmmc0_bus4: sdmmc0-bus4 {
-			rockchip,pins =
-				/* sdmmc0_d0 */
-				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d1 */
-				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d2 */
-				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d3 */
-				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_clk: sdmmc0-clk {
-			rockchip,pins =
-				/* sdmmc0_clk */
-				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_cmd: sdmmc0-cmd {
-			rockchip,pins =
-				/* sdmmc0_cmd */
-				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_det: sdmmc0-det {
-			rockchip,pins =
-				<0 RK_PA3 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_pwr: sdmmc0-pwr {
-			rockchip,pins =
-				<0 RK_PC0 1 &pcfg_pull_none>;
-		};
-	};
-	sdmmc1 {
-		/omit-if-no-ref/
-		sdmmc1_bus4: sdmmc1-bus4 {
-			rockchip,pins =
-				/* sdmmc1_d0 */
-				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d1 */
-				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d2 */
-				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d3 */
-				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_clk: sdmmc1-clk {
-			rockchip,pins =
-				/* sdmmc1_clk */
-				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_cmd: sdmmc1-cmd {
-			rockchip,pins =
-				/* sdmmc1_cmd */
-				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_det: sdmmc1-det {
-			rockchip,pins =
-				<1 RK_PD0 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_pwr: sdmmc1-pwr {
-			rockchip,pins =
-				<1 RK_PD1 2 &pcfg_pull_none>;
-		};
-	};
-	uart0 {
-		/omit-if-no-ref/
-		uart0_xfer: uart0-xfer {
-			rockchip,pins =
-				/* uart0_rx */
-				<1 RK_PC2 1 &pcfg_pull_up>,
-				/* uart0_tx */
-				<1 RK_PC3 1 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart0_ctsn: uart0-ctsn {
-			rockchip,pins =
-				<1 RK_PC1 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		uart0_rtsn: uart0-rtsn {
-			rockchip,pins =
-				<1 RK_PC0 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		uart0_rtsn_gpio: uart0-rts-pin {
-			rockchip,pins =
-				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-	uart1 {
-		/omit-if-no-ref/
-		uart1m0_xfer: uart1m0-xfer {
-			rockchip,pins =
-				/* uart1_rx_m0 */
-				<0 RK_PB7 2 &pcfg_pull_up>,
-				/* uart1_tx_m0 */
-				<0 RK_PB6 2 &pcfg_pull_up>;
-		};
-	};
-	uart2 {
-		/omit-if-no-ref/
-		uart2m1_xfer: uart2m1-xfer {
-			rockchip,pins =
-				/* uart2_rx_m1 */
-				<3 RK_PA3 1 &pcfg_pull_up>,
-				/* uart2_tx_m1 */
-				<3 RK_PA2 1 &pcfg_pull_up>;
-		};
-	};
-	uart3 {
-		/omit-if-no-ref/
-		uart3m0_xfer: uart3m0-xfer {
-			rockchip,pins =
-				/* uart3_rx_m0 */
-				<3 RK_PC7 4 &pcfg_pull_up>,
-				/* uart3_tx_m0 */
-				<3 RK_PC6 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart3m2_xfer: uart3m2-xfer {
-			rockchip,pins =
-				/* uart3_rx_m2 */
-				<3 RK_PA1 4 &pcfg_pull_up>,
-				/* uart3_tx_m2 */
-				<3 RK_PA0 4 &pcfg_pull_up>;
-		};
-	};
-	uart4 {
-		/omit-if-no-ref/
-		uart4m0_xfer: uart4m0-xfer {
-			rockchip,pins =
-				/* uart4_rx_m0 */
-				<3 RK_PA5 4 &pcfg_pull_up>,
-				/* uart4_tx_m0 */
-				<3 RK_PA4 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart4m2_xfer: uart4m2-xfer {
-			rockchip,pins =
-				/* uart4_rx_m2 */
-				<1 RK_PD4 3 &pcfg_pull_up>,
-				/* uart4_tx_m2 */
-				<1 RK_PD5 3 &pcfg_pull_up>;
-		};
-	};
-	uart5 {
-		/omit-if-no-ref/
-		uart5m0_xfer: uart5m0-xfer {
-			rockchip,pins =
-				/* uart5_rx_m0 */
-				<3 RK_PA7 4 &pcfg_pull_up>,
-				/* uart5_tx_m0 */
-				<3 RK_PA6 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart5m2_xfer: uart5m2-xfer {
-			rockchip,pins =
-				/* uart5_rx_m2 */
-				<2 RK_PA1 3 &pcfg_pull_up>,
-				/* uart5_tx_m2 */
-				<2 RK_PA0 3 &pcfg_pull_up>;
-		};
-	};
-};
--- a/arch/arm/dts/rv1126-sonoff-ihost.dts
+++ b/arch/arm/dts/rv1126-sonoff-ihost.dts
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-sonoff-ihost.dtsi"
-
-/ {
-	model = "Sonoff iHost 4G";
-	compatible = "itead,sonoff-ihost", "rockchip,rv1126";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_arm>;
-};
--- a/arch/arm/dts/rv1126-sonoff-ihost.dtsi
+++ b/arch/arm/dts/rv1126-sonoff-ihost.dtsi
@@ -1,404 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
-	aliases {
-		ethernet0 = &gmac;
-		mmc0 = &emmc;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	vcc5v0_sys: regulator-vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	sdio_pwrseq: pwrseq-sdio {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&emmc {
-	bus-width = <8>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
-	rockchip,default-sample-phase = <90>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc_buck5>;
-		vcc6-supply = <&vcc_buck5>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-
-		regulators {
-			vdd_npu_vepu: DCDC_REG1 {
-				regulator-name = "vdd_npu_vepu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <650000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_arm: DCDC_REG2 {
-				regulator-name = "vdd_arm";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <725000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc3v3_sys: DCDC_REG4 {
-				regulator-name = "vcc3v3_sys";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcc_buck5: DCDC_REG5 {
-				regulator-name = "vcc_buck5";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <2200000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2200000>;
-				};
-			};
-
-			vcc_0v8: LDO_REG1 {
-				regulator-name = "vcc_0v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_pmu: LDO_REG2 {
-				regulator-name = "vcc1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd0v8_pmu: LDO_REG3 {
-				regulator-name = "vcc0v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <800000>;
-				};
-			};
-
-			vcc_1v8: LDO_REG4 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_dovdd: LDO_REG5 {
-				regulator-name = "vcc_dovdd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_dvdd: LDO_REG6 {
-				regulator-name = "vcc_dvdd";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_avdd: LDO_REG7 {
-				regulator-name = "vcc_avdd";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG8 {
-				regulator-name = "vccio_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: LDO_REG9 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_5v0: SWITCH_REG1 {
-				regulator-name = "vcc_5v0";
-			};
-
-			vcc_3v3: SWITCH_REG2 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	status = "okay";
-	clock-frequency = <400000>;
-
-	pcf8563: rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-		clock-output-names = "xin32k";
-	};
-};
-
-&gmac {
-	assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
-			  <&cru CLK_GMAC_TX_RX>;
-	assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
-				 <&cru RMII_MODE_CLK>;
-	assigned-clock-rates = <0>, <50000000>;
-	clock_in_out = "output";
-	phy-handle = <&phy>;
-	phy-mode = "rmii";
-	phy-supply = <&vcc_3v3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
-	status = "okay";
-};
-
-&mdio {
-	phy: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eth_phy_rst>;
-		reset-active-low;
-		reset-assert-us = <50000>;
-		reset-deassert-us = <10000>;
-		reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	ethernet {
-		eth_phy_rst: eth-phy-rst {
-			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-	bt {
-		bt_enable: bt-enable {
-			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_wake_dev: bt-wake-dev {
-			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_wake_host: bt-wake-host {
-			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	wifi {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio0-supply = <&vcc1v8_pmu>;
-	pmuio1-supply = <&vcc3v3_sys>;
-	vccio1-supply = <&vcc_1v8>;
-	vccio2-supply = <&vccio_sd>;
-	vccio3-supply = <&vcc_1v8>;
-	vccio4-supply = <&vcc_dovdd>;
-	vccio5-supply = <&vcc_1v8>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_dovdd>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdio {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	max-frequency = <100000000>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sys>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
-	uart-has-rtscts;
-	status = "okay";
-
-	bluetooth {
-		compatible = "realtek,rtl8723ds-bt";
-		device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
-		enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
-		host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
-		max-speed = <2000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3m2_xfer>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4m2_xfer>;
-	status = "okay";
-};
--- a/arch/arm/dts/rv1126.dtsi
+++ b/arch/arm/dts/rv1126.dtsi
@@ -1,623 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rockchip,rv1126-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rockchip,rv1126-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	compatible = "rockchip,rv1126";
-
-	interrupt-parent = <&gic>;
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c2 = &i2c2;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@f00 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf00>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu1: cpu@f01 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf01>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu2: cpu@f02 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf02>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu3: cpu@f03 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf03>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
-	};
-
-	display_subsystem {
-		compatible = "rockchip,display-subsystem";
-		ports = <&vop_out>;
-	};
-
-	xin24m: oscillator {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-		#clock-cells = <0>;
-	};
-
-	grf: syscon@fe000000 {
-		compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
-		reg = <0xfe000000 0x20000>;
-	};
-
-	pmugrf: syscon@fe020000 {
-		compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
-		reg = <0xfe020000 0x1000>;
-
-		pmu_io_domains: io-domains {
-			compatible = "rockchip,rv1126-pmu-io-voltage-domain";
-			status = "disabled";
-		};
-	};
-
-	qos_emmc: qos@fe860000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860000 0x20>;
-	};
-
-	qos_nandc: qos@fe860080 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860080 0x20>;
-	};
-
-	qos_sfc: qos@fe860200 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860200 0x20>;
-	};
-
-	qos_sdio: qos@fe86c000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe86c000 0x20>;
-	};
-
-	qos_iep: qos@fe8a0000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0000 0x20>;
-	};
-
-	qos_rga_rd: qos@fe8a0080 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0080 0x20>;
-	};
-
-	qos_rga_wr: qos@fe8a0100 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0100 0x20>;
-	};
-
-	qos_vop: qos@fe8a0180 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0180 0x20>;
-	};
-
-	gic: interrupt-controller@feff0000 {
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-
-		reg = <0xfeff1000 0x1000>,
-		      <0xfeff2000 0x2000>,
-		      <0xfeff4000 0x2000>,
-		      <0xfeff6000 0x2000>;
-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	pmu: power-management@ff3e0000 {
-		compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
-		reg = <0xff3e0000 0x1000>;
-
-		power: power-controller {
-			compatible = "rockchip,rv1126-power-controller";
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			power-domain@RV1126_PD_NVM {
-				reg = <RV1126_PD_NVM>;
-				clocks = <&cru HCLK_EMMC>,
-					 <&cru CLK_EMMC>,
-					 <&cru HCLK_NANDC>,
-					 <&cru CLK_NANDC>,
-					 <&cru HCLK_SFC>,
-					 <&cru HCLK_SFCXIP>,
-					 <&cru SCLK_SFC>;
-				pm_qos = <&qos_emmc>,
-					 <&qos_nandc>,
-					 <&qos_sfc>;
-				#power-domain-cells = <0>;
-			};
-
-			power-domain@RV1126_PD_SDIO {
-				reg = <RV1126_PD_SDIO>;
-				clocks = <&cru HCLK_SDIO>,
-					 <&cru CLK_SDIO>;
-				pm_qos = <&qos_sdio>;
-				#power-domain-cells = <0>;
-			};
-
-			power-domain@RV1126_PD_VO {
-				reg = <RV1126_PD_VO>;
-				clocks = <&cru ACLK_RGA>,
-					 <&cru HCLK_RGA>,
-					 <&cru CLK_RGA_CORE>,
-					 <&cru ACLK_VOP>,
-					 <&cru HCLK_VOP>,
-					 <&cru DCLK_VOP>,
-					 <&cru PCLK_DSIHOST>,
-					 <&cru ACLK_IEP>,
-					 <&cru HCLK_IEP>,
-					 <&cru CLK_IEP_CORE>;
-				pm_qos = <&qos_rga_rd>,
-					 <&qos_rga_wr>,
-					 <&qos_vop>,
-					 <&qos_iep>;
-				#power-domain-cells = <0>;
-			};
-		};
-	};
-
-	i2c0: i2c@ff3f0000 {
-		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
-		reg = <0xff3f0000 0x1000>;
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,grf = <&pmugrf>;
-		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
-		clock-names = "i2c", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c2: i2c@ff400000 {
-		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
-		reg = <0xff400000 0x1000>;
-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,grf = <&pmugrf>;
-		clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
-		clock-names = "i2c", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c2_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	uart1: serial@ff410000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff410000 0x100>;
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 7>, <&dmac 6>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	pwm2: pwm@ff430020 {
-		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
-		reg = <0xff430020 0x10>;
-		clock-names = "pwm", "pclk";
-		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm2m0_pins>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pmucru: clock-controller@ff480000 {
-		compatible = "rockchip,rv1126-pmucru";
-		reg = <0xff480000 0x1000>;
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	cru: clock-controller@ff490000 {
-		compatible = "rockchip,rv1126-cru";
-		reg = <0xff490000 0x1000>;
-		clocks = <&xin24m>;
-		clock-names = "xin24m";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	dmac: dma-controller@ff4e0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0xff4e0000 0x4000>;
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		#dma-cells = <1>;
-		arm,pl330-periph-burst;
-		clocks = <&cru ACLK_DMAC>;
-		clock-names = "apb_pclk";
-	};
-
-	pwm11: pwm@ff550030 {
-		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
-		reg = <0xff550030 0x10>;
-		clock-names = "pwm", "pclk";
-		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-		pinctrl-0 = <&pwm11m0_pins>;
-		pinctrl-names = "default";
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	uart0: serial@ff560000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff560000 0x100>;
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 5>, <&dmac 4>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart2: serial@ff570000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff570000 0x100>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 9>, <&dmac 8>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2m1_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart3: serial@ff580000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff580000 0x100>;
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 11>, <&dmac 10>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart3m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart4: serial@ff590000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff590000 0x100>;
-		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 13>, <&dmac 12>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart4m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart5: serial@ff5a0000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff5a0000 0x100>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 15>, <&dmac 14>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart5m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	saradc: adc@ff5e0000 {
-		compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
-		reg = <0xff5e0000 0x100>;
-		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-		#io-channel-cells = <1>;
-		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
-		clock-names = "saradc", "apb_pclk";
-		resets = <&cru SRST_SARADC_P>;
-		reset-names = "saradc-apb";
-		status = "disabled";
-	};
-
-	timer0: timer@ff660000 {
-		compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
-		reg = <0xff660000 0x20>;
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
-		clock-names = "pclk", "timer";
-	};
-
-	vop: vop@ffb00000 {
-		compatible = "rockchip,rv1126-vop";
-		reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
-		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
-		reset-names = "axi", "ahb", "dclk";
-		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
-		iommus = <&vop_mmu>;
-		power-domains = <&power RV1126_PD_VO>;
-		status = "disabled";
-
-		vop_out: port {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			vop_out_rgb: endpoint@0 {
-				reg = <0>;
-			};
-
-			vop_out_dsi: endpoint@1 {
-				reg = <1>;
-			};
-		};
-	};
-
-	vop_mmu: iommu@ffb00f00 {
-		compatible = "rockchip,iommu";
-		reg = <0xffb00f00 0x100>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "aclk", "iface";
-		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-		#iommu-cells = <0>;
-		power-domains = <&power RV1126_PD_VO>;
-		status = "disabled";
-	};
-
-	gmac: ethernet@ffc40000 {
-		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
-		reg = <0xffc40000 0x4000>;
-		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "macirq", "eth_wake_irq";
-		rockchip,grf = <&grf>;
-		clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
-			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
-			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
-			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
-		clock-names = "stmmaceth", "mac_clk_rx",
-			      "mac_clk_tx", "clk_mac_ref",
-			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref";
-		resets = <&cru SRST_GMAC_A>;
-		reset-names = "stmmaceth";
-
-		snps,mixed-burst;
-		snps,tso;
-
-		snps,axi-config = <&stmmac_axi_setup>;
-		snps,mtl-rx-config = <&mtl_rx_setup>;
-		snps,mtl-tx-config = <&mtl_tx_setup>;
-		status = "disabled";
-
-		mdio: mdio {
-			compatible = "snps,dwmac-mdio";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-		};
-
-		stmmac_axi_setup: stmmac-axi-config {
-			snps,wr_osr_lmt = <4>;
-			snps,rd_osr_lmt = <8>;
-			snps,blen = <0 0 0 0 16 8 4>;
-		};
-
-		mtl_rx_setup: rx-queues-config {
-			snps,rx-queues-to-use = <1>;
-			queue0 {};
-		};
-
-		mtl_tx_setup: tx-queues-config {
-			snps,tx-queues-to-use = <1>;
-			queue0 {};
-		};
-	};
-
-	emmc: mmc@ffc50000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc50000 0x4000>;
-		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
-			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		power-domains = <&power RV1126_PD_NVM>;
-		status = "disabled";
-	};
-
-	sdmmc: mmc@ffc60000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc60000 0x4000>;
-		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
-			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		status = "disabled";
-	};
-
-	sdio: mmc@ffc70000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc70000 0x4000>;
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
-			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		power-domains = <&power RV1126_PD_SDIO>;
-		status = "disabled";
-	};
-
-	sfc: spi@ffc90000  {
-		compatible = "rockchip,sfc";
-		reg = <0xffc90000 0x4000>;
-		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-		assigned-clocks = <&cru SCLK_SFC>;
-		assigned-clock-rates = <80000000>;
-		clock-names = "clk_sfc", "hclk_sfc";
-		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-		power-domains = <&power RV1126_PD_NVM>;
-		status = "disabled";
-	};
-
-	pinctrl: pinctrl {
-		compatible = "rockchip,rv1126-pinctrl";
-		rockchip,grf = <&grf>;
-		rockchip,pmu = <&pmugrf>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio@ff460000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff460000 0x100>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@ff620000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff620000 0x100>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@ff630000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff630000 0x100>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@ff640000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff640000 0x100>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio4: gpio@ff650000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff650000 0x100>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-	};
-};
-
-#include "rv1126-pinctrl.dtsi"
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -29,6 +29,7 @@ enum rk3588_pll_id {
 	V0PLL,
 	AUPLL,
 	PPLL,
+	SPLL,
 	PLL_COUNT,
 };

@@ -150,6 +151,9 @@ struct pll_rate_table {
 #define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
 #define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)

+#define RK3588_SBUSCRU_SPLL_CON(x)	((x) * 0x4 + 0x220)
+#define RK3588_SBUSCRU_MODE_CON0	0x280
+
 enum {
 	/* CRU_CLK_SEL8_CON */
 	ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT		= 14,
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -427,6 +427,7 @@ config ROCKCHIP_RV1126
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
 	imply SPL_SYSCON
+	imply OF_UPSTREAM

 config ROCKCHIP_USB_UART
 	bool "Route uart output to usb pins"
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "px30"

+config ROCKCHIP_COMMON_STACK_ADDR
+	default y
+
 config SYS_MALLOC_F_LEN
-	default 0x400
+	default 0x400 if !SPL_SHARES_INIT_SP_ADDR

 config SPL_SERIAL
 	default y
@@ -83,6 +86,9 @@ config TPL_TEXT_BASE
 config TPL_STACK
 	default 0xff0e4fff

+config TPL_SYS_MALLOC_F_LEN
+	default 0x600
+
 config DEBUG_UART_CHANNEL
 	int "Mux channel to use for debug UART2/UART3"
 	depends on DEBUG_UART_BOARD_INIT
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568
 	help
 	  Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.

+config TARGET_POWKIDDY_X55_RK3566
+	bool "Powkiddy X55"
+	help
+	  Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
 config TARGET_QUARTZ64_RK3566
 	bool "Pine64 Quartz64"
 	help
@@ -48,5 +53,6 @@ source "board/rockchip/evb_rk3568/Kconfig"
 source "board/anbernic/rgxx3_rk3566/Kconfig"
 source "board/hardkernel/odroid_m1/Kconfig"
 source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"

 endif
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@ config TARGET_NANOPCT6_RK3588
 	  Power: 5.5*2.1mm DC Jack, 12VDC input
 	  Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)

+config TARGET_NOVA_RK3588
+	bool "Indiedroid Nova RK3588"
+	select BOARD_LATE_INIT
+	help
+	  Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+	  It comes in configurations from 4GB of RAM to 16GB of RAM,
+	  includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+	  GPIO header for expansion.
+
 config TARGET_RK3588_NEU6
 	bool "Edgeble Neural Compute Module 6(Neu6) SoM"
 	select BOARD_LATE_INIT
@@ -223,6 +232,7 @@ config TEXT_BASE

 source "board/edgeble/neural-compute-module-6/Kconfig"
 source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
 source "board/pine64/quartzpro64-rk3588/Kconfig"
 source "board/turing/turing-rk1-rk3588/Kconfig"
 source "board/radxa/rock5a-rk3588s/Kconfig"
--- a/board/indiedroid/nova/Kconfig
+++ b/board/indiedroid/nova/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOVA_RK3588
+
+config SYS_BOARD
+	default "nova-rk3588s"
+
+config SYS_VENDOR
+	default "indiedroid"
+
+config SYS_CONFIG_NAME
+	default "nova-rk3588s"
+
+endif
--- a/board/indiedroid/nova/MAINTAINERS
+++ b/board/indiedroid/nova/MAINTAINERS
@@ -0,0 +1,6 @@
+INDIEDROID-NOVA-RK3588
+M:	Chris Morgan <macromorgan@hotmail.com>
+S:	Maintained
+F:	board/indiedroid/nova
+F:	configs/nova-rk3588s_defconfig
+F:	include/configs/nova-rk3588s.h
--- a/board/powkiddy/x55/Kconfig
+++ b/board/powkiddy/x55/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POWKIDDY_X55_RK3566
+
+config SYS_BOARD
+	default "x55"
+
+config SYS_VENDOR
+	default "powkiddy"
+
+config SYS_CONFIG_NAME
+	default "powkiddy-x55-rk3566"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+
+endif
--- a/board/powkiddy/x55/MAINTAINERS
+++ b/board/powkiddy/x55/MAINTAINERS
@@ -0,0 +1,7 @@
+X55
+M:	Chris Morgan <macromorgan@hotmail.com>
+S:	Maintained
+F:	board/powkiddy/x55
+F:	include/configs/powkiddy-x55-rk3566.h
+F:	configs/powkiddy-x55-rk3566_defconfig
+F:	arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
--- a/board/powkiddy/x55/Makefile
+++ b/board/powkiddy/x55/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+#
+
+obj-y += x55.o
--- a/board/powkiddy/x55/x55.c
+++ b/board/powkiddy/x55/x55.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Chris Morgan <macromorgan@hotmail.com>
+ */
+
+#include <asm/io.h>
+
+#define GPIO4_BASE		0xfe770000
+#define GPIO_SWPORT_DR_L	0x0000
+#define GPIO_SWPORT_DDR_L	0x0008
+#define GPIO_B4			BIT(12)
+#define GPIO_B5			BIT(13)
+#define GPIO_B6			BIT(14)
+
+#define GPIO_WRITEMASK(bits)	((bits) << 16)
+
+/*
+ * Start LED very early so user knows device is on. Set color
+ * to red.
+ */
+void spl_board_init(void)
+{
+	/* Set GPIO4_B4, GPIO4_B5, and GPIO4_B6 to output. */
+	writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | \
+	       (GPIO_B6 | GPIO_B5 | GPIO_B4),
+	       (GPIO4_BASE + GPIO_SWPORT_DDR_L));
+	/* Set GPIO4_B5 and GPIO4_B6 to 0 and GPIO4_B4 to 1. */
+	writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B4,
+	       (GPIO4_BASE + GPIO_SWPORT_DR_L));
+}
+
+int rk_board_late_init(void)
+{
+	/* Turn off red LED and turn on orange LED. */
+	writel(GPIO_WRITEMASK(GPIO_B6 | GPIO_B5 | GPIO_B4) | GPIO_B6,
+	       (GPIO4_BASE + GPIO_SWPORT_DR_L));
+
+	return 0;
+}
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -16,7 +16,6 @@ CONFIG_ROCKCHIP_PX30=y
 CONFIG_TARGET_EVB_PX30=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_EVB_PX30=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_SYS_ARCH_TIMER=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-edgeble-neu2-io"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-edgeble-neu2-io"
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RV1126=y
 CONFIG_TARGET_RV1126_NEU2=y
--- a/configs/nova-rk3588s_defconfig
+++ b/configs/nova-rk3588s_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-indiedroid-nova"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_NOVA_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -19,7 +19,6 @@ CONFIG_TARGET_ODROID_GO2=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/powkiddy-x55-rk3566_defconfig
+++ b/configs/powkiddy-x55-rk3566_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-powkiddy-x55"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-powkiddy-x55.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -17,7 +17,6 @@ CONFIG_TARGET_PX30_CORE=y
 CONFIG_DEBUG_UART_CHANNEL=1
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_SPL_STACK=0x400000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -2,28 +2,15 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000
 CONFIG_DEFAULT_DEVICE_TREE="px30-ringneck-haikou"
-CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
+# CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
 CONFIG_TARGET_RINGNECK_PX30=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
+# CONFIG_TPL_LIBCOMMON_SUPPORT is not set
 CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
-CONFIG_SPL_STACK_R=y
 CONFIG_DEBUG_UART_BASE=0xFF030000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
@@ -42,11 +29,11 @@ CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF=y
 # CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_TPL_SYS_MALLOC_SIMPLE is not set
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
--- a/configs/sonoff-ihost-rv1126_defconfig
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -5,7 +5,7 @@ CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_SYS_ARCH_TIMER=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rv1126-sonoff-ihost"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1126-sonoff-ihost"
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RV1126=y
 CONFIG_TARGET_RV1126_SONOFF_IHOST=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -104,6 +104,7 @@ List of mainline supported Rockchip boards:
     - Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
     - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
     - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+     - Powkiddy X55 (powkiddy-x55-rk3566)
     - Radxa CM3 IO Board (radxa-cm3-io-rk3566)

 * rk3568
@@ -123,6 +124,7 @@ List of mainline supported Rockchip boards:
     - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
     - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
     - Generic RK3588S/RK3588 (generic-rk3588)
+     - Indiedroid Nova (nova-rk3588s)
     - Pine64 QuartzPro64 (quartzpro64-rk3588)
     - Radxa ROCK 5A (rock5a-rk3588s)
     - Radxa ROCK 5B (rock5b-rk3588)
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -37,6 +37,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
 	RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
 	RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
 	RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+	RK3588_PLL_RATE(702000000, 3, 351, 2, 0),
 	RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
 	RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
 	RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
@@ -65,6 +66,15 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
 		     RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
 	[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
 		     RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * The SPLL is part of the SBUSCRU, not the main CRU and as
+	 * such only directly accessible during the SPL stage.
+	 */
+	[SPLL] = PLL(pll_rk3588, 0, RK3588_SBUSCRU_SPLL_CON(0),
+		     RK3588_SBUSCRU_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
+#endif
+
 };

 #ifndef CONFIG_SPL_BUILD
@@ -2044,6 +2054,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {

 #ifdef CONFIG_SPL_BUILD
 #define SCRU_BASE			0xfd7d0000
+#define SBUSCRU_BASE			0xfd7d8000

 static ulong rk3588_scru_clk_get_rate(struct clk *clk)
 {
@@ -2118,15 +2129,28 @@ static ulong rk3588_scru_clk_set_rate(struct clk *clk, ulong rate)
 	return rk3588_scru_clk_get_rate(clk);
 }

+static int rk3588_scru_clk_probe(struct udevice *dev)
+{
+	int ret;
+
+	ret = rockchip_pll_set_rate(&rk3588_pll_clks[SPLL],
+				    (void *)SBUSCRU_BASE, SPLL, SPLL_HZ);
+	if (ret)
+		debug("%s setting spll rate failed %d\n", __func__, ret);
+
+	return 0;
+}
+
 static const struct clk_ops rk3588_scru_clk_ops = {
 	.get_rate = rk3588_scru_clk_get_rate,
 	.set_rate = rk3588_scru_clk_set_rate,
 };

 U_BOOT_DRIVER(rockchip_rk3588_scru) = {
-	.name = "rockchip_rk3588_scru",
-	.id = UCLASS_CLK,
-	.ops = &rk3588_scru_clk_ops,
+	.name	= "rockchip_rk3588_scru",
+	.id	= UCLASS_CLK,
+	.ops	= &rk3588_scru_clk_ops,
+	.probe	= rk3588_scru_clk_probe,
 };

 static int rk3588_scmi_spl_glue_bind(struct udevice *dev)
--- a/include/configs/nova-rk3588s.h
+++ b/include/configs/nova-rk3588s.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Collabora Ltd.
+ */
+
+#ifndef __NOVA_RK3588S_H
+#define __NOVA_RK3588S_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __NOVA_RK3588S_H */
--- a/include/configs/powkiddy-x55-rk3566.h
+++ b/include/configs/powkiddy-x55-rk3566.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __POWKIDDY_X55_RK3566_H
+#define __POWKIDDY_X55_RK3566_H
+
+#include <configs/rk3568_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+			"stdout=serial,vidconsole\0" \
+			"stderr=serial,vidconsole\0"
+
+#endif
--- a/include/dt-bindings/clock/rockchip,rv1126-cru.h
+++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h
@@ -1,632 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
- * Author: Finley Xiao <finley.xiao@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
-
-/* pmucru-clocks indices */
-
-/* pll clocks */
-#define PLL_GPLL		1
-
-/* sclk (special clocks) */
-#define CLK_OSC0_DIV32K		2
-#define CLK_RTC32K		3
-#define CLK_WIFI_DIV		4
-#define CLK_WIFI_OSC0		5
-#define CLK_WIFI		6
-#define CLK_PMU			7
-#define SCLK_UART1_DIV		8
-#define SCLK_UART1_FRACDIV	9
-#define SCLK_UART1_MUX		10
-#define SCLK_UART1		11
-#define CLK_I2C0		12
-#define CLK_I2C2		13
-#define CLK_CAPTURE_PWM0	14
-#define CLK_PWM0		15
-#define CLK_CAPTURE_PWM1	16
-#define CLK_PWM1		17
-#define CLK_SPI0		18
-#define DBCLK_GPIO0		19
-#define CLK_PMUPVTM		20
-#define CLK_CORE_PMUPVTM	21
-#define CLK_REF12M		22
-#define CLK_USBPHY_OTG_REF	23
-#define CLK_USBPHY_HOST_REF	24
-#define CLK_REF24M		25
-#define CLK_MIPIDSIPHY_REF	26
-
-/* pclk */
-#define PCLK_PDPMU		30
-#define PCLK_PMU		31
-#define PCLK_UART1		32
-#define PCLK_I2C0		33
-#define PCLK_I2C2		34
-#define PCLK_PWM0		35
-#define PCLK_PWM1		36
-#define PCLK_SPI0		37
-#define PCLK_GPIO0		38
-#define PCLK_PMUSGRF		39
-#define PCLK_PMUGRF		40
-#define PCLK_PMUCRU		41
-#define PCLK_CHIPVEROTP		42
-#define PCLK_PDPMU_NIU		43
-#define PCLK_PMUPVTM		44
-#define PCLK_SCRKEYGEN		45
-
-#define CLKPMU_NR_CLKS		(PCLK_SCRKEYGEN + 1)
-
-/* cru-clocks indices */
-
-/* pll clocks */
-#define PLL_APLL		1
-#define PLL_DPLL		2
-#define PLL_CPLL		3
-#define PLL_HPLL		4
-
-/* sclk (special clocks) */
-#define ARMCLK			5
-#define USB480M			6
-#define CLK_CORE_CPUPVTM	7
-#define CLK_CPUPVTM		8
-#define CLK_SCR1		9
-#define CLK_SCR1_CORE		10
-#define CLK_SCR1_RTC		11
-#define CLK_SCR1_JTAG		12
-#define SCLK_UART0_DIV		13
-#define SCLK_UART0_FRAC		14
-#define SCLK_UART0_MUX		15
-#define SCLK_UART0		16
-#define SCLK_UART2_DIV		17
-#define SCLK_UART2_FRAC		18
-#define SCLK_UART2_MUX		19
-#define SCLK_UART2		20
-#define SCLK_UART3_DIV		21
-#define SCLK_UART3_FRAC		22
-#define SCLK_UART3_MUX		23
-#define SCLK_UART3		24
-#define SCLK_UART4_DIV		25
-#define SCLK_UART4_FRAC		26
-#define SCLK_UART4_MUX		27
-#define SCLK_UART4		28
-#define SCLK_UART5_DIV		29
-#define SCLK_UART5_FRAC		30
-#define SCLK_UART5_MUX		31
-#define SCLK_UART5		32
-#define CLK_I2C1		33
-#define CLK_I2C3		34
-#define CLK_I2C4		35
-#define CLK_I2C5		36
-#define CLK_SPI1		37
-#define CLK_CAPTURE_PWM2	38
-#define CLK_PWM2		39
-#define DBCLK_GPIO1		40
-#define DBCLK_GPIO2		41
-#define DBCLK_GPIO3		42
-#define DBCLK_GPIO4		43
-#define CLK_SARADC		44
-#define CLK_TIMER0		45
-#define CLK_TIMER1		46
-#define CLK_TIMER2		47
-#define CLK_TIMER3		48
-#define CLK_TIMER4		49
-#define CLK_TIMER5		50
-#define CLK_CAN			51
-#define CLK_NPU_TSADC		52
-#define CLK_NPU_TSADCPHY	53
-#define CLK_CPU_TSADC		54
-#define CLK_CPU_TSADCPHY	55
-#define CLK_CRYPTO_CORE		56
-#define CLK_CRYPTO_PKA		57
-#define MCLK_I2S0_TX_DIV	58
-#define MCLK_I2S0_TX_FRACDIV	59
-#define MCLK_I2S0_TX_MUX	60
-#define MCLK_I2S0_TX		61
-#define MCLK_I2S0_RX_DIV	62
-#define MCLK_I2S0_RX_FRACDIV	63
-#define MCLK_I2S0_RX_MUX	64
-#define MCLK_I2S0_RX		65
-#define MCLK_I2S0_TX_OUT2IO	66
-#define MCLK_I2S0_RX_OUT2IO	67
-#define MCLK_I2S1_DIV		68
-#define MCLK_I2S1_FRACDIV	69
-#define MCLK_I2S1_MUX		70
-#define MCLK_I2S1		71
-#define MCLK_I2S1_OUT2IO	72
-#define MCLK_I2S2_DIV		73
-#define MCLK_I2S2_FRACDIV	74
-#define MCLK_I2S2_MUX		75
-#define MCLK_I2S2		76
-#define MCLK_I2S2_OUT2IO	77
-#define MCLK_PDM		78
-#define SCLK_ADUPWM_DIV		79
-#define SCLK_AUDPWM_FRACDIV	80
-#define SCLK_AUDPWM_MUX		81
-#define	SCLK_AUDPWM		82
-#define CLK_ACDCDIG_ADC		83
-#define CLK_ACDCDIG_DAC		84
-#define CLK_ACDCDIG_I2C		85
-#define CLK_VENC_CORE		86
-#define CLK_VDEC_CORE		87
-#define CLK_VDEC_CA		88
-#define CLK_VDEC_HEVC_CA	89
-#define CLK_RGA_CORE		90
-#define CLK_IEP_CORE		91
-#define CLK_ISP_DIV		92
-#define CLK_ISP_NP5		93
-#define CLK_ISP_NUX		94
-#define CLK_ISP			95
-#define CLK_CIF_OUT_DIV		96
-#define CLK_CIF_OUT_FRACDIV	97
-#define CLK_CIF_OUT_MUX		98
-#define CLK_CIF_OUT		99
-#define CLK_MIPICSI_OUT_DIV	100
-#define CLK_MIPICSI_OUT_FRACDIV	101
-#define CLK_MIPICSI_OUT_MUX	102
-#define CLK_MIPICSI_OUT		103
-#define CLK_ISPP_DIV		104
-#define CLK_ISPP_NP5		105
-#define CLK_ISPP_NUX		106
-#define CLK_ISPP		107
-#define CLK_SDMMC		108
-#define SCLK_SDMMC_DRV		109
-#define SCLK_SDMMC_SAMPLE	110
-#define CLK_SDIO		111
-#define SCLK_SDIO_DRV		112
-#define SCLK_SDIO_SAMPLE	113
-#define CLK_EMMC		114
-#define SCLK_EMMC_DRV		115
-#define SCLK_EMMC_SAMPLE	116
-#define CLK_NANDC		117
-#define SCLK_SFC		118
-#define CLK_USBHOST_UTMI_OHCI	119
-#define CLK_USBOTG_REF		120
-#define CLK_GMAC_DIV		121
-#define CLK_GMAC_RGMII_M0	122
-#define CLK_GMAC_SRC_M0		123
-#define CLK_GMAC_RGMII_M1	124
-#define CLK_GMAC_SRC_M1		125
-#define CLK_GMAC_SRC		126
-#define CLK_GMAC_REF		127
-#define CLK_GMAC_TX_SRC		128
-#define CLK_GMAC_TX_DIV5	129
-#define CLK_GMAC_TX_DIV50	130
-#define RGMII_MODE_CLK		131
-#define CLK_GMAC_RX_SRC		132
-#define CLK_GMAC_RX_DIV2	133
-#define CLK_GMAC_RX_DIV20	134
-#define RMII_MODE_CLK		135
-#define CLK_GMAC_TX_RX		136
-#define CLK_GMAC_PTPREF		137
-#define CLK_GMAC_ETHERNET_OUT	138
-#define CLK_DDRPHY		139
-#define CLK_DDR_MON		140
-#define TMCLK_DDR_MON		141
-#define CLK_NPU_DIV		142
-#define CLK_NPU_NP5		143
-#define CLK_CORE_NPU		144
-#define CLK_CORE_NPUPVTM	145
-#define CLK_NPUPVTM		146
-#define SCLK_DDRCLK		147
-#define CLK_OTP			148
-
-/* dclk */
-#define DCLK_DECOM		150
-#define DCLK_VOP_DIV		151
-#define DCLK_VOP_FRACDIV	152
-#define DCLK_VOP_MUX		153
-#define DCLK_VOP		154
-#define DCLK_CIF		155
-#define DCLK_CIFLITE		156
-
-/* aclk */
-#define ACLK_PDBUS		160
-#define ACLK_DMAC		161
-#define ACLK_DCF		162
-#define ACLK_SPINLOCK		163
-#define ACLK_DECOM		164
-#define ACLK_PDCRYPTO		165
-#define ACLK_CRYPTO		166
-#define ACLK_PDVEPU		167
-#define ACLK_VENC		168
-#define ACLK_PDVDEC		169
-#define ACLK_PDJPEG		170
-#define ACLK_VDEC		171
-#define ACLK_JPEG		172
-#define ACLK_PDVO		173
-#define ACLK_RGA		174
-#define ACLK_VOP		175
-#define ACLK_IEP		176
-#define ACLK_PDVI_DIV		177
-#define ACLK_PDVI_NP5		178
-#define ACLK_PDVI		179
-#define ACLK_ISP		180
-#define ACLK_CIF		181
-#define ACLK_CIFLITE		182
-#define ACLK_PDISPP_DIV		183
-#define ACLK_PDISPP_NP5		184
-#define ACLK_PDISPP		185
-#define ACLK_ISPP		186
-#define ACLK_PDPHP		187
-#define ACLK_PDUSB		188
-#define ACLK_USBOTG		189
-#define ACLK_PDGMAC		190
-#define ACLK_GMAC		191
-#define ACLK_PDNPU_DIV		192
-#define ACLK_PDNPU_NP5		193
-#define ACLK_PDNPU		194
-#define ACLK_NPU		195
-
-/* hclk */
-#define HCLK_PDCORE_NIU		200
-#define HCLK_PDUSB		201
-#define HCLK_PDCRYPTO		202
-#define HCLK_CRYPTO		203
-#define HCLK_PDAUDIO		204
-#define HCLK_I2S0		205
-#define HCLK_I2S1		206
-#define HCLK_I2S2		207
-#define HCLK_PDM		208
-#define HCLK_AUDPWM		209
-#define HCLK_PDVEPU		210
-#define HCLK_VENC		211
-#define HCLK_PDVDEC		212
-#define HCLK_PDJPEG		213
-#define HCLK_VDEC		214
-#define HCLK_JPEG		215
-#define HCLK_PDVO		216
-#define HCLK_RGA		217
-#define HCLK_VOP		218
-#define HCLK_IEP		219
-#define HCLK_PDVI		220
-#define HCLK_ISP		221
-#define HCLK_CIF		222
-#define HCLK_CIFLITE		223
-#define HCLK_PDISPP		224
-#define HCLK_ISPP		225
-#define HCLK_PDPHP		226
-#define HCLK_PDSDMMC		227
-#define HCLK_SDMMC		228
-#define HCLK_PDSDIO		229
-#define HCLK_SDIO		230
-#define HCLK_PDNVM		231
-#define HCLK_EMMC		232
-#define HCLK_NANDC		233
-#define HCLK_SFC		234
-#define HCLK_SFCXIP		235
-#define HCLK_PDBUS		236
-#define HCLK_USBHOST		237
-#define HCLK_USBHOST_ARB	238
-#define HCLK_PDNPU		239
-#define HCLK_NPU		240
-
-/* pclk */
-#define PCLK_CPUPVTM		245
-#define PCLK_PDBUS		246
-#define PCLK_DCF		247
-#define PCLK_WDT		248
-#define PCLK_MAILBOX		249
-#define PCLK_UART0		250
-#define PCLK_UART2		251
-#define PCLK_UART3		252
-#define PCLK_UART4		253
-#define PCLK_UART5		254
-#define PCLK_I2C1		255
-#define PCLK_I2C3		256
-#define PCLK_I2C4		257
-#define PCLK_I2C5		258
-#define PCLK_SPI1		259
-#define PCLK_PWM2		261
-#define PCLK_GPIO1		262
-#define PCLK_GPIO2		263
-#define PCLK_GPIO3		264
-#define PCLK_GPIO4		265
-#define PCLK_SARADC		266
-#define PCLK_TIMER		267
-#define PCLK_DECOM		268
-#define PCLK_CAN		269
-#define PCLK_NPU_TSADC		270
-#define PCLK_CPU_TSADC		271
-#define PCLK_ACDCDIG		272
-#define PCLK_PDVO		273
-#define PCLK_DSIHOST		274
-#define PCLK_PDVI		275
-#define PCLK_CSIHOST		276
-#define PCLK_PDGMAC		277
-#define PCLK_GMAC		278
-#define PCLK_PDDDR		279
-#define PCLK_DDR_MON		280
-#define PCLK_PDNPU		281
-#define PCLK_NPUPVTM		282
-#define PCLK_PDTOP		283
-#define PCLK_TOPCRU		284
-#define PCLK_TOPGRF		285
-#define PCLK_CPUEMADET		286
-#define PCLK_DDRPHY		287
-#define PCLK_DSIPHY		289
-#define PCLK_CSIPHY0		290
-#define PCLK_CSIPHY1		291
-#define PCLK_USBPHY_HOST	292
-#define PCLK_USBPHY_OTG		293
-#define PCLK_OTP		294
-
-#define CLK_NR_CLKS		(PCLK_OTP + 1)
-
-/* pmu soft-reset indices */
-
-/* pmu_cru_softrst_con0 */
-#define SRST_PDPMU_NIU_P	0
-#define SRST_PMU_SGRF_P		1
-#define SRST_PMU_SGRF_REMAP_P	2
-#define SRST_I2C0_P		3
-#define SRST_I2C0		4
-#define SRST_I2C2_P		7
-#define SRST_I2C2		8
-#define SRST_UART1_P		9
-#define SRST_UART1		10
-#define SRST_PWM0_P		11
-#define SRST_PWM0		12
-#define SRST_PWM1_P		13
-#define SRST_PWM1		14
-#define SRST_DDR_FAIL_SAFE	15
-
-/* pmu_cru_softrst_con1 */
-#define SRST_GPIO0_P		17
-#define SRST_GPIO0_DB		18
-#define SRST_SPI0_P		19
-#define SRST_SPI0		20
-#define SRST_PMUGRF_P		21
-#define SRST_CHIPVEROTP_P	22
-#define SRST_PMUPVTM		24
-#define SRST_PMUPVTM_P		25
-#define SRST_PMUCRU_P		30
-
-/* soft-reset indices */
-
-/* cru_softrst_con0 */
-#define SRST_CORE0_PO		0
-#define SRST_CORE1_PO		1
-#define SRST_CORE2_PO		2
-#define SRST_CORE3_PO		3
-#define SRST_CORE0		4
-#define SRST_CORE1		5
-#define SRST_CORE2		6
-#define SRST_CORE3		7
-#define SRST_CORE0_DBG		8
-#define SRST_CORE1_DBG		9
-#define SRST_CORE2_DBG		10
-#define SRST_CORE3_DBG		11
-#define SRST_NL2		12
-#define SRST_CORE_NIU_A		13
-#define SRST_DBG_DAPLITE_P	14
-#define SRST_DAPLITE_P		15
-
-/* cru_softrst_con1 */
-#define SRST_PDBUS_NIU1_A	16
-#define SRST_PDBUS_NIU1_H	17
-#define SRST_PDBUS_NIU1_P	18
-#define SRST_PDBUS_NIU2_A	19
-#define SRST_PDBUS_NIU2_H	20
-#define SRST_PDBUS_NIU3_A	21
-#define SRST_PDBUS_NIU3_H	22
-#define SRST_PDBUS_HOLD_NIU1_A	23
-#define SRST_DBG_NIU_P		24
-#define SRST_PDCORE_NIIU_H	25
-#define SRST_MUC_NIU		26
-#define SRST_DCF_A		29
-#define SRST_DCF_P		30
-#define SRST_SYSTEM_SRAM_A	31
-
-/* cru_softrst_con2 */
-#define SRST_I2C1_P		32
-#define SRST_I2C1		33
-#define SRST_I2C3_P		34
-#define SRST_I2C3		35
-#define SRST_I2C4_P		36
-#define SRST_I2C4		37
-#define SRST_I2C5_P		38
-#define SRST_I2C5		39
-#define SRST_SPI1_P		40
-#define SRST_SPI1		41
-#define SRST_MCU_CORE		42
-#define SRST_PWM2_P		44
-#define SRST_PWM2		45
-#define SRST_SPINLOCK_A		46
-
-/* cru_softrst_con3 */
-#define SRST_UART0_P		48
-#define SRST_UART0		49
-#define SRST_UART2_P		50
-#define SRST_UART2		51
-#define SRST_UART3_P		52
-#define SRST_UART3		53
-#define SRST_UART4_P		54
-#define SRST_UART4		55
-#define SRST_UART5_P		56
-#define SRST_UART5		57
-#define SRST_WDT_P		58
-#define SRST_SARADC_P		59
-#define SRST_GRF_P		61
-#define SRST_TIMER_P		62
-#define SRST_MAILBOX_P		63
-
-/* cru_softrst_con4 */
-#define SRST_TIMER0		64
-#define SRST_TIMER1		65
-#define SRST_TIMER2		66
-#define SRST_TIMER3		67
-#define SRST_TIMER4		68
-#define SRST_TIMER5		69
-#define SRST_INTMUX_P		70
-#define SRST_GPIO1_P		72
-#define SRST_GPIO1_DB		73
-#define SRST_GPIO2_P		74
-#define SRST_GPIO2_DB		75
-#define SRST_GPIO3_P		76
-#define SRST_GPIO3_DB		77
-#define SRST_GPIO4_P		78
-#define SRST_GPIO4_DB		79
-
-/* cru_softrst_con5 */
-#define SRST_CAN_P		80
-#define SRST_CAN		81
-#define SRST_DECOM_A		85
-#define SRST_DECOM_P		86
-#define SRST_DECOM_D		87
-#define SRST_PDCRYPTO_NIU_A	88
-#define SRST_PDCRYPTO_NIU_H	89
-#define SRST_CRYPTO_A		90
-#define SRST_CRYPTO_H		91
-#define SRST_CRYPTO_CORE	92
-#define SRST_CRYPTO_PKA		93
-#define SRST_SGRF_P		95
-
-/* cru_softrst_con6 */
-#define SRST_PDAUDIO_NIU_H	96
-#define SRST_PDAUDIO_NIU_P	97
-#define SRST_I2S0_H		98
-#define SRST_I2S0_TX_M		99
-#define SRST_I2S0_RX_M		100
-#define SRST_I2S1_H		101
-#define SRST_I2S1_M		102
-#define SRST_I2S2_H		103
-#define SRST_I2S2_M		104
-#define SRST_PDM_H		105
-#define SRST_PDM_M		106
-#define SRST_AUDPWM_H		107
-#define SRST_AUDPWM		108
-#define SRST_ACDCDIG_P		109
-#define SRST_ACDCDIG		110
-
-/* cru_softrst_con7 */
-#define SRST_PDVEPU_NIU_A	112
-#define SRST_PDVEPU_NIU_H	113
-#define SRST_VENC_A		114
-#define SRST_VENC_H		115
-#define SRST_VENC_CORE		116
-#define SRST_PDVDEC_NIU_A	117
-#define SRST_PDVDEC_NIU_H	118
-#define SRST_VDEC_A		119
-#define SRST_VDEC_H		120
-#define SRST_VDEC_CORE		121
-#define SRST_VDEC_CA		122
-#define SRST_VDEC_HEVC_CA	123
-#define SRST_PDJPEG_NIU_A	124
-#define SRST_PDJPEG_NIU_H	125
-#define SRST_JPEG_A		126
-#define SRST_JPEG_H		127
-
-/* cru_softrst_con8 */
-#define SRST_PDVO_NIU_A		128
-#define SRST_PDVO_NIU_H		129
-#define SRST_PDVO_NIU_P		130
-#define SRST_RGA_A		131
-#define SRST_RGA_H		132
-#define SRST_RGA_CORE		133
-#define SRST_VOP_A		134
-#define SRST_VOP_H		135
-#define SRST_VOP_D		136
-#define SRST_TXBYTEHS_DSIHOST	137
-#define SRST_DSIHOST_P		138
-#define SRST_IEP_A		139
-#define SRST_IEP_H		140
-#define SRST_IEP_CORE		141
-#define SRST_ISP_RX_P		142
-
-/* cru_softrst_con9 */
-#define SRST_PDVI_NIU_A		144
-#define SRST_PDVI_NIU_H		145
-#define SRST_PDVI_NIU_P		146
-#define SRST_ISP		147
-#define SRST_CIF_A		148
-#define SRST_CIF_H		149
-#define SRST_CIF_D		150
-#define SRST_CIF_P		151
-#define SRST_CIF_I		152
-#define SRST_CIF_RX_P		153
-#define SRST_PDISPP_NIU_A	154
-#define SRST_PDISPP_NIU_H	155
-#define SRST_ISPP_A		156
-#define SRST_ISPP_H		157
-#define SRST_ISPP		158
-#define SRST_CSIHOST_P		159
-
-/* cru_softrst_con10 */
-#define SRST_PDPHPMID_NIU_A	160
-#define SRST_PDPHPMID_NIU_H	161
-#define SRST_PDNVM_NIU_H	163
-#define SRST_SDMMC_H		164
-#define SRST_SDIO_H		165
-#define SRST_EMMC_H		166
-#define SRST_SFC_H		167
-#define SRST_SFCXIP_H		168
-#define SRST_SFC		169
-#define SRST_NANDC_H		170
-#define SRST_NANDC		171
-#define SRST_PDSDMMC_H		173
-#define SRST_PDSDIO_H		174
-
-/* cru_softrst_con11 */
-#define SRST_PDUSB_NIU_A	176
-#define SRST_PDUSB_NIU_H	177
-#define SRST_USBHOST_H		178
-#define SRST_USBHOST_ARB_H	179
-#define SRST_USBHOST_UTMI	180
-#define SRST_USBOTG_A		181
-#define SRST_USBPHY_OTG_P	182
-#define SRST_USBPHY_HOST_P	183
-#define SRST_USBPHYPOR_OTG	184
-#define SRST_USBPHYPOR_HOST	185
-#define SRST_PDGMAC_NIU_A	188
-#define SRST_PDGMAC_NIU_P	189
-#define SRST_GMAC_A		190
-
-/* cru_softrst_con12 */
-#define SRST_DDR_DFICTL_P	193
-#define SRST_DDR_MON_P		194
-#define SRST_DDR_STANDBY_P	195
-#define SRST_DDR_GRF_P		196
-#define SRST_DDR_MSCH_P		197
-#define SRST_DDR_SPLIT_A	198
-#define SRST_DDR_MSCH		199
-#define SRST_DDR_DFICTL		202
-#define SRST_DDR_STANDBY	203
-#define SRST_NPUMCU_NIU		205
-#define SRST_DDRPHY_P		206
-#define SRST_DDRPHY		207
-
-/* cru_softrst_con13 */
-#define SRST_PDNPU_NIU_A	208
-#define SRST_PDNPU_NIU_H	209
-#define SRST_PDNPU_NIU_P	210
-#define SRST_NPU_A		211
-#define SRST_NPU_H		212
-#define SRST_NPU		213
-#define SRST_NPUPVTM_P		214
-#define SRST_NPUPVTM		215
-#define SRST_NPU_TSADC_P	216
-#define SRST_NPU_TSADC		217
-#define SRST_NPU_TSADCPHY	218
-#define SRST_CIFLITE_A		220
-#define SRST_CIFLITE_H		221
-#define SRST_CIFLITE_D		222
-#define SRST_CIFLITE_RX_P	223
-
-/* cru_softrst_con14 */
-#define SRST_TOPNIU_P		224
-#define SRST_TOPCRU_P		225
-#define SRST_TOPGRF_P		226
-#define SRST_CPUEMADET_P	227
-#define SRST_CSIPHY0_P		228
-#define SRST_CSIPHY1_P		229
-#define SRST_DSIPHY_P		230
-#define SRST_CPU_TSADC_P	232
-#define SRST_CPU_TSADC		233
-#define SRST_CPU_TSADCPHY	234
-#define SRST_CPUPVTM_P		235
-#define SRST_CPUPVTM		236
-
-#endif
--- a/include/dt-bindings/clock/rv1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
- * Author: Shawn Lin <shawn.lin@rock-chips.com>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
-
-/* pll id */
-#define PLL_APLL			0
-#define PLL_DPLL			1
-#define PLL_GPLL			2
-#define ARMCLK				3
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0			65
-#define SCLK_NANDC			67
-#define SCLK_SDMMC			68
-#define SCLK_SDIO			69
-#define SCLK_EMMC			71
-#define SCLK_UART0			72
-#define SCLK_UART1			73
-#define SCLK_UART2			74
-#define SCLK_I2S0			75
-#define SCLK_I2S1			76
-#define SCLK_I2S2			77
-#define SCLK_TIMER0			78
-#define SCLK_TIMER1			79
-#define SCLK_SFC			80
-#define SCLK_SDMMC_DRV			81
-#define SCLK_SDIO_DRV			82
-#define SCLK_EMMC_DRV			83
-#define SCLK_SDMMC_SAMPLE		84
-#define SCLK_SDIO_SAMPLE		85
-#define SCLK_EMMC_SAMPLE		86
-#define SCLK_VENC_CORE			87
-#define SCLK_HEVC_CORE			88
-#define SCLK_HEVC_CABAC			89
-#define SCLK_PWM0_PMU			90
-#define SCLK_I2C0_PMU			91
-#define SCLK_WIFI			92
-#define SCLK_CIFOUT			93
-#define SCLK_MIPI_CSI_OUT		94
-#define SCLK_CIF0			95
-#define SCLK_CIF1			96
-#define SCLK_CIF2			97
-#define SCLK_CIF3			98
-#define SCLK_DSP			99
-#define SCLK_DSP_IOP			100
-#define SCLK_DSP_EPP			101
-#define SCLK_DSP_EDP			102
-#define SCLK_DSP_EDAP			103
-#define SCLK_CVBS_HOST			104
-#define SCLK_HDMI_SFR			105
-#define SCLK_HDMI_CEC			106
-#define SCLK_CRYPTO			107
-#define SCLK_SPI			108
-#define SCLK_SARADC			109
-#define SCLK_TSADC			110
-#define SCLK_MAC_PRE			111
-#define SCLK_MAC			112
-#define SCLK_MAC_RX			113
-#define SCLK_MAC_REF			114
-#define SCLK_MAC_REFOUT			115
-#define SCLK_DSP_PFM			116
-#define SCLK_RGA			117
-#define SCLK_I2C1			118
-#define SCLK_I2C2			119
-#define SCLK_I2C3			120
-#define SCLK_PWM			121
-#define SCLK_ISP			122
-#define SCLK_USBPHY			123
-#define SCLK_I2S0_SRC			124
-#define SCLK_I2S1_SRC			125
-#define SCLK_I2S2_SRC			126
-#define SCLK_UART0_SRC			127
-#define SCLK_UART1_SRC			128
-#define SCLK_UART2_SRC			129
-#define SCLK_MAC_TX			130
-#define SCLK_MACREF			131
-#define SCLK_MACREF_OUT			132
-
-#define DCLK_VOP_SRC			185
-#define DCLK_HDMIPHY			186
-#define DCLK_VOP			187
-
-/* aclk gates */
-#define ACLK_DMAC			192
-#define ACLK_PRE			193
-#define ACLK_CORE			194
-#define ACLK_ENMCORE			195
-#define ACLK_RKVENC			196
-#define ACLK_RKVDEC			197
-#define ACLK_VPU			198
-#define ACLK_CIF0			199
-#define ACLK_VIO0			200
-#define ACLK_VIO1			201
-#define ACLK_VOP			202
-#define ACLK_IEP			203
-#define ACLK_RGA			204
-#define ACLK_ISP			205
-#define ACLK_CIF1			206
-#define ACLK_CIF2			207
-#define ACLK_CIF3			208
-#define ACLK_PERI			209
-#define ACLK_GMAC			210
-
-/* pclk gates */
-#define PCLK_GPIO1			256
-#define PCLK_GPIO2			257
-#define PCLK_GPIO3			258
-#define PCLK_GRF			259
-#define PCLK_I2C1			260
-#define PCLK_I2C2			261
-#define PCLK_I2C3			262
-#define PCLK_SPI			263
-#define PCLK_SFC			264
-#define PCLK_UART0			265
-#define PCLK_UART1			266
-#define PCLK_UART2			267
-#define PCLK_TSADC			268
-#define PCLK_PWM			269
-#define PCLK_TIMER			270
-#define PCLK_PERI			271
-#define PCLK_GPIO0_PMU			272
-#define PCLK_I2C0_PMU			273
-#define PCLK_PWM0_PMU			274
-#define PCLK_ISP			275
-#define PCLK_VIO			276
-#define PCLK_MIPI_DSI			277
-#define PCLK_HDMI_CTRL			278
-#define PCLK_SARADC			279
-#define PCLK_DSP_CFG			280
-#define PCLK_BUS			281
-#define PCLK_EFUSE0			282
-#define PCLK_EFUSE1			283
-#define PCLK_WDT			284
-#define PCLK_GMAC			285
-
-/* hclk gates */
-#define HCLK_I2S0_8CH			320
-#define HCLK_I2S1_2CH			321
-#define HCLK_I2S2_2CH			322
-#define HCLK_NANDC			323
-#define HCLK_SDMMC			324
-#define HCLK_SDIO			325
-#define HCLK_EMMC			326
-#define HCLK_PERI			327
-#define HCLK_SFC			328
-#define HCLK_RKVENC			329
-#define HCLK_RKVDEC			330
-#define HCLK_CIF0			331
-#define HCLK_VIO			332
-#define HCLK_VOP			333
-#define HCLK_IEP			334
-#define HCLK_RGA			335
-#define HCLK_ISP			336
-#define HCLK_CRYPTO_MST			337
-#define HCLK_CRYPTO_SLV			338
-#define HCLK_HOST0			339
-#define HCLK_OTG			340
-#define HCLK_CIF1			341
-#define HCLK_CIF2			342
-#define HCLK_CIF3			343
-#define HCLK_BUS			344
-#define HCLK_VPU			345
-
-#define CLK_NR_CLKS			(HCLK_VPU + 1)
-
-/* reset id */
-#define SRST_CORE_PO_AD			0
-#define SRST_CORE_AD			1
-#define SRST_L2_AD			2
-#define SRST_CPU_NIU_AD			3
-#define SRST_CORE_PO			4
-#define SRST_CORE			5
-#define SRST_L2				6
-#define SRST_CORE_DBG			8
-#define PRST_DBG			9
-#define RST_DAP				10
-#define PRST_DBG_NIU			11
-#define ARST_STRC_SYS_AD		15
-
-#define SRST_DDRPHY_CLKDIV		16
-#define SRST_DDRPHY			17
-#define PRST_DDRPHY			18
-#define PRST_HDMIPHY			19
-#define PRST_VDACPHY			20
-#define PRST_VADCPHY			21
-#define PRST_MIPI_CSI_PHY		22
-#define PRST_MIPI_DSI_PHY		23
-#define PRST_ACODEC			24
-#define ARST_BUS_NIU			25
-#define PRST_TOP_NIU			26
-#define ARST_INTMEM			27
-#define HRST_ROM			28
-#define ARST_DMAC			29
-#define SRST_MSCH_NIU			30
-#define PRST_MSCH_NIU			31
-
-#define PRST_DDRUPCTL			32
-#define NRST_DDRUPCTL			33
-#define PRST_DDRMON			34
-#define HRST_I2S0_8CH			35
-#define MRST_I2S0_8CH			36
-#define HRST_I2S1_2CH			37
-#define MRST_IS21_2CH			38
-#define HRST_I2S2_2CH			39
-#define MRST_I2S2_2CH			40
-#define HRST_CRYPTO			41
-#define SRST_CRYPTO			42
-#define PRST_SPI			43
-#define SRST_SPI			44
-#define PRST_UART0			45
-#define PRST_UART1			46
-#define PRST_UART2			47
-
-#define SRST_UART0			48
-#define SRST_UART1			49
-#define SRST_UART2			50
-#define PRST_I2C1			51
-#define PRST_I2C2			52
-#define PRST_I2C3			53
-#define SRST_I2C1			54
-#define SRST_I2C2			55
-#define SRST_I2C3			56
-#define PRST_PWM1			58
-#define SRST_PWM1			60
-#define PRST_WDT			61
-#define PRST_GPIO1			62
-#define PRST_GPIO2			63
-
-#define PRST_GPIO3			64
-#define PRST_GRF			65
-#define PRST_EFUSE			66
-#define PRST_EFUSE512			67
-#define PRST_TIMER0			68
-#define SRST_TIMER0			69
-#define SRST_TIMER1			70
-#define PRST_TSADC			71
-#define SRST_TSADC			72
-#define PRST_SARADC			73
-#define SRST_SARADC			74
-#define HRST_SYSBUS			75
-#define PRST_USBGRF			76
-
-#define ARST_PERIPH_NIU			80
-#define HRST_PERIPH_NIU			81
-#define PRST_PERIPH_NIU			82
-#define HRST_PERIPH			83
-#define HRST_SDMMC			84
-#define HRST_SDIO			85
-#define HRST_EMMC			86
-#define HRST_NANDC			87
-#define NRST_NANDC			88
-#define HRST_SFC			89
-#define SRST_SFC			90
-#define ARST_GMAC			91
-#define HRST_OTG			92
-#define SRST_OTG			93
-#define SRST_OTG_ADP			94
-#define HRST_HOST0			95
-
-#define HRST_HOST0_AUX			96
-#define HRST_HOST0_ARB			97
-#define SRST_HOST0_EHCIPHY		98
-#define SRST_HOST0_UTMI			99
-#define SRST_USBPOR			100
-#define SRST_UTMI0			101
-#define SRST_UTMI1			102
-
-#define ARST_VIO0_NIU			102
-#define ARST_VIO1_NIU			103
-#define HRST_VIO_NIU			104
-#define PRST_VIO_NIU			105
-#define ARST_VOP			106
-#define HRST_VOP			107
-#define DRST_VOP			108
-#define ARST_IEP			109
-#define HRST_IEP			110
-#define ARST_RGA			111
-#define HRST_RGA			112
-#define SRST_RGA			113
-#define PRST_CVBS			114
-#define PRST_HDMI			115
-#define SRST_HDMI			116
-#define PRST_MIPI_DSI			117
-
-#define ARST_ISP_NIU			118
-#define HRST_ISP_NIU			119
-#define HRST_ISP			120
-#define SRST_ISP			121
-#define ARST_VIP0			122
-#define HRST_VIP0			123
-#define PRST_VIP0			124
-#define ARST_VIP1			125
-#define HRST_VIP1			126
-#define PRST_VIP1			127
-#define ARST_VIP2			128
-#define HRST_VIP2			129
-#define PRST_VIP2			120
-#define ARST_VIP3			121
-#define HRST_VIP3			122
-#define PRST_VIP4			123
-
-#define PRST_CIF1TO4			124
-#define SRST_CVBS_CLK			125
-#define HRST_CVBS			126
-
-#define ARST_VPU_NIU			140
-#define HRST_VPU_NIU			141
-#define ARST_VPU			142
-#define HRST_VPU			143
-#define ARST_RKVDEC_NIU			144
-#define HRST_RKVDEC_NIU			145
-#define ARST_RKVDEC			146
-#define HRST_RKVDEC			147
-#define SRST_RKVDEC_CABAC		148
-#define SRST_RKVDEC_CORE		149
-#define ARST_RKVENC_NIU			150
-#define HRST_RKVENC_NIU			151
-#define ARST_RKVENC			152
-#define HRST_RKVENC			153
-#define SRST_RKVENC_CORE		154
-
-#define SRST_DSP_CORE			156
-#define SRST_DSP_SYS			157
-#define SRST_DSP_GLOBAL			158
-#define SRST_DSP_OECM			159
-#define PRST_DSP_IOP_NIU		160
-#define ARST_DSP_EPP_NIU		161
-#define ARST_DSP_EDP_NIU		162
-#define PRST_DSP_DBG_NIU		163
-#define PRST_DSP_CFG_NIU		164
-#define PRST_DSP_GRF			165
-#define PRST_DSP_MAILBOX		166
-#define PRST_DSP_INTC			167
-#define PRST_DSP_PFM_MON		169
-#define SRST_DSP_PFM_MON		170
-#define ARST_DSP_EDAP_NIU		171
-
-#define SRST_PMU			172
-#define SRST_PMU_I2C0			173
-#define PRST_PMU_I2C0			174
-#define PRST_PMU_GPIO0			175
-#define PRST_PMU_INTMEM			176
-#define PRST_PMU_PWM0			177
-#define SRST_PMU_PWM0			178
-#define PRST_PMU_GRF			179
-#define SRST_PMU_NIU			180
-#define SRST_PMU_PVTM			181
-#define ARST_DSP_EDP_PERF		184
-#define ARST_DSP_EPP_PERF		185
-
-#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
--- a/include/dt-bindings/power/rockchip,rv1126-power.h
+++ b/include/dt-bindings/power/rockchip,rv1126-power.h
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
-#define __DT_BINDINGS_POWER_RV1126_POWER_H__
-
-/* VD_CORE */
-#define RV1126_PD_CPU_0		0
-#define RV1126_PD_CPU_1		1
-#define RV1126_PD_CPU_2		2
-#define RV1126_PD_CPU_3		3
-#define RV1126_PD_CORE_ALIVE	4
-
-/* VD_PMU */
-#define RV1126_PD_PMU		5
-#define RV1126_PD_PMU_ALIVE	6
-
-/* VD_NPU */
-#define RV1126_PD_NPU		7
-
-/* VD_VEPU */
-#define RV1126_PD_VEPU		8
-
-/* VD_LOGIC */
-#define RV1126_PD_VI		9
-#define RV1126_PD_VO		10
-#define RV1126_PD_ISPP		11
-#define RV1126_PD_VDPU		12
-#define RV1126_PD_CRYPTO	13
-#define RV1126_PD_DDR		14
-#define RV1126_PD_NVM		15
-#define RV1126_PD_SDIO		16
-#define RV1126_PD_USB		17
-#define RV1126_PD_LOGIC_ALIVE	18
-
-#endif