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imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun

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To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2023-01-31 16:42:32 +08:00
committed by Stefano Babic
parent 74a39c15c3
commit 6c01ca0a53
2 changed files with 4 additions and 4 deletions
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4
board/freescale/imx8ulp_evk/lpddr4_timing.c
View File

@@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
{ 0x2e0604d4, 0x102 }, /* 309 */
{ 0x2e0604d8, 0x404 }, /* 310 */
{ 0x2e0604d4, 0x01000102 }, /* 309 */
{ 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */

4
board/freescale/imx8ulp_evk/lpddr4_timing_266.c
View File

@@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
{ 0x2e0604d4, 0x102 }, /* 309 */
{ 0x2e0604d8, 0x404 }, /* 310 */
{ 0x2e0604d4, 0x01000102 }, /* 309 */
{ 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */