Merge tag 'u-boot-rockchip-20250423' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/25909 Please pull the updates for rockchip platform: - New SoC support: RK3528, RK3576 - New Board support: rk3528 Radxa E20C, rk3576 Firefly ROC-RK3576-PC; - Add generic board for rk3288 and rk3399; - rng driver binding update; - misc updates on board level or header files;
2026-06-02 09:46:37 +03:00 · 2025-04-23 11:34:53 -06:00
parent 873bca77a3 1f07d25730
commit 6e325df489
107 changed files with 12440 additions and 208 deletions
--- a/arch/arm/dts/px30-evb-u-boot.dtsi
+++ b/arch/arm/dts/px30-evb-u-boot.dtsi
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * (C) Copyright 2020 Rockchip Electronics Co., Ltd
- */
-
-#include "px30-u-boot.dtsi"
-
-&rng {
-	status = "okay";
-};
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -24,7 +24,6 @@
 	rng: rng@ff0b0000 {
 		compatible = "rockchip,cryptov2-rng";
 		reg = <0x0 0xff0b0000 0x0 0x4000>;
-		status = "disabled";
 	};
 };

--- a/arch/arm/dts/rk3328-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-generic-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3328-u-boot.dtsi"
+
+&gpio0 {
+	/delete-property/ bootph-pre-ram;
+};
+
+&pcfg_pull_down_4ma {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&spi0 {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&spi0m2_clk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&spi0m2_cs0 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&spi0m2_rx {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&spi0m2_tx {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
--- a/arch/arm/dts/rk3328-generic.dts
+++ b/arch/arm/dts/rk3328-generic.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3328 with eMMC, SD-card, SPI flash and USB OTG enabled
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+	model = "Generic RK3328";
+	compatible = "rockchip,rk3328";
+
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&emmc {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+	status = "okay";
+};
+
+&sdmmc0m1_pin {
+	rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down_4ma>;
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	no-mmc;
+	no-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4 &sdmmc0m1_pin>;
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+};
+
+&u2phy {
+	status = "okay";
+};
+
+&u2phy_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb20_otg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
--- a/arch/arm/dts/rk3399-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-generic-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3399-u-boot.dtsi"
+
+&spi1 {
+	flash@0 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
--- a/arch/arm/dts/rk3399-generic.dts
+++ b/arch/arm/dts/rk3399-generic.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3399 with eMMC, SD-card, SPI flash and USB OTG enabled
+ */
+
+/dts-v1/;
+#include "rk3399.dtsi"
+
+/ {
+	model = "Generic RK3399";
+	compatible = "rockchip,rk3399";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	max-frequency = <150000000>;
+	mmc-hs200-1_8v;
+	mmc-ddr-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-mmc;
+	no-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+	phys = <&u2phy0_otg>;
+	phy-names = "usb2-phy";
+	status = "okay";
+};
--- a/arch/arm/dts/rk3528-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	no-mmc;
+	no-sdio;
+	status = "okay";
+};
--- a/arch/arm/dts/rk3528-generic.dts
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3528 with eMMC enabled
+ */
+
+/dts-v1/;
+#include "rk3528.dtsi"
+
+/ {
+	model = "Generic RK3528";
+	compatible = "rockchip,rk3528";
+
+	chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	no-sd;
+	no-sdio;
+	non-removable;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0m0_xfer>;
+	status = "okay";
+};
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	vmmc-supply = <&vcc_3v3>;
+	status = "okay";
+};
--- a/arch/arm/dts/rk3528-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+	};
+
+	dmc {
+		compatible = "rockchip,rk3528-dmc";
+		bootph-all;
+	};
+
+	soc {
+		rng: rng@ffc50000 {
+			compatible = "rockchip,rkrng";
+			reg = <0x0 0xffc50000 0x0 0x200>;
+		};
+
+		otp: nvmem@ffce0000 {
+			compatible = "rockchip,rk3528-otp";
+			reg = <0x0 0xffce0000 0x0 0x4000>;
+		};
+
+		sdmmc: mmc@ffc30000 {
+			compatible = "rockchip,rk3528-dw-mshc",
+				     "rockchip,rk3288-dw-mshc";
+			reg = <0x0 0xffc30000 0x0 0x4000>;
+			clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+			clock-names = "biu", "ciu";
+			fifo-depth = <0x100>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <150000000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+				    <&sdmmc_det>;
+			resets = <&cru SRST_H_SDMMC0>;
+			reset-names = "reset";
+			rockchip,default-sample-phase = <90>;
+			status = "disabled";
+		};
+	};
+};
+
+&cru {
+	bootph-all;
+};
+
+&emmc_bus8 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_clk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_cmd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_strb {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gmac0_clk {
+	bootph-all;
+};
+
+&ioc_grf {
+	bootph-all;
+};
+
+&otp {
+	bootph-some-ram;
+};
+
+&pcfg_pull_none {
+	bootph-all;
+};
+
+&pcfg_pull_up {
+	bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl {
+	bootph-all;
+};
+
+&sdhci {
+	bootph-pre-ram;
+	bootph-some-ram;
+	u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+	bootph-pre-ram;
+	bootph-some-ram;
+	u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc_clk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc_cmd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc_det {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&uart0 {
+	bootph-all;
+	clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+	bootph-pre-sram;
+	bootph-pre-ram;
+};
+
+&xin24m {
+	bootph-all;
+};
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -21,11 +21,6 @@
 		bootph-all;
 	};

-	rng: rng@fe388000 {
-		compatible = "rockchip,cryptov2-rng";
-		reg = <0x0 0xfe388000 0x0 0x2000>;
-	};
-
 	otp: nvmem@fe38c000 {
 		compatible = "rockchip,rk3568-otp";
 		reg = <0x0 0xfe38c000 0x0 0x4000>;
@@ -121,6 +116,10 @@
 	bootph-all;
 };

+&rng {
+	status = "okay";
+};
+
 &sdhci {
 	bootph-pre-ram;
 	bootph-some-ram;
--- a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net>
+ *
+ */
+
+#include "rk3576-u-boot.dtsi"
+
+&sdhci {
+	cap-mmc-highspeed;
+};
--- a/arch/arm/dts/rk3576-u-boot.dtsi
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * (C) Copyright 2025 Rockchip Electronics Co., Ltd
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+	};
+
+	dmc {
+		compatible = "rockchip,rk3576-dmc";
+		bootph-all;
+	};
+};
+
+&cru {
+	bootph-all;
+};
+
+&emmc_bus8 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_clk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_cmd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_rstnout {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&emmc_strb {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&ioc_grf {
+	bootph-all;
+};
+
+&pcfg_pull_none {
+	bootph-all;
+};
+
+&pcfg_pull_up {
+	bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pcfg_pull_up_drv_level_3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl {
+	bootph-all;
+};
+
+&pmu1_grf {
+	bootph-all;
+};
+
+&sdhci {
+	bootph-pre-ram;
+	bootph-some-ram;
+	u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+	bootph-pre-ram;
+	bootph-some-ram;
+	u-boot,spl-fifo-mode;
+};
+
+&sdmmc0_bus4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc0_clk {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc0_cmd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc0_det {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sdmmc0_pwren {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&sys_grf {
+	bootph-all;
+};
+
+&uart0 {
+	bootph-all;
+	clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+	bootph-pre-sram;
+	bootph-pre-ram;
+};
+
+&xin24m {
+	bootph-all;
+};
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -18,11 +18,6 @@
 		compatible = "rockchip,rk3588-dmc";
 		bootph-all;
 	};
-
-	rng: rng@fe378000 {
-		compatible = "rockchip,trngv1";
-		reg = <0x0 0xfe378000 0x0 0x200>;
-	};
 };

 #ifdef CONFIG_ROCKCHIP_SPI_IMAGE
--- a/arch/arm/include/asm/arch-rk3528/boot0.h
+++ b/arch/arm/include/asm/arch-rk3528/boot0.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- a/arch/arm/include/asm/arch-rk3528/gpio.h
+++ b/arch/arm/include/asm/arch-rk3528/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- a/arch/arm/include/asm/arch-rk3576/boot0.h
+++ b/arch/arm/include/asm/arch-rk3576/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- a/arch/arm/include/asm/arch-rk3576/gpio.h
+++ b/arch/arm/include/asm/arch-rk3576/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -15,6 +15,13 @@ struct udevice;
 #define RKCLK_PLL_MODE_NORMAL		1
 #define RKCLK_PLL_MODE_DEEP		2

+/*
+ * PLL flags
+ */
+#define ROCKCHIP_PLL_SYNC_RATE		BIT(0)
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
+#define ROCKCHIP_PLL_FIXED_MODE		BIT(1)
+
 enum {
 	ROCKCHIP_SYSCON_NOC,
 	ROCKCHIP_SYSCON_GRF,
@@ -207,6 +214,26 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
 */
 int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
 			    u32 reg_offset, u32 reg_number);
+/*
+ * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
+ *			     using dedicated RK3528 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+/*
+ * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device
+ *			     using dedicated RK3576 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
 /*
 * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
 *			     using dedicated RK3588 lookup table
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3528_H
+#define _ASM_ARCH_CRU_RK3528_H
+
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+
+#define CPU_PVTPLL_HZ	(1200 * MHz)
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(1188 * MHz)
+#define CPLL_HZ		(996 * MHz)
+#define PPLL_HZ		(1000 * MHz)
+
+/* RK3528 pll id */
+enum rk3528_pll_id {
+	APLL,
+	CPLL,
+	GPLL,
+	PPLL,
+	DPLL,
+	PLL_COUNT,
+};
+
+struct rk3528_clk_priv {
+	struct rk3528_cru *cru;
+	unsigned long ppll_hz;
+	unsigned long gpll_hz;
+	unsigned long cpll_hz;
+	unsigned long armclk_hz;
+	unsigned long armclk_enter_hz;
+	unsigned long armclk_init_hz;
+	bool sync_kernel;
+};
+
+struct rk3528_pll {
+	unsigned int con0;
+	unsigned int con1;
+	unsigned int con2;
+	unsigned int con3;
+	unsigned int con4;
+	unsigned int reserved0[3];
+};
+
+#define RK3528_CRU_BASE			((struct rk3528_cru *)0xff4a0000)
+
+struct rk3528_cru {
+	unsigned int apll_con[5];
+	unsigned int reserved0014[3];
+	unsigned int cpll_con[5];
+	unsigned int reserved0034[11];
+	unsigned int gpll_con[5];
+	unsigned int reserved0074[51 + 32];
+	unsigned int reserved01c0[48];
+	unsigned int mode_con[1];
+	unsigned int reserved0284[31];
+	unsigned int clksel_con[91];
+	unsigned int reserved046c[229];
+	unsigned int gate_con[46];
+	unsigned int reserved08b8[82];
+	unsigned int softrst_con[47];
+	unsigned int reserved0abc[81];
+	unsigned int glb_cnt_th;
+	unsigned int glb_rst_st;
+	unsigned int glb_srst_fst;
+	unsigned int glb_srst_snd;
+	unsigned int glb_rst_con;
+	unsigned int reserved0c14[6];
+	unsigned int corewfi_con;
+	unsigned int reserved0c30[15604];
+
+	/* pmucru */
+	unsigned int reserved10000[192];
+	unsigned int pmuclksel_con[3];
+	unsigned int reserved1030c[317];
+	unsigned int pmugate_con[3];
+	unsigned int reserved1080c[125];
+	unsigned int pmusoftrst_con[3];
+	unsigned int reserved10a08[7550 + 8191];
+
+	/* pciecru */
+	unsigned int reserved20000[32];
+	unsigned int ppll_con[5];
+	unsigned int reserved20094[155];
+	unsigned int pcieclksel_con[2];
+	unsigned int reserved20308[318];
+	unsigned int pciegate_con;
+};
+
+check_member(rk3528_cru, pciegate_con, 0x20800);
+
+struct pll_rate_table {
+	unsigned long rate;
+	unsigned int fbdiv;
+	unsigned int postdiv1;
+	unsigned int refdiv;
+	unsigned int postdiv2;
+	unsigned int dsmpd;
+	unsigned int frac;
+};
+
+#define RK3528_PMU_CRU_BASE			0x10000
+#define RK3528_PCIE_CRU_BASE			0x20000
+#define RK3528_DDRPHY_CRU_BASE			0x28000
+#define RK3528_PLL_CON(x)			((x) * 0x4)
+#define RK3528_PCIE_PLL_CON(x)			((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x)		((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON				0x280
+#define RK3528_CLKSEL_CON(x)			((x) * 0x4 + 0x300)
+#define RK3528_PMU_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON			(0x280 + RK3528_DDRPHY_CRU_BASE)
+
+#define RK3528_DIV_ACLK_M_CORE_SHIFT		11
+#define RK3528_DIV_ACLK_M_CORE_MASK		(0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
+#define RK3528_DIV_PCLK_DBG_SHIFT		1
+#define RK3528_DIV_PCLK_DBG_MASK		(0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
+
+enum {
+	/* CRU_CLKSEL_CON00 */
+	CLK_MATRIX_50M_SRC_DIV_SHIFT		= 2,
+	CLK_MATRIX_50M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
+	CLK_MATRIX_100M_SRC_DIV_SHIFT		= 7,
+	CLK_MATRIX_100M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON01 */
+	CLK_MATRIX_150M_SRC_DIV_SHIFT		= 0,
+	CLK_MATRIX_150M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
+	CLK_MATRIX_200M_SRC_DIV_SHIFT		= 5,
+	CLK_MATRIX_200M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
+	CLK_MATRIX_250M_SRC_DIV_SHIFT		= 10,
+	CLK_MATRIX_250M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
+	CLK_MATRIX_250M_SRC_SEL_SHIFT		= 15,
+	CLK_MATRIX_250M_SRC_SEL_MASK		= 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON02 */
+	CLK_MATRIX_300M_SRC_DIV_SHIFT		= 0,
+	CLK_MATRIX_300M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
+	CLK_MATRIX_339M_SRC_DIV_SHIFT		= 5,
+	CLK_MATRIX_339M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
+	CLK_MATRIX_400M_SRC_DIV_SHIFT		= 10,
+	CLK_MATRIX_400M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON03 */
+	CLK_MATRIX_500M_SRC_DIV_SHIFT		= 6,
+	CLK_MATRIX_500M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
+	CLK_MATRIX_500M_SRC_SEL_SHIFT		= 11,
+	CLK_MATRIX_500M_SRC_SEL_MASK		= 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON04 */
+	CLK_MATRIX_600M_SRC_DIV_SHIFT		= 0,
+	CLK_MATRIX_600M_SRC_DIV_MASK		= 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
+	CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX	= 0U,
+	CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX	= 1U,
+	CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX	= 0U,
+	CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX	= 1U,
+
+	/* PMUCRU_CLKSEL_CON00 */
+	CLK_I2C2_SEL_SHIFT			= 0,
+	CLK_I2C2_SEL_MASK			= 0x3 << CLK_I2C2_SEL_SHIFT,
+
+	/* PCIE_CRU_CLKSEL_CON01 */
+	PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT	= 7,
+	PCIE_CLK_MATRIX_50M_SRC_DIV_MASK	= 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
+	PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT	= 11,
+	PCIE_CLK_MATRIX_100M_SRC_DIV_MASK	= 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON32 */
+	DCLK_VOP_SRC0_SEL_SHIFT			= 10,
+	DCLK_VOP_SRC0_SEL_MASK			= 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
+	DCLK_VOP_SRC0_DIV_SHIFT			= 2,
+	DCLK_VOP_SRC0_DIV_MASK			= 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON33 */
+	DCLK_VOP_SRC1_SEL_SHIFT			= 8,
+	DCLK_VOP_SRC1_SEL_MASK			= 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
+	DCLK_VOP_SRC1_DIV_SHIFT			= 0,
+	DCLK_VOP_SRC1_DIV_MASK			= 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON43 */
+	CLK_CORE_CRYPTO_SEL_SHIFT		= 14,
+	CLK_CORE_CRYPTO_SEL_MASK		= 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+	ACLK_BUS_VOPGL_ROOT_DIV_SHIFT		= 0U,
+	ACLK_BUS_VOPGL_ROOT_DIV_MASK		= 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON44 */
+	CLK_PWM0_SEL_SHIFT			= 6,
+	CLK_PWM0_SEL_MASK			= 0x3 << CLK_PWM0_SEL_SHIFT,
+	CLK_PWM1_SEL_SHIFT			= 8,
+	CLK_PWM1_SEL_MASK			= 0x3 << CLK_PWM1_SEL_SHIFT,
+	CLK_PWM0_SEL_CLK_MATRIX_100M_SRC	= 0U,
+	CLK_PWM0_SEL_CLK_MATRIX_50M_SRC		= 1U,
+	CLK_PWM0_SEL_XIN_OSC0_FUNC		= 2U,
+	CLK_PWM1_SEL_CLK_MATRIX_100M_SRC	= 0U,
+	CLK_PWM1_SEL_CLK_MATRIX_50M_SRC		= 1U,
+	CLK_PWM1_SEL_XIN_OSC0_FUNC		= 2U,
+	CLK_PKA_CRYPTO_SEL_SHIFT		= 0,
+	CLK_PKA_CRYPTO_SEL_MASK			= 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+	CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC	= 0U,
+	CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC	= 1U,
+	CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC	= 2U,
+	CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC	= 3U,
+	CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC	= 0U,
+	CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC	= 1U,
+	CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC	= 2U,
+	CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC	= 3U,
+
+	/* CRU_CLKSEL_CON60 */
+	CLK_MATRIX_25M_SRC_DIV_SHIFT		= 2,
+	CLK_MATRIX_25M_SRC_DIV_MASK		= 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
+	CLK_MATRIX_125M_SRC_DIV_SHIFT		= 10,
+	CLK_MATRIX_125M_SRC_DIV_MASK		= 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON61 */
+	SCLK_SFC_DIV_SHIFT			= 6,
+	SCLK_SFC_DIV_MASK			= 0x3F << SCLK_SFC_DIV_SHIFT,
+	SCLK_SFC_SEL_SHIFT			= 12,
+	SCLK_SFC_SEL_MASK			= 0x3 << SCLK_SFC_SEL_SHIFT,
+	SCLK_SFC_SEL_CLK_GPLL_MUX		= 0U,
+	SCLK_SFC_SEL_CLK_CPLL_MUX		= 1U,
+	SCLK_SFC_SEL_XIN_OSC0_FUNC		= 2U,
+
+	/* CRU_CLKSEL_CON62 */
+	CCLK_SRC_EMMC_DIV_SHIFT			= 0,
+	CCLK_SRC_EMMC_DIV_MASK			= 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
+	CCLK_SRC_EMMC_SEL_SHIFT			= 6,
+	CCLK_SRC_EMMC_SEL_MASK			= 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
+	BCLK_EMMC_SEL_SHIFT			= 8,
+	BCLK_EMMC_SEL_MASK			= 0x3 << BCLK_EMMC_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON63 */
+	CLK_I2C3_SEL_SHIFT			= 12,
+	CLK_I2C3_SEL_MASK			= 0x3 << CLK_I2C3_SEL_SHIFT,
+	CLK_I2C5_SEL_SHIFT			= 14,
+	CLK_I2C5_SEL_MASK			= 0x3 << CLK_I2C5_SEL_SHIFT,
+	CLK_SPI1_SEL_SHIFT			= 10,
+	CLK_SPI1_SEL_MASK			= 0x3 << CLK_SPI1_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON64 */
+	CLK_I2C6_SEL_SHIFT			= 0,
+	CLK_I2C6_SEL_MASK			= 0x3 << CLK_I2C6_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON74 */
+	CLK_SARADC_DIV_SHIFT			= 0,
+	CLK_SARADC_DIV_MASK			= 0x7 << CLK_SARADC_DIV_SHIFT,
+	CLK_TSADC_DIV_SHIFT			= 3,
+	CLK_TSADC_DIV_MASK			= 0x1F << CLK_TSADC_DIV_SHIFT,
+	CLK_TSADC_TSEN_DIV_SHIFT		= 8,
+	CLK_TSADC_TSEN_DIV_MASK			= 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
+
+	/* CRU_CLKSEL_CON79 */
+	CLK_I2C1_SEL_SHIFT			= 9,
+	CLK_I2C1_SEL_MASK			= 0x3 << CLK_I2C1_SEL_SHIFT,
+	CLK_I2C0_SEL_SHIFT			= 11,
+	CLK_I2C0_SEL_MASK			= 0x3 << CLK_I2C0_SEL_SHIFT,
+	CLK_SPI0_SEL_SHIFT			= 13,
+	CLK_SPI0_SEL_MASK			= 0x3 << CLK_SPI0_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON83 */
+	ACLK_VOP_ROOT_DIV_SHIFT			= 12,
+	ACLK_VOP_ROOT_DIV_MASK			= 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
+	ACLK_VOP_ROOT_SEL_SHIFT			= 15,
+	ACLK_VOP_ROOT_SEL_MASK			= 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
+
+	/* CRU_CLKSEL_CON84 */
+	DCLK_VOP0_SEL_SHIFT			= 0,
+	DCLK_VOP0_SEL_MASK			= 0x1 << DCLK_VOP0_SEL_SHIFT,
+	DCLK_VOP_SRC_SEL_CLK_GPLL_MUX		= 0U,
+	DCLK_VOP_SRC_SEL_CLK_CPLL_MUX		= 1U,
+	ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX		= 0U,
+	ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX		= 1U,
+	DCLK_VOP0_SEL_DCLK_VOP_SRC0		= 0U,
+	DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO	= 1U,
+
+	/* CRU_CLKSEL_CON85 */
+	CLK_I2C4_SEL_SHIFT			= 13,
+	CLK_I2C4_SEL_MASK			= 0x3 << CLK_I2C4_SEL_SHIFT,
+	CLK_I2C7_SEL_SHIFT			= 0,
+	CLK_I2C7_SEL_MASK			= 0x3 << CLK_I2C7_SEL_SHIFT,
+	CLK_I2C3_SEL_CLK_MATRIX_200M_SRC	= 0U,
+	CLK_I2C3_SEL_CLK_MATRIX_100M_SRC	= 1U,
+	CLK_I2C3_SEL_CLK_MATRIX_50M_SRC		= 2U,
+	CLK_I2C3_SEL_XIN_OSC0_FUNC		= 3U,
+	CLK_SPI1_SEL_CLK_MATRIX_200M_SRC	= 0U,
+	CLK_SPI1_SEL_CLK_MATRIX_100M_SRC	= 1U,
+	CLK_SPI1_SEL_CLK_MATRIX_50M_SRC		= 2U,
+	CLK_SPI1_SEL_XIN_OSC0_FUNC		= 3U,
+	CCLK_SRC_SDMMC0_DIV_SHIFT		= 0,
+	CCLK_SRC_SDMMC0_DIV_MASK		= 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
+	CCLK_SRC_SDMMC0_SEL_SHIFT		= 6,
+	CCLK_SRC_SDMMC0_SEL_MASK		= 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
+	CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX		= 0U,
+	CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX		= 1U,
+	CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC		= 2U,
+	BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC	= 0U,
+	BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC	= 1U,
+	BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC	= 2U,
+	BCLK_EMMC_SEL_XIN_OSC0_FUNC		= 3U,
+	CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX	= 0U,
+	CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX	= 1U,
+	CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC	= 2U,
+
+	/* CRU_CLKSEL_CON04 */
+	CLK_UART0_SRC_DIV_SHIFT			= 5,
+	CLK_UART0_SRC_DIV_MASK			= 0x1F << CLK_UART0_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON05 */
+	CLK_UART0_FRAC_DIV_SHIFT		= 0,
+	CLK_UART0_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON06 */
+	SCLK_UART0_SRC_SEL_SHIFT		= 0,
+	SCLK_UART0_SRC_SEL_MASK			= 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
+	CLK_UART1_SRC_DIV_SHIFT			= 2,
+	CLK_UART1_SRC_DIV_MASK			= 0x1F << CLK_UART1_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON07 */
+	CLK_UART1_FRAC_DIV_SHIFT		= 0,
+	CLK_UART1_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON08 */
+	SCLK_UART1_SRC_SEL_SHIFT		= 0,
+	SCLK_UART1_SRC_SEL_MASK			= 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
+	CLK_UART2_SRC_DIV_SHIFT			= 2,
+	CLK_UART2_SRC_DIV_MASK			= 0x1F << CLK_UART2_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON09 */
+	CLK_UART2_FRAC_DIV_SHIFT		= 0,
+	CLK_UART2_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON10 */
+	SCLK_UART2_SRC_SEL_SHIFT		= 0,
+	SCLK_UART2_SRC_SEL_MASK			= 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
+	CLK_UART3_SRC_DIV_SHIFT			= 2,
+	CLK_UART3_SRC_DIV_MASK			= 0x1F << CLK_UART3_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON11 */
+	CLK_UART3_FRAC_DIV_SHIFT		= 0,
+	CLK_UART3_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON12 */
+	SCLK_UART3_SRC_SEL_SHIFT		= 0,
+	SCLK_UART3_SRC_SEL_MASK			= 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
+	CLK_UART4_SRC_DIV_SHIFT			= 2,
+	CLK_UART4_SRC_DIV_MASK			= 0x1F << CLK_UART4_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON13 */
+	CLK_UART4_FRAC_DIV_SHIFT		= 0,
+	CLK_UART4_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON14 */
+	SCLK_UART4_SRC_SEL_SHIFT		= 0,
+	SCLK_UART4_SRC_SEL_MASK			= 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
+	CLK_UART5_SRC_DIV_SHIFT			= 2,
+	CLK_UART5_SRC_DIV_MASK			= 0x1F << CLK_UART5_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON15 */
+	CLK_UART5_FRAC_DIV_SHIFT		= 0,
+	CLK_UART5_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON16 */
+	SCLK_UART5_SRC_SEL_SHIFT		= 0,
+	SCLK_UART5_SRC_SEL_MASK			= 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
+	CLK_UART6_SRC_DIV_SHIFT			= 2,
+	CLK_UART6_SRC_DIV_MASK			= 0x1F << CLK_UART6_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON17 */
+	CLK_UART6_FRAC_DIV_SHIFT		= 0,
+	CLK_UART6_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON18 */
+	SCLK_UART6_SRC_SEL_SHIFT		= 0,
+	SCLK_UART6_SRC_SEL_MASK			= 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
+	CLK_UART7_SRC_DIV_SHIFT			= 2,
+	CLK_UART7_SRC_DIV_MASK			= 0x1F << CLK_UART7_SRC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON19 */
+	CLK_UART7_FRAC_DIV_SHIFT		= 0,
+	CLK_UART7_FRAC_DIV_MASK			= 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
+	/* CRU_CLKSEL_CON20 */
+	SCLK_UART7_SRC_SEL_SHIFT		= 0,
+	SCLK_UART7_SRC_SEL_MASK			= 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
+	SCLK_UART0_SRC_SEL_CLK_UART0_SRC	= 0U,
+	SCLK_UART0_SRC_SEL_CLK_UART0_FRAC	= 1U,
+	SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC	= 2U,
+
+	/* CRU_CLKSEL_CON60 */
+	CLK_GMAC1_VPU_25M_DIV_SHIFT		= 2,
+	CLK_GMAC1_VPU_25M_DIV_MASK		= 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
+	/* CRU_CLKSEL_CON66 */
+	CLK_GMAC1_SRC_VPU_DIV_SHIFT		= 0,
+	CLK_GMAC1_SRC_VPU_DIV_MASK		= 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
+	/* CRU_CLKSEL_CON84 */
+	CLK_GMAC0_SRC_DIV_SHIFT			= 3,
+	CLK_GMAC0_SRC_DIV_MASK			= 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
+};
+
+#endif /* _ASM_ARCH_CRU_RK3528_H */
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3576_H
+#define _ASM_ARCH_CRU_RK3576_H
+
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+
+#define CPU_PVTPLL_HZ	(1008 * MHz)
+#define LPLL_HZ		(816 * MHz)
+#define GPLL_HZ		(1188 * MHz)
+#define CPLL_HZ		(1000 * MHz)
+#define PPLL_HZ		(1100 * MHz)
+#define GMAC0_PTP_REFCLK_IN	(24 * MHz)
+#define GMAC1_PTP_REFCLK_IN	(24 * MHz)
+
+/* RK3576 pll id */
+enum rk3576_pll_id {
+	BPLL,
+	LPLL,
+	DPLL,
+	CPLL,
+	GPLL,
+	VPLL,
+	AUPLL,
+	SPLL,
+	PPLL,
+	PLL_COUNT,
+};
+
+struct rk3576_clk_priv {
+	struct rk3576_cru *cru;
+	ulong ppll_hz;
+	ulong gpll_hz;
+	ulong cpll_hz;
+	ulong vpll_hz;
+	ulong aupll_hz;
+	ulong spll_hz;
+	ulong lpll_hz;
+	ulong bpll_hz;
+	ulong armclk_hz;
+	ulong armclk_enter_hz;
+	ulong armclk_init_hz;
+	bool sync_kernel;
+	bool set_armclk_rate;
+};
+
+struct rk3576_pll {
+	unsigned int con0;
+	unsigned int con1;
+	unsigned int con2;
+	unsigned int con3;
+	unsigned int con4;
+	unsigned int reserved0[3];
+};
+
+struct rk3576_cru {
+	struct rk3576_pll pll[18];
+	unsigned int reserved0[16];/* Address Offset: 0x0240 */
+	unsigned int mode_con00;/* Address Offset: 0x0280 */
+	unsigned int reserved1[31];/* Address Offset: 0x0284 */
+	unsigned int clksel_con[181]; /* Address Offset: 0x0300 */
+	unsigned int reserved2[139];/* Address Offset: 0x05d4 */
+	unsigned int clkgate_con[80];/* Address Offset: 0x0800 */
+	unsigned int reserved3[48];/* Address Offset: 0x0938 */
+	unsigned int softrst_con[80];/* Address Offset: 0x0400 */
+	unsigned int reserved4[48];/* Address Offset: 0x0b38 */
+	unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
+	unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
+	unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
+	unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
+	unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
+	unsigned int reserved5[43];/* Address Offset: 0x0c14 */
+	unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */
+	unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */
+	unsigned int reserved8[32137];/* Address Offset: 0x0c38 */
+	unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */
+	unsigned int reserved9[298];/* Address Offset: 0x20358 */
+	unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */
+	unsigned int reserved10[32440];/* Address Offset: 0x20820 */
+	unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */
+};
+
+check_member(rk3576_cru, mode_con00, 0x280);
+check_member(rk3576_cru, pmuclksel_con[1], 0x20304);
+
+struct pll_rate_table {
+	unsigned long rate;
+	unsigned int m;
+	unsigned int p;
+	unsigned int s;
+	unsigned int k;
+};
+
+#define RK3576_PHP_CRU_BASE		0x8000
+#define RK3576_PMU_CRU_BASE		0x20000
+#define RK3576_BIGCORE_CRU_BASE		0x38000
+#define RK3576_LITCORE_CRU_BASE		0x40000
+#define RK3576_CCI_CRU_BASE		0x48000
+#define RK3576_CRU_BASE			0x27200000
+#define RK3576_SCRU_BASE		0x27214000
+
+#define RK3576_BIGCORE_GRF_BASE		0x2600C000
+#define RK3576_LITCORE_GRF_BASE		0x2600E000
+#define RK3576_CCI_GRF_BASE		0x26010000
+
+#define RK3576_PLL_CON(x)		((x) * 0x4)
+#define RK3576_MODE_CON0		0x280
+#define RK3576_BPLL_MODE_CON0		(RK3576_BIGCORE_CRU_BASE + 0x280)
+#define RK3576_LPLL_MODE_CON0		(RK3576_LITCORE_CRU_BASE + 0x280)
+#define RK3576_PPLL_MODE_CON0		(RK3576_PHP_CRU_BASE + 0x280)
+#define RK3576_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
+#define RK3576_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
+#define RK3576_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
+#define RK3576_GLB_CNT_TH		0xc00
+#define RK3576_GLB_SRST_FST		0xc08
+#define RK3576_GLB_SRST_SND		0xc0c
+#define RK3576_GLB_RST_CON		0xc10
+#define RK3576_GLB_RST_ST		0xc04
+#define RK3576_SDIO_CON0		0xC24
+#define RK3576_SDIO_CON1		0xC28
+#define RK3576_SDMMC_CON0		0xC30
+#define RK3576_SDMMC_CON1		0xC34
+
+#define RK3576_PHP_CLKSEL_CON(x)	((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
+#define RK3576_PHP_CLKGATE_CON(x)	((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
+#define RK3576_PHP_SOFTRST_CON(x)	((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
+
+#define RK3576_PMU_PLL_CON(x)		((x) * 0x4 + RK3576_PHP_CRU_BASE)
+#define RK3576_PMU_CLKSEL_CON(x)	((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
+#define RK3576_PMU_CLKGATE_CON(x)	((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
+#define RK3576_PMU_SOFTRST_CON(x)	((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
+
+#define RK3576_CCI_CLKSEL_CON(x)	((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
+#define RK3576_CCI_CLKGATE_CON(x)	((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
+#define RK3576_CCI_SOFTRST_CON(x)	((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
+
+#define RK3576_BPLL_CON(x)		((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
+#define RK3576_BIGCORE_CLKSEL_CON(x)	((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
+#define RK3576_BIGCORE_CLKGATE_CON(x)	((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
+#define RK3576_BIGCORE_SOFTRST_CON(x)	((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
+#define RK3576_LPLL_CON(x)		((x) * 0x4 + RK3576_CCI_CRU_BASE)
+#define RK3576_LITCORE_CLKSEL_CON(x)	((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
+#define RK3576_LITCORE_CLKGATE_CON(x)	((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
+#define RK3576_LITCORE_SOFTRST_CON(x)	((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
+
+enum {
+	/* CRU_CLK_SEL8_CON */
+	PCLK_TOP_SEL_SHIFT		= 7,
+	PCLK_TOP_SEL_MASK		= 3 << PCLK_TOP_SEL_SHIFT,
+	PCLK_TOP_SEL_100M		= 0,
+	PCLK_TOP_SEL_50M,
+	PCLK_TOP_SEL_OSC,
+
+	/* CRU_CLK_SEL9_CON */
+	ACLK_TOP_SEL_SHIFT		= 5,
+	ACLK_TOP_SEL_MASK		= 3 << ACLK_TOP_SEL_SHIFT,
+	ACLK_TOP_SEL_GPLL		= 0,
+	ACLK_TOP_SEL_CPLL,
+	ACLK_TOP_SEL_AUPLL,
+	ACLK_TOP_DIV_SHIFT		= 0,
+	ACLK_TOP_DIV_MASK		= 0x1f << ACLK_TOP_DIV_SHIFT,
+
+	/* CRU_CLK_SEL10_CON */
+	ACLK_TOP_MID_SEL_SHIFT		= 5,
+	ACLK_TOP_MID_SEL_MASK		= 1 << ACLK_TOP_MID_SEL_SHIFT,
+	ACLK_TOP_MID_SEL_GPLL		= 0,
+	ACLK_TOP_MID_SEL_CPLL,
+	ACLK_TOP_MID_DIV_SHIFT		= 0,
+	ACLK_TOP_MID_DIV_MASK		= 0x1f << ACLK_TOP_MID_DIV_SHIFT,
+
+	/* CRU_CLK_SEL19_CON */
+	HCLK_TOP_SEL_SHIFT		= 2,
+	HCLK_TOP_SEL_MASK		= 3 << HCLK_TOP_SEL_SHIFT,
+	HCLK_TOP_SEL_200M		= 0,
+	HCLK_TOP_SEL_100M,
+	HCLK_TOP_SEL_50M,
+	HCLK_TOP_SEL_OSC,
+
+	/* CRU_CLK_SEL25_CON */
+	CLK_UART_FRAC_NUMERATOR_SHIFT	= 16,
+	CLK_UART_FRAC_NUMERATOR_MASK	= 0xffff << 16,
+	CLK_UART_FRAC_DENOMINATOR_SHIFT	= 0,
+	CLK_UART_FRAC_DENOMINATOR_MASK	= 0xffff,
+
+	/* CRU_CLK_SEL26_CON */
+	CLK_UART_SRC_SEL_SHIFT		= 0,
+	CLK_UART_SRC_SEL_MASK		= 0x3 << CLK_UART_SRC_SEL_SHIFT,
+	CLK_UART_SRC_SEL_GPLL		= 0,
+	CLK_UART_SRC_SEL_CPLL,
+	CLK_UART_SRC_SEL_AUPLL,
+	CLK_UART_SRC_SEL_OSC,
+
+	/* CRU_CLK_SEL27_CON */
+	CLK_UART1_SRC_SEL_SHIFT		= 13,
+	CLK_UART1_SRC_SEL_MASK		= 0x7 << CLK_UART1_SRC_SEL_SHIFT,
+	CLK_UART1_SRC_DIV_SHIFT		= 5,
+	CLK_UART1_SRC_DIV_MASK		= 0xff << CLK_UART1_SRC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL30_CON */
+	CLK_GMAC0_125M_DIV_SHIFT	= 10,
+	CLK_GMAC0_125M_DIV_MASK		= 0x1f << CLK_GMAC0_125M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL31_CON */
+	CLK_GMAC1_125M_DIV_SHIFT	= 0,
+	CLK_GMAC1_125M_DIV_MASK		= 0x1f << CLK_GMAC1_125M_DIV_SHIFT,
+
+	/* CRU_CLK_SEL33_CON */
+	REF_CLK0_OUT_PLL_SEL_SHIFT	= 8,
+	REF_CLK0_OUT_PLL_SEL_MASK	= 7 << REF_CLK0_OUT_PLL_SEL_SHIFT,
+	REF_CLK0_OUT_PLL_SEL_GPLL	= 0,
+	REF_CLK0_OUT_PLL_SEL_CPLL,
+	REF_CLK0_OUT_PLL_SEL_SPLL,
+	REF_CLK0_OUT_PLL_SEL_AUPLL,
+	REF_CLK0_OUT_PLL_SEL_LPLL,
+	REF_CLK0_OUT_PLL_SEL_OSC,
+	REF_CLK0_OUT_PLL_DIV_SHIFT	= 0,
+	REF_CLK0_OUT_PLL_DIV_MASK	= 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT,
+
+	/* CRU_CLK_SEL55_CON */
+	ACLK_BUS_ROOT_SEL_SHIFT		= 9,
+	ACLK_BUS_ROOT_SEL_MASK		= 1 << ACLK_BUS_ROOT_SEL_SHIFT,
+	ACLK_BUS_ROOT_SEL_GPLL		= 0,
+	ACLK_BUS_ROOT_SEL_CPLL,
+	ACLK_BUS_ROOT_DIV_SHIFT		= 4,
+	ACLK_BUS_ROOT_DIV_MASK		= 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
+	PCLK_BUS_ROOT_SEL_SHIFT		= 2,
+	PCLK_BUS_ROOT_SEL_MASK		= 3 << PCLK_BUS_ROOT_SEL_SHIFT,
+	PCLK_BUS_ROOT_SEL_100M		= 0,
+	PCLK_BUS_ROOT_SEL_50M,
+	PCLK_BUS_ROOT_SEL_OSC,
+	HCLK_BUS_ROOT_SEL_SHIFT		= 0,
+	HCLK_BUS_ROOT_SEL_MASK		= 3 << HCLK_BUS_ROOT_SEL_SHIFT,
+	HCLK_BUS_ROOT_SEL_200M		= 0,
+	HCLK_BUS_ROOT_SEL_100M,
+	HCLK_BUS_ROOT_SEL_50M,
+	HCLK_BUS_ROOT_SEL_OSC,
+
+	/* CRU_CLK_SEL57_CON */
+	CLK_I2C8_SEL_SHIFT		= 14,
+	CLK_I2C8_SEL_MASK		= 3 << CLK_I2C8_SEL_SHIFT,
+	CLK_I2C7_SEL_SHIFT		= 12,
+	CLK_I2C7_SEL_MASK		= 3 << CLK_I2C7_SEL_SHIFT,
+	CLK_I2C6_SEL_SHIFT		= 10,
+	CLK_I2C6_SEL_MASK		= 3 << CLK_I2C6_SEL_SHIFT,
+	CLK_I2C5_SEL_SHIFT		= 8,
+	CLK_I2C5_SEL_MASK		= 3 << CLK_I2C5_SEL_SHIFT,
+	CLK_I2C4_SEL_SHIFT		= 6,
+	CLK_I2C4_SEL_MASK		= 3 << CLK_I2C4_SEL_SHIFT,
+	CLK_I2C3_SEL_SHIFT		= 4,
+	CLK_I2C3_SEL_MASK		= 3 << CLK_I2C3_SEL_SHIFT,
+	CLK_I2C2_SEL_SHIFT		= 2,
+	CLK_I2C2_SEL_MASK		= 3 << CLK_I2C2_SEL_SHIFT,
+	CLK_I2C1_SEL_SHIFT		= 0,
+	CLK_I2C1_SEL_MASK		= 3 << CLK_I2C1_SEL_SHIFT,
+	CLK_I2C_SEL_200M		= 0,
+	CLK_I2C_SEL_100M,
+	CLK_I2C_SEL_50M,
+	CLK_I2C_SEL_OSC,
+
+	/* CRU_CLK_SEL58_CON */
+	CLK_SARADC_SEL_SHIFT		= 12,
+	CLK_SARADC_SEL_MASK		= 0x1 << CLK_SARADC_SEL_SHIFT,
+	CLK_SARADC_SEL_GPLL		= 0,
+	CLK_SARADC_SEL_OSC,
+	CLK_SARADC_DIV_SHIFT		= 4,
+	CLK_SARADC_DIV_MASK		= 0xff << CLK_SARADC_DIV_SHIFT,
+	CLK_I2C9_SEL_SHIFT		= 0,
+	CLK_I2C9_SEL_MASK		= 3 << CLK_I2C9_SEL_SHIFT,
+
+	/* CRU_CLK_SEL59_CON */
+	CLK_TSADC_DIV_SHIFT		= 0,
+	CLK_TSADC_DIV_MASK		= 0xff << CLK_TSADC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL60_CON */
+	CLK_UART_SEL_SHIFT		= 8,
+	CLK_UART_SEL_MASK		= 7 << CLK_UART_SEL_SHIFT,
+	CLK_UART_SEL_GPLL		= 0,
+	CLK_UART_SEL_CPLL,
+	CLK_UART_SEL_AUPLL,
+	CLK_UART_SEL_OSC,
+	CLK_UART_SEL_FRAC0,
+	CLK_UART_SEL_FRAC1,
+	CLK_UART_SEL_FRAC2,
+	CLK_UART_DIV_SHIFT		= 0,
+	CLK_UART_DIV_MASK		= 0xff << CLK_UART_DIV_SHIFT,
+
+	/* CRU_CLK_SEL70_CON */
+	CLK_SPI0_SEL_SHIFT		= 13,
+	CLK_SPI0_SEL_MASK		= 3 << CLK_SPI0_SEL_SHIFT,
+	CLK_SPI_SEL_200M		= 0,
+	CLK_SPI_SEL_100M,
+	CLK_SPI_SEL_50M,
+	CLK_SPI_SEL_OSC,
+
+	/* CRU_CLK_SEL71_CON */
+	CLK_PWM1_SEL_SHIFT		= 8,
+	CLK_PWM1_SEL_MASK		= 3 << CLK_PWM1_SEL_SHIFT,
+	CLK_SPI4_SEL_SHIFT		= 6,
+	CLK_SPI4_SEL_MASK		= 3 << CLK_SPI4_SEL_SHIFT,
+	CLK_SPI3_SEL_SHIFT		= 4,
+	CLK_SPI3_SEL_MASK		= 3 << CLK_SPI3_SEL_SHIFT,
+	CLK_SPI2_SEL_SHIFT		= 2,
+	CLK_SPI2_SEL_MASK		= 3 << CLK_SPI2_SEL_SHIFT,
+	CLK_SPI1_SEL_SHIFT		= 0,
+	CLK_SPI1_SEL_MASK		= 3 << CLK_SPI1_SEL_SHIFT,
+	CLK_PWM_SEL_100M		= 0,
+	CLK_PWM_SEL_50M,
+	CLK_PWM_SEL_OSC,
+
+	/* CRU_CLK_SEL72_CON */
+	DCLK_DECOM_SEL_SHIFT		= 5,
+	DCLK_DECOM_SEL_MASK		= 1 << DCLK_DECOM_SEL_SHIFT,
+	DCLK_DECOM_SEL_GPLL		= 0,
+	DCLK_DECOM_SEL_SPLL,
+	DCLK_DECOM_DIV_SHIFT		= 0,
+	DCLK_DECOM_DIV_MASK		= 0x1f << DCLK_DECOM_DIV_SHIFT,
+
+	/* CRU_CLK_SEL74_CON */
+	CLK_PWM2_SEL_SHIFT		= 6,
+	CLK_PWM2_SEL_MASK		= 3 << CLK_PWM2_SEL_SHIFT,
+
+	/* CRU_CLK_SEL89_CON */
+	CCLK_EMMC_SEL_SHIFT		= 14,
+	CCLK_EMMC_SEL_MASK		= 3 << CCLK_EMMC_SEL_SHIFT,
+	CCLK_EMMC_SEL_GPLL		= 0,
+	CCLK_EMMC_SEL_CPLL,
+	CCLK_EMMC_SEL_OSC,
+	CCLK_EMMC_DIV_SHIFT		= 8,
+	CCLK_EMMC_DIV_MASK		= 0x3f << CCLK_EMMC_DIV_SHIFT,
+	SCLK_FSPI_SEL_SHIFT		= 6,
+	SCLK_FSPI_SEL_MASK		= 3 << SCLK_FSPI_SEL_SHIFT,
+	SCLK_FSPI_SEL_GPLL		= 0,
+	SCLK_FSPI_SEL_CPLL,
+	SCLK_FSPI_SEL_OSC,
+	SCLK_FSPI_DIV_SHIFT		= 0,
+	SCLK_FSPI_DIV_MASK		= 0x3f << SCLK_FSPI_DIV_SHIFT,
+
+	/* CRU_CLK_SEL90_CON */
+	BCLK_EMMC_SEL_SHIFT		= 0,
+	BCLK_EMMC_SEL_MASK		= 3 << BCLK_EMMC_SEL_SHIFT,
+	BCLK_EMMC_SEL_200M		= 0,
+	BCLK_EMMC_SEL_100M,
+	BCLK_EMMC_SEL_50M,
+	BCLK_EMMC_SEL_OSC,
+
+	/* CRU_CLK_SEL104_CON */
+	CLK_GMAC1_PTP_SEL_SHIFT		= 13,
+	CLK_GMAC1_PTP_SEL_MASK		= 3 << CLK_GMAC1_PTP_SEL_SHIFT,
+	CLK_GMAC1_PTP_SEL_GPLL		= 0,
+	CLK_GMAC1_PTP_SEL_CPLL,
+	CLK_GMAC1_PTP_SEL_REFIN,
+	CLK_GMAC1_PTP_DIV_SHIFT		= 8,
+	CLK_GMAC1_PTP_DIV_MASK		= 0x1f << CLK_GMAC1_PTP_DIV_SHIFT,
+	CCLK_SDIO_SRC_SEL_SHIFT		= 6,
+	CCLK_SDIO_SRC_SEL_MASK		= 3 << CCLK_SDIO_SRC_SEL_SHIFT,
+	CCLK_SDIO_SRC_SEL_GPLL		= 0,
+	CCLK_SDIO_SRC_SEL_CPLL,
+	CCLK_SDIO_SRC_SEL_OSC,
+	CCLK_SDIO_SRC_DIV_SHIFT		= 0,
+	CCLK_SDIO_SRC_DIV_MASK		= 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL105_CON */
+	CCLK_SDMMC0_SRC_SEL_SHIFT	= 13,
+	CCLK_SDMMC0_SRC_SEL_MASK	= 3 << CCLK_SDMMC0_SRC_SEL_SHIFT,
+	CCLK_SDMMC0_SRC_SEL_GPLL	= 0,
+	CCLK_SDMMC0_SRC_SEL_CPLL,
+	CCLK_SDMMC0_SRC_SEL_OSC,
+	CCLK_SDMMC0_SRC_DIV_SHIFT	= 7,
+	CCLK_SDMMC0_SRC_DIV_MASK	= 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT,
+	CLK_GMAC0_PTP_SEL_SHIFT		= 5,
+	CLK_GMAC0_PTP_SEL_MASK		= 3 << CLK_GMAC0_PTP_SEL_SHIFT,
+	CLK_GMAC0_PTP_SEL_GPLL		= 0,
+	CLK_GMAC0_PTP_SEL_CPLL,
+	CLK_GMAC0_PTP_SEL_REFIN,
+	CLK_GMAC0_PTP_DIV_SHIFT		= 0,
+	CLK_GMAC0_PTP_DIV_MASK		= 0x1f << CLK_GMAC0_PTP_DIV_SHIFT,
+
+	/* CRU_CLK_SEL123_CON */
+	DCLK_EBC_SEL_SHIFT		= 12,
+	DCLK_EBC_SEL_MASK		= 7 << DCLK_EBC_SEL_SHIFT,
+	DCLK_EBC_SEL_GPLL		= 0,
+	DCLK_EBC_SEL_CPLL,
+	DCLK_EBC_SEL_VPLL,
+	DCLK_EBC_SEL_AUPLL,
+	DCLK_EBC_SEL_LPLL,
+	DCLK_EBC_SEL_FRAC_SRC,
+	DCLK_EBC_SEL_OSC,
+	DCLK_EBC_DIV_SHIFT		= 3,
+	DCLK_EBC_DIV_MASK		= 0x1ff << DCLK_EBC_DIV_SHIFT,
+	DCLK_EBC_FRAC_SRC_SEL_SHIFT	= 0,
+	DCLK_EBC_FRAC_SRC_SEL_MASK	= 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT,
+	DCLK_EBC_FRAC_SRC_SEL_GPLL	= 0,
+	DCLK_EBC_FRAC_SRC_SEL_CPLL,
+	DCLK_EBC_FRAC_SRC_SEL_VPLL,
+	DCLK_EBC_FRAC_SRC_SEL_AUPLL,
+	DCLK_EBC_FRAC_SRC_SEL_OSC,
+
+	/* CRU_CLK_SEL144_CON */
+	PCLK_VOP_ROOT_SEL_SHIFT		= 12,
+	PCLK_VOP_ROOT_SEL_MASK		= 3 << PCLK_VOP_ROOT_SEL_SHIFT,
+	PCLK_VOP_ROOT_SEL_100M		= 0,
+	PCLK_VOP_ROOT_SEL_50M,
+	PCLK_VOP_ROOT_SEL_OSC,
+	HCLK_VOP_ROOT_SEL_SHIFT		= 10,
+	HCLK_VOP_ROOT_SEL_MASK		= 3 << HCLK_VOP_ROOT_SEL_SHIFT,
+	HCLK_VOP_ROOT_SEL_200M		= 0,
+	HCLK_VOP_ROOT_SEL_100M,
+	HCLK_VOP_ROOT_SEL_50M,
+	HCLK_VOP_ROOT_SEL_OSC,
+	ACLK_VOP_ROOT_SEL_SHIFT		= 5,
+	ACLK_VOP_ROOT_SEL_MASK		= 7 << ACLK_VOP_ROOT_SEL_SHIFT,
+	ACLK_VOP_ROOT_SEL_GPLL		= 0,
+	ACLK_VOP_ROOT_SEL_CPLL,
+	ACLK_VOP_ROOT_SEL_AUPLL,
+	ACLK_VOP_ROOT_SEL_SPLL,
+	ACLK_VOP_ROOT_SEL_LPLL,
+	ACLK_VOP_ROOT_DIV_SHIFT		= 0,
+	ACLK_VOP_ROOT_DIV_MASK		= 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
+
+	/* CRU_CLK_SEL145_CON */
+	DCLK0_VOP_SRC_SEL_SHIFT		= 8,
+	DCLK0_VOP_SRC_SEL_MASK		= 7 << DCLK0_VOP_SRC_SEL_SHIFT,
+	DCLK_VOP_SRC_SEL_GPLL		= 0,
+	DCLK_VOP_SRC_SEL_CPLL,
+	DCLK_VOP_SRC_SEL_VPLL,
+	DCLK_VOP_SRC_SEL_BPLL,
+	DCLK_VOP_SRC_SEL_LPLL,
+	DCLK0_VOP_SRC_DIV_SHIFT		= 0,
+	DCLK0_VOP_SRC_DIV_MASK		= 0xff << DCLK0_VOP_SRC_DIV_SHIFT,
+
+	/* CRU_CLK_SEL147_CON */
+	DCLK2_VOP_SEL_SHIFT		= 13,
+	DCLK2_VOP_SEL_MASK		= 1 << DCLK2_VOP_SEL_SHIFT,
+	DCLK1_VOP_SEL_SHIFT		= 12,
+	DCLK1_VOP_SEL_MASK		= 1 << DCLK1_VOP_SEL_SHIFT,
+	DCLK0_VOP_SEL_SHIFT		= 11,
+	DCLK0_VOP_SEL_MASK		= 1 << DCLK0_VOP_SEL_SHIFT,
+
+	/* CRU_CLK_SEL149_CON */
+	ACLK_VO0_ROOT_SEL_SHIFT		= 5,
+	ACLK_VO0_ROOT_SEL_MASK		= 3 << ACLK_VO0_ROOT_SEL_SHIFT,
+	ACLK_VO0_ROOT_SEL_GPLL		= 0,
+	ACLK_VO0_ROOT_SEL_CPLL,
+	ACLK_VO0_ROOT_SEL_LPLL,
+	ACLK_VO0_ROOT_SEL_BPLL,
+	ACLK_VO0_ROOT_DIV_SHIFT		= 0,
+	ACLK_VO0_ROOT_DIV_MASK		= 0x1f << ACLK_VO0_ROOT_DIV_SHIFT,
+
+	/* CRU_CLK_SEL151_CON */
+	CLK_DSIHOST0_SEL_SHIFT		= 7,
+	CLK_DSIHOST0_SEL_MASK		= 7 << CLK_DSIHOST0_SEL_SHIFT,
+	CLK_DSIHOST0_SEL_GPLL		= 0,
+	CLK_DSIHOST0_SEL_CPLL,
+	CLK_DSIHOST0_SEL_SPLL,
+	CLK_DSIHOST0_SEL_VPLL,
+	CLK_DSIHOST0_SEL_BPLL,
+	CLK_DSIHOST0_SEL_LPLL,
+	CLK_DSIHOST0_DIV_SHIFT		= 0,
+	CLK_DSIHOST0_DIV_MASK		= 0x7f << CLK_DSIHOST0_DIV_SHIFT,
+
+	/* PMUCRU_CLK_SEL5_CON */
+	CLK_PMU1PWM_SEL_SHIFT		= 2,
+	CLK_PMU1PWM_SEL_MASK		= 3 << CLK_PMU1PWM_SEL_SHIFT,
+
+	/* PMUCRU_CLK_SEL6_CON */
+	CLK_I2C0_SEL_SHIFT		= 7,
+	CLK_I2C0_SEL_MASK		= 3 << CLK_I2C0_SEL_SHIFT,
+
+	/* PMUCRU_CLK_SEL8_CON */
+	CLK_UART1_SEL_SHIFT		= 0,
+	CLK_UART1_SEL_MASK		= 1 << CLK_UART1_SEL_SHIFT,
+	CLK_UART1_SEL_TOP		= 0,
+	CLK_UART1_SEL_OSC,
+
+	/* LITCRU_CLK_SEL0_CON */
+	CLK_LITCORE_SEL_SHIFT		= 12,
+	CLK_LITCORE_SEL_MASK		= 3 << CLK_LITCORE_SEL_SHIFT,
+	CLK_LITCORE_SEL_LPLL		= 0,
+	CLK_LITCORE_SEL_GPLL,
+	CLK_LITCORE_SEL_PVTPLL,
+	CLK_LITCORE_DIV_SHIFT		= 7,
+	CLK_LITCORE_DIV_MASK		= 0x1f << CLK_LITCORE_DIV_SHIFT,
+
+};
+#endif
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -15,7 +15,9 @@ config ROCKCHIP_PX30
 	select TPL_SERIAL
 	select DEBUG_UART_BOARD_INIT
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply SPL_ROCKCHIP_COMMON_BOARD
+	imply TPL_LIBGENERIC_SUPPORT
 	imply ARMV8_CRYPTO
 	imply ARMV8_SET_SMPEN
 	help
@@ -176,6 +178,8 @@ config ROCKCHIP_RK3308
 	imply OF_UPSTREAM
 	imply RNG_ROCKCHIP
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
+	imply ROCKCHIP_EXTERNAL_TPL
 	imply ROCKCHIP_OTP
 	imply SPL_CLK
 	imply SPL_DM_SEQ_ALIAS
@@ -197,7 +201,6 @@ config ROCKCHIP_RK3328
 	select SUPPORT_SPL
 	select SPL
 	select SUPPORT_TPL
-	select TPL
 	select TPL_HAVE_INIT_STACK if TPL
 	imply ARMV8_CRYPTO
 	imply ARMV8_SET_SMPEN
@@ -208,11 +211,14 @@ config ROCKCHIP_RK3328
 	imply OF_UPSTREAM
 	imply PRE_CONSOLE_BUFFER
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EFUSE
 	imply ROCKCHIP_SDRAM_COMMON
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SEPARATE_BSS
 	imply SPL_SERIAL
+	imply TPL if !ROCKCHIP_EXTERNAL_TPL
+	imply TPL_ROCKCHIP_COMMON_BOARD
 	imply TPL_SERIAL
 	help
 	  The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
@@ -285,6 +291,7 @@ config ROCKCHIP_RK3399
 	imply PRE_CONSOLE_BUFFER
 	imply RNG_ROCKCHIP
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EFUSE
 	imply ROCKCHIP_SDRAM_COMMON
 	imply SPL_DM_SEQ_ALIAS
@@ -312,6 +319,56 @@ config ROCKCHIP_RK3399
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.

+config ROCKCHIP_RK3528
+	bool "Support Rockchip RK3528"
+	select ARM64
+	select SUPPORT_SPL
+	select SPL
+	select CLK
+	select PINCTRL
+	select RAM
+	select REGMAP
+	select SYSCON
+	select BOARD_LATE_INIT
+	select DM_REGULATOR_FIXED
+	select DM_RESET
+	imply ARMV8_CRYPTO
+	imply ARMV8_SET_SMPEN
+	imply BOOTSTD_FULL
+	imply DM_RNG
+	imply FIT
+	imply LEGACY_IMAGE_FORMAT
+	imply MISC
+	imply MISC_INIT_R
+	imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+	imply OF_LIBFDT_OVERLAY
+	imply OF_LIVE
+	imply OF_UPSTREAM
+	imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+	imply RNG_ROCKCHIP
+	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
+	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_OTP
+	imply SPL_ATF
+	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+	imply SPL_CLK
+	imply SPL_DM_SEQ_ALIAS
+	imply SPL_FIT_SIGNATURE
+	imply SPL_LOAD_FIT
+	imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+	imply SPL_OF_CONTROL
+	imply SPL_PINCTRL
+	imply SPL_RAM
+	imply SPL_REGMAP
+	imply SPL_SERIAL
+	imply SPL_SYSCON
+	imply SYS_RELOC_GD_ENV_ADDR
+	imply SYSRESET
+	imply SYSRESET_PSCI if SPL_ATF
+	help
+	  The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
+
 config ROCKCHIP_RK3568
 	bool "Support Rockchip RK3568"
 	select ARM64
@@ -334,6 +391,8 @@ config ROCKCHIP_RK3568
 	imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
 	imply RNG_ROCKCHIP
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
+	imply ROCKCHIP_EXTERNAL_TPL
 	imply ROCKCHIP_OTP
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
 	imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
@@ -344,6 +403,56 @@ config ROCKCHIP_RK3568
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.

+config ROCKCHIP_RK3576
+	bool "Support Rockchip RK3576"
+	select ARM64
+	select SUPPORT_SPL
+	select SPL
+	select CLK
+	select PINCTRL
+	select RAM
+	select REGMAP
+	select SYSCON
+	select BOARD_LATE_INIT
+	select DM_REGULATOR_FIXED
+	select DM_RESET
+	imply ARMV8_CRYPTO
+	imply ARMV8_SET_SMPEN
+	imply BOOTSTD_FULL
+	imply DM_RNG
+	imply FIT
+	imply LEGACY_IMAGE_FORMAT
+	imply MISC
+	imply MISC_INIT_R
+	imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+	imply OF_LIBFDT_OVERLAY
+	imply OF_LIVE
+	imply OF_UPSTREAM
+	imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+	imply RNG_ROCKCHIP
+	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
+	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_OTP
+	imply SPL_ATF
+	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+	imply SPL_CLK
+	imply SPL_DM_SEQ_ALIAS
+	imply SPL_FIT_SIGNATURE
+	imply SPL_LOAD_FIT
+	imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+	imply SPL_OF_CONTROL
+	imply SPL_PINCTRL
+	imply SPL_RAM
+	imply SPL_REGMAP
+	imply SPL_SERIAL
+	imply SPL_SYSCON
+	imply SYS_RELOC_GD_ENV_ADDR
+	imply SYSRESET
+	help
+	  The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72 and
+	  and quad-core Cortex-A53.
+
 config ROCKCHIP_RK3588
 	bool "Support Rockchip RK3588"
 	select ARM64
@@ -367,6 +476,8 @@ config ROCKCHIP_RK3588
 	imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
 	imply RNG_ROCKCHIP
 	imply ROCKCHIP_COMMON_BOARD
+	imply ROCKCHIP_COMMON_STACK_ADDR
+	imply ROCKCHIP_EXTERNAL_TPL
 	imply ROCKCHIP_OTP
 	imply SCMI_FIRMWARE
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -493,7 +604,6 @@ config TPL_ROCKCHIP_COMMON_BOARD

 config ROCKCHIP_EXTERNAL_TPL
 	bool "Use external TPL binary"
-	default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
 	help
 	  Some Rockchip SoCs require an external TPL to initialize DRAM.
 	  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
@@ -603,17 +713,17 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 config ROCKCHIP_COMMON_STACK_ADDR
 	bool
 	depends on SPL_SHARES_INIT_SP_ADDR
+	depends on TPL || ROCKCHIP_EXTERNAL_TPL
 	select HAS_CUSTOM_SYS_INIT_SP_ADDR
 	imply SPL_LIBCOMMON_SUPPORT if SPL
 	imply SPL_LIBGENERIC_SUPPORT if SPL
 	imply SPL_ROCKCHIP_COMMON_BOARD if SPL
 	imply SPL_SYS_MALLOC_F if SPL
 	imply SPL_SYS_MALLOC_SIMPLE if SPL
-	imply TPL_LIBCOMMON_SUPPORT if TPL
-	imply TPL_LIBGENERIC_SUPPORT if TPL
-	imply TPL_ROCKCHIP_COMMON_BOARD if TPL
-	imply TPL_SYS_MALLOC_F if TPL
-	imply TPL_SYS_MALLOC_SIMPLE if TPL
+	imply TPL_LIBCOMMON_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD
+	imply TPL_LIBGENERIC_SUPPORT if TPL && TPL_ROCKCHIP_COMMON_BOARD
+	imply TPL_SYS_MALLOC_F if TPL && TPL_ROCKCHIP_COMMON_BOARD
+	imply TPL_SYS_MALLOC_SIMPLE if TPL && TPL_ROCKCHIP_COMMON_BOARD

 config NR_DRAM_BANKS
 	default 10 if ROCKCHIP_EXTERNAL_TPL
@@ -629,7 +739,9 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
 source "arch/arm/mach-rockchip/rk3328/Kconfig"
 source "arch/arm/mach-rockchip/rk3368/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
 source "arch/arm/mach-rockchip/rk3568/Kconfig"
+source "arch/arm/mach-rockchip/rk3576/Kconfig"
 source "arch/arm/mach-rockchip/rk3588/Kconfig"
 source "arch/arm/mach-rockchip/rv1108/Kconfig"
 source "arch/arm/mach-rockchip/rv1126/Kconfig"
@@ -637,40 +749,64 @@ source "arch/arm/mach-rockchip/rv1126/Kconfig"
 if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR

 config CUSTOM_SYS_INIT_SP_ADDR
-	default 0x3f00000
+	default 0x63f00000 if SPL_TEXT_BASE = 0x60000000
+	default 0x43f00000 if SPL_TEXT_BASE = 0x40000000
+	default 0x03f00000 if SPL_TEXT_BASE = 0x00000000

 config SYS_MALLOC_F_LEN
-	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000

 config SPL_SYS_MALLOC_F_LEN
-	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000

 config TPL_SYS_MALLOC_F_LEN
-	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+	default 0x0800 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000

 config TEXT_BASE
-	default 0x00200000 if ARM64
+	default 0x60200000 if SPL_TEXT_BASE = 0x60000000
+	default 0x40200000 if SPL_TEXT_BASE = 0x40000000
+	default 0x00200000 if SPL_TEXT_BASE = 0x00000000

 config SPL_TEXT_BASE
-	default 0x0 if ARM64
+	default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \
+			      ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
+			      ROCKCHIP_RK322X || ROCKCHIP_RV1108
+	default 0x40000000 if ROCKCHIP_RK3576
+	default 0x00000000

 config SPL_HAS_BSS_LINKER_SECTION
 	default y if ARM64

 config SPL_BSS_START_ADDR
-	default 0x3f80000
+	default 0x63f80000 if SPL_TEXT_BASE = 0x60000000
+	default 0x43f80000 if SPL_TEXT_BASE = 0x40000000
+	default 0x03f80000 if SPL_TEXT_BASE = 0x00000000

 config SPL_BSS_MAX_SIZE
-	default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
+	default 0x8000 if SPL_BSS_START_ADDR = 0x63f80000
+	default 0x8000 if SPL_BSS_START_ADDR = 0x43f80000
+	default 0x8000 if SPL_BSS_START_ADDR = 0x03f80000

 config SPL_STACK_R
-	default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+	default y if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+	default y if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+	default y if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000

 config SPL_STACK_R_ADDR
-	default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+	default 0x63e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
+	default 0x43e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x43f00000
+	default 0x03e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000

 config SPL_STACK_R_MALLOC_SIMPLE_LEN
-	default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
+	default 0x200000 if SPL_STACK_R_ADDR = 0x63e00000
+	default 0x200000 if SPL_STACK_R_ADDR = 0x43e00000
+	default 0x200000 if SPL_STACK_R_ADDR = 0x03e00000

 endif
 endif
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,7 +42,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
 obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
+obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
 obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
 obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,9 +68,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "px30"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config SYS_MALLOC_F_LEN
 	default 0x400 if !SPL_SHARES_INIT_SP_ADDR

--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "rk3308"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config TEXT_BASE
 	default 0x00600000

--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -3,15 +3,12 @@
 *Copyright (c) 2018 Rockchip Electronics Co., Ltd
 */
 #include <init.h>
-#include <malloc.h>
+#include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/grf_rk3308.h>
 #include <asm/arch-rockchip/hardware.h>
-#include <asm/gpio.h>
-#include <debug_uart.h>
 #include <linux/bitops.h>

-#include <asm/armv8/mmu.h>
 static struct mm_region rk3308_mem_map[] = {
 	{
 		.virt = 0x0UL,
@@ -38,22 +35,6 @@ struct mm_region *mem_map = rk3308_mem_map;
 #define SGRF_BASE	0xff2b0000

 enum {
-	GPIO1C7_SHIFT		= 8,
-	GPIO1C7_MASK		= GENMASK(11, 8),
-	GPIO1C7_GPIO		= 0,
-	GPIO1C7_UART1_RTSN,
-	GPIO1C7_UART2_TX_M0,
-	GPIO1C7_SPI2_MOSI,
-	GPIO1C7_JTAG_TMS,
-
-	GPIO1C6_SHIFT		= 4,
-	GPIO1C6_MASK		= GENMASK(7, 4),
-	GPIO1C6_GPIO		= 0,
-	GPIO1C6_UART1_CTSN,
-	GPIO1C6_UART2_RX_M0,
-	GPIO1C6_SPI2_MISO,
-	GPIO1C6_JTAG_TCLK,
-
 	GPIO4D3_SHIFT           = 6,
 	GPIO4D3_MASK            = GENMASK(7, 6),
 	GPIO4D3_GPIO            = 0,
@@ -116,60 +97,12 @@ enum {
 	GPIO2A2_SEL_SRC_CTRL_SEL_PLUS	= 1,
 };

-enum {
-	IOVSEL3_CTRL_SHIFT	= 8,
-	IOVSEL3_CTRL_MASK	= BIT(8),
-	VCCIO3_SEL_BY_GPIO	= 0,
-	VCCIO3_SEL_BY_IOVSEL3,
-
-	IOVSEL3_SHIFT		= 3,
-	IOVSEL3_MASK		= BIT(3),
-	VCCIO3_3V3		= 0,
-	VCCIO3_1V8,
-};
-
-/*
- * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
- * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
- * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
- * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
- * for other usage.
- */
-
-#define GPIO0_A4	4
-
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
 	[BROM_BOOTSOURCE_SPINOR] = "/spi@ff4c0000/flash@0",
 	[BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
 };

-int rk_board_init(void)
-{
-	static struct rk3308_grf * const grf = (void *)GRF_BASE;
-	u32 val;
-	int ret;
-
-	ret = gpio_request(GPIO0_A4, "gpio0_a4");
-	if (ret < 0) {
-		printf("request for gpio0_a4 failed:%d\n", ret);
-		return 0;
-	}
-
-	gpio_direction_input(GPIO0_A4);
-
-	if (gpio_get_value(GPIO0_A4))
-		val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
-		      VCCIO3_1V8 << IOVSEL3_SHIFT;
-	else
-		val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
-		      VCCIO3_3V3 << IOVSEL3_SHIFT;
-	rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
-
-	gpio_free(GPIO0_A4);
-	return 0;
-}
-
 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 __weak void board_debug_uart_init(void)
 {
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -21,9 +21,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "rk3328"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config TPL_LDSCRIPT
 	default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"

--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -143,9 +143,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "rk3399"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config TPL_LDSCRIPT
 	default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"

--- a/arch/arm/mach-rockchip/rk3528/Kconfig
+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -0,0 +1,15 @@
+if ROCKCHIP_RK3528
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0xff370200
+
+config ROCKCHIP_STIMER_BASE
+	default 0xff620000
+
+config SYS_SOC
+	default "rk3528"
+
+config SYS_CONFIG_NAME
+	default "rk3528_common"
+
+endif
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -0,0 +1,11 @@
+GENERIC-RK3528
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3528-generic*
+F:	configs/generic-rk3528_defconfig
+
+RADXA-E20C
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	arch/arm/dts/rk3528-radxa-e20c*
+F:	configs/radxa-e20c-rk3528_defconfig
--- a/arch/arm/mach-rockchip/rk3528/Makefile
+++ b/arch/arm/mach-rockchip/rk3528/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += rk3528.o
+obj-y += clk_rk3528.o
+obj-y += syscon_rk3528.o
--- a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/cru_rk3528.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+				DM_DRIVER_GET(rockchip_rk3528_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	return RK3528_CRU_BASE;
+}
--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define FIREWALL_DDR_BASE		0xff2e0000
+#define FW_DDR_MST6_REG			0x58
+#define FW_DDR_MST7_REG			0x5c
+#define FW_DDR_MST14_REG		0x78
+#define FW_DDR_MST16_REG		0x80
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
+	[BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
+};
+
+static struct mm_region rk3528_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0xfc000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0xfc000000UL,
+		.phys = 0xfc000000UL,
+		.size = 0x04000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = rk3528_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+int arch_cpu_init(void)
+{
+	u32 val;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD))
+		return 0;
+
+	/* Set the emmc to access ddr memory */
+	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+	/* Set the fspi to access ddr memory */
+	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+
+	/* Set the sdmmc to access ddr memory */
+	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+
+	/* Set the usb to access ddr memory */
+	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+	writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+
+	return 0;
+}
+
+#define HP_TIMER_BASE			CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG			0x04
+#define TIMER_EN			BIT(0)
+#define HP_LOAD_COUNT0_REG		0x14
+#define HP_LOAD_COUNT1_REG		0x18
+
+void rockchip_stimer_init(void)
+{
+	u32 reg;
+
+	if (!IS_ENABLED(CONFIG_XPL_BUILD))
+		return;
+
+	reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+	if (reg & TIMER_EN)
+		return;
+
+	asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+	writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+#define RK3528_OTP_CPU_CODE_OFFSET		0x02
+#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET		0x28
+
+int checkboard(void)
+{
+	u8 cpu_code[2], chip_type;
+	struct udevice *dev;
+	char suffix[2];
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+		return 0;
+
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_DRIVER_GET(rockchip_otp), &dev);
+	if (ret) {
+		log_debug("Could not find otp device, ret=%d\n", ret);
+		return 0;
+	}
+
+	/* cpu-code: SoC model, e.g. 0x35 0x28 */
+	ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+	if (ret < 0) {
+		log_debug("Could not read cpu-code, ret=%d\n", ret);
+		return 0;
+	}
+
+	ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1);
+	if (ret < 0) {
+		log_debug("Could not read chip type, ret=%d\n", ret);
+		return 0;
+	}
+
+	suffix[0] = chip_type != 0x1 ? 'A' : '\0';
+	suffix[1] = '\0';
+
+	printf("SoC:   RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
+	return 0;
+}
--- a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3528_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_syscon) = {
+	.name = "rockchip_rk3528_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3528_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind = dm_scan_fdt_dev,
+#endif
+};
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -5,7 +5,6 @@ choice

 config TARGET_EVB_RK3568
 	bool "RK3568 evaluation board"
-	select BOARD_LATE_INIT
 	help
 	  RK3568 EVB is a evaluation board for Rockchp RK3568.

@@ -71,9 +70,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "rk3568"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config TEXT_BASE
 	default 0x00a00000

@@ -87,4 +83,7 @@ source "board/qnap/ts433/Kconfig"
 source "board/radxa/zero3-rk3566/Kconfig"
 source "board/xunlong/orangepi-3b-rk3566/Kconfig"

+config SYS_CONFIG_NAME
+	default "rk3568_common"
+
 endif
--- a/arch/arm/mach-rockchip/rk3576/Kconfig
+++ b/arch/arm/mach-rockchip/rk3576/Kconfig
@@ -0,0 +1,23 @@
+if ROCKCHIP_RK3576
+
+config TARGET_ROC_PC_RK3576
+	bool "Firefly ROC-RK3576-PC"
+	help
+	  ROC-RK3576-PC is a single board computer from Firefly
+	  using the Rockchip RK3576.
+
+config ROCKCHIP_BOOT_MODE_REG
+	default 0x26024040
+
+config ROCKCHIP_STIMER_BASE
+	default 0x27400000
+
+config SYS_SOC
+	default "rk3576"
+
+source board/firefly/roc-pc-rk3576/Kconfig
+
+config SYS_CONFIG_NAME
+	default "rk3576_common"
+
+endif
--- a/arch/arm/mach-rockchip/rk3576/Makefile
+++ b/arch/arm/mach-rockchip/rk3576/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += rk3576.o
+obj-y += clk_rk3576.o
+obj-y += syscon_rk3576.o
--- a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/cru_rk3576.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+				DM_DRIVER_GET(rockchip_rk3576_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	return (void *)RK3576_CRU_BASE;
+}
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define SYS_GRF_BASE		0x2600A000
+#define SYS_GRF_SOC_CON2	0x0008
+#define SYS_GRF_SOC_CON7	0x001c
+#define SYS_GRF_SOC_CON11	0x002c
+#define SYS_GRF_SOC_CON12	0x0030
+
+#define GPIO0_IOC_BASE		0x26040000
+#define GPIO0B_PULL_L		0x0024
+#define GPIO0B_IE_L		0x002C
+
+#define SYS_SGRF_BASE		0x26004000
+#define SYS_SGRF_SOC_CON14	0x0058
+#define SYS_SGRF_SOC_CON15	0x005C
+#define SYS_SGRF_SOC_CON20	0x0070
+
+#define FW_SYS_SGRF_BASE	0x26005000
+#define SGRF_DOMAIN_CON1	0x4
+#define SGRF_DOMAIN_CON2	0x8
+#define SGRF_DOMAIN_CON3	0xc
+#define SGRF_DOMAIN_CON4	0x10
+#define SGRF_DOMAIN_CON5	0x14
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
+	[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+};
+
+static struct mm_region rk3576_mem_map[] = {
+	{
+		/* I/O area */
+		.virt = 0x20000000UL,
+		.phys = 0x20000000UL,
+		.size = 0xb080000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* PMU_SRAM, CBUF, SYSTEM_SRAM */
+		.virt = 0x3fe70000UL,
+		.phys = 0x3fe70000UL,
+		.size = 0x190000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* MSCH_DDR_PORT */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* PCIe 0+1 */
+		.virt = 0x900000000UL,
+		.phys = 0x900000000UL,
+		.size = 0x100800000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = rk3576_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+#define HP_TIMER_BASE			CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG			0x04
+#define TIMER_EN			BIT(0)
+#define HP_LOAD_COUNT0_REG		0x14
+#define HP_LOAD_COUNT1_REG		0x18
+
+void rockchip_stimer_init(void)
+{
+	u32 reg;
+
+	if (!IS_ENABLED(CONFIG_XPL_BUILD))
+		return;
+
+	reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+	if (reg & TIMER_EN)
+		return;
+
+	asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+	writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+int arch_cpu_init(void)
+{
+	u32 val;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD))
+		return 0;
+
+	/* Set the emmc to access ddr memory */
+	val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+	writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+
+	/* Set the sdmmc0 to access ddr memory */
+	val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+	writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+
+	/* Set the UFS to access ddr memory */
+	val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+	writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+
+	/* Set the fspi0 and fspi1 to access ddr memory */
+	val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+	writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+
+	/* Set the decom to access ddr memory */
+	val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+	writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+
+	/*
+	 * Set the GPIO0B0~B3 pull up and input enable.
+	 * Keep consistent with other IO.
+	 */
+	writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
+	writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
+
+	/*
+	 * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
+	 * keep consistent with other pwm.
+	 */
+	writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
+
+	/* Enable noc slave response timeout */
+	writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
+	writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
+
+	/*
+	 * Enable cci channels for below module AXI R/W
+	 * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
+	 */
+	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
+
+	return 0;
+}
--- a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3576_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3576-pmu1-grf",  .data = ROCKCHIP_SYSCON_PMUGRF },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_syscon) = {
+	.name = "rockchip_rk3576_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3576_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind = dm_scan_fdt_dev,
+#endif
+};
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -2,13 +2,11 @@ if ROCKCHIP_RK3588

 config TARGET_EVB_RK3588
 	bool "Rockchip EVB1 v10"
-	select BOARD_LATE_INIT
 	help
 	  RK3588 EVB is a evaluation board for Rockchp RK3588.

 config TARGET_CM3588_NAS_RK3588
 	bool "FriendlyElec CM3588 NAS"
-	select BOARD_LATE_INIT
 	help
 	  The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based
 	  on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board.
@@ -31,7 +29,6 @@ config TARGET_CM3588_NAS_RK3588

 config TARGET_GENBOOK_CM5_RK3588
 	bool "Cool Pi CM5 GenBook"
-	select BOARD_LATE_INIT
 	help
 	  GeenBook is a notebook based on Rockchip RK3588, and works as a carrier
 	  board connect with CM5 SOM.
@@ -49,7 +46,6 @@ config TARGET_GENBOOK_CM5_RK3588

 config TARGET_JAGUAR_RK3588
 	bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
-	select BOARD_LATE_INIT
 	help
 	  The SBC-RK3588-AMR is a Single Board Computer designed by
 	  Theobroma Systems for autonomous mobile robots.
@@ -76,7 +72,6 @@ config TARGET_JAGUAR_RK3588

 config TARGET_KHADAS_EDGE2_RK3588
 	bool "Khadas Edge2 RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer)
 	  by Khadas.
@@ -98,7 +93,6 @@ config TARGET_KHADAS_EDGE2_RK3588

 config TARGET_NANOPCT6_RK3588
 	bool "FriendlyElec NanoPC-T6 RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec.

@@ -143,7 +137,6 @@ config TARGET_NANOPCT6_RK3588

 config TARGET_NANOPI_R6C_RK3588S
 	bool "FriendlyElec NanoPi R6C"
-	select BOARD_LATE_INIT
 	help
 	  The NanoPi R6C is a SBC by FriendlyElec based on the Rockchip
 	  RK3588s.
@@ -155,7 +148,6 @@ config TARGET_NANOPI_R6C_RK3588S

 config TARGET_NANOPI_R6S_RK3588S
 	bool "FriendlyElec NanoPi R6S"
-	select BOARD_LATE_INIT
 	help
 	  The NanoPi R6S is a SBC by FriendlyElec based on the Rockchip
 	  RK3588s.
@@ -167,7 +159,6 @@ config TARGET_NANOPI_R6S_RK3588S

 config TARGET_NOVA_RK3588
 	bool "Indiedroid Nova RK3588"
-	select BOARD_LATE_INIT
 	help
 	  Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
 	  It comes in configurations from 4GB of RAM to 16GB of RAM,
@@ -176,13 +167,11 @@ config TARGET_NOVA_RK3588

 config TARGET_ODROID_M2_RK3588S
 	bool "Hardkernel ODROID-M2"
-	select BOARD_LATE_INIT
 	help
 	  Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC.

 config TARGET_RK3588_NEU6
 	bool "Edgeble Neural Compute Module 6(Neu6) SoM"
-	select BOARD_LATE_INIT
 	help
 	  Neu6A:
 	  Neural Compute Module 6A(Neu6A) is a 96boards SoM-CB compute module
@@ -204,7 +193,6 @@ config TARGET_RK3588_NEU6

 config TARGET_ROCK5A_RK3588
 	bool "Radxa ROCK5A RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  Radxa ROCK5A is a Rockchip RK3588S based SBC (Single Board Computer)
 	  by Radxa.
@@ -231,7 +219,6 @@ config TARGET_ROCK5A_RK3588

 config TARGET_ROCK5B_RK3588
 	bool "Radxa ROCK5B RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  Radxa ROCK5B is a Rockchip RK3588 based SBC (Single Board Computer)
 	  by Radxa.
@@ -256,7 +243,6 @@ config TARGET_ROCK5B_RK3588

 config TARGET_ROCK_5_ITX_RK3588
 	bool "Radxa ROCK-5-ITX RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board
 	  Computer) by Radxa in the ITX formfactor.
@@ -284,7 +270,6 @@ config TARGET_ROCK_5_ITX_RK3588

 config TARGET_ROCK_5C_RK3588S
 	bool "Radxa ROCK 5C RK3588S2 board"
-	select BOARD_LATE_INIT
 	help
 	  Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer.

@@ -304,7 +289,6 @@ config TARGET_ROCK_5C_RK3588S

 config TARGET_SIGE7_RK3588
 	bool "ArmSoM Sige7 RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
 	  by ArmSoM.
@@ -329,14 +313,12 @@ config TARGET_SIGE7_RK3588

 config TARGET_QUARTZPRO64_RK3588
 	bool "Pine64 QuartzPro64 RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
 	  Computer) by Pine64.

 config TARGET_TIGER_RK3588
 	bool "Theobroma Systems SOM-RK3588-Q7 (Tiger)"
-	select BOARD_LATE_INIT
 	help
 	  The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
 	  connector) system-on-module from Theobroma Systems, featuring the
@@ -366,7 +348,6 @@ config TARGET_TIGER_RK3588

 config TARGET_TURINGRK1_RK3588
 	bool "Turing Machines RK1 RK3588 board"
-	select BOARD_LATE_INIT
 	help
 	  The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.

@@ -389,7 +370,6 @@ config TARGET_TURINGRK1_RK3588

 config TARGET_TOYBRICK_RK3588
 	bool "Toybrick TB-RK3588X board"
-	select BOARD_LATE_INIT
 	help
 	  Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board.
 	  TB-RK3588X adopts core board and mainboard design. The core board is connected
@@ -420,9 +400,6 @@ config ROCKCHIP_STIMER_BASE
 config SYS_SOC
 	default "rk3588"

-config ROCKCHIP_COMMON_STACK_ADDR
-	default y
-
 config TEXT_BASE
 	default 0x00a00000

@@ -447,4 +424,7 @@ source "board/rockchip/toybrick_rk3588/Kconfig"
 source "board/theobroma-systems/jaguar_rk3588/Kconfig"
 source "board/theobroma-systems/tiger_rk3588/Kconfig"

+config SYS_CONFIG_NAME
+	default "rk3588_common"
+
 endif
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -116,18 +116,25 @@ void board_debug_uart_init(void)
 }

 #ifdef CONFIG_XPL_BUILD
+
+#define HP_TIMER_BASE			CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG			0x04
+#define TIMER_EN			BIT(0)
+#define HP_LOAD_COUNT0_REG		0x14
+#define HP_LOAD_COUNT1_REG		0x18
+
 void rockchip_stimer_init(void)
 {
 	/* If Timer already enabled, don't re-init it */
-	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+	u32 reg = readl(HP_TIMER_BASE + HP_CTRL_REG);

-	if (reg & 0x1)
+	if (reg & TIMER_EN)
 		return;

-	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
-	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
-	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+	asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+	writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+	writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
 }
 #endif

--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,7 +110,9 @@ static int rockchip_dram_init_banksize(void)
 	u8 i, j;

 	if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
-	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
+	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
+	    !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
 		return -ENOTSUPP;

 	if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
@@ -181,9 +183,9 @@ static int rockchip_dram_init_banksize(void)
 		 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
 		 * have it, so force this space as reserved.
 		 */
-		if (start_addr < SZ_2M) {
-			size -= SZ_2M - start_addr;
-			start_addr = SZ_2M;
+		if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {
+			size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
+			start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
 		}

 		/*
@@ -228,7 +230,7 @@ static int rockchip_dram_init_banksize(void)
 					return -EINVAL;
 				}

-				size -= rsrv_end - start_addr;
+				size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
 				start_addr = rsrv_end;
 				break;
 			}
@@ -301,8 +303,8 @@ int dram_init_banksize(void)
 	debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
 	      ret);

-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
+	/* Reserve 2M for ATF bl31 */
+	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;

 	/* Add usable memory beyond the blob of space for peripheral near 4GB */
--- a/board/firefly/roc-pc-rk3576/Kconfig
+++ b/board/firefly/roc-pc-rk3576/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROC_PC_RK3576
+
+config SYS_BOARD
+	default "roc-pc-rk3576"
+
+config SYS_VENDOR
+	default "firefly"
+
+config SYS_CONFIG_NAME
+	default "roc-pc-rk3576"
+
+endif
--- a/board/firefly/roc-pc-rk3576/MAINTAINERS
+++ b/board/firefly/roc-pc-rk3576/MAINTAINERS
@@ -0,0 +1,7 @@
+ROC-RK3576-PC
+M:	Heiko Stuebner <heiko@sntech.de>
+S:	Maintained
+F:	board/firefly/roc-pc-rk3576
+F:	include/configs/roc-pc-rk3576.h
+F:	configs/roc-pc-rk3576_defconfig
+F:	arch/arm/dts/rk3576-roc-pc*
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -7,6 +7,12 @@ F:      configs/evb-rk3328_defconfig
 F:      arch/arm/dts/rk3328-evb.dts
 F:      arch/arm/dts/rk3328-evb-u-boot.dtsi

+GENERIC-RK3328
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/generic-rk3328_defconfig
+F:	arch/arm/dts/rk3328-generic*
+
 NANOPI-R2C-RK3328
 M:      Tianling Shen <cnsztl@gmail.com>
 S:      Maintained
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -14,6 +14,12 @@ S:      Maintained
 F:	configs/eaidk-610-rk3399_defconfig
 F:	arch/arm/dts/rk3399-eaidk-610*

+GENERIC-RK3399
+M:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/generic-rk3399_defconfig
+F:	arch/arm/dts/rk3399-generic*
+
 KHADAS-EDGE
 M:	Nick Xie <nick@khadas.com>
 S:	Maintained
--- a/board/theobroma-systems/common/Makefile
+++ b/board/theobroma-systems/common/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2025 Cherry Embedded Solutions GmbH
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifneq ($(CONFIG_XPL_BUILD),y)
+obj-y	+= common.o
+endif
--- a/board/theobroma-systems/jaguar_rk3588/Makefile
+++ b/board/theobroma-systems/jaguar_rk3588/Makefile
@@ -5,6 +5,3 @@
 #

 obj-y += jaguar_rk3588.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y	+= ../common/common.o
-endif
--- a/board/theobroma-systems/puma_rk3399/Makefile
+++ b/board/theobroma-systems/puma_rk3399/Makefile
@@ -5,6 +5,3 @@
 #

 obj-y	+= puma-rk3399.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y	+= ../common/common.o
-endif
--- a/board/theobroma-systems/ringneck_px30/Makefile
+++ b/board/theobroma-systems/ringneck_px30/Makefile
@@ -5,6 +5,3 @@
 #

 obj-y	+= ringneck-px30.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y	+= ../common/common.o
-endif
--- a/board/theobroma-systems/tiger_rk3588/Makefile
+++ b/board/theobroma-systems/tiger_rk3588/Makefile
@@ -5,6 +5,3 @@
 #

 obj-y += tiger_rk3588.o
-ifneq ($(CONFIG_XPL_BUILD),y)
-obj-y	+= ../common/common.o
-endif
--- a/configs/generic-rk3328_defconfig
+++ b/configs/generic-rk3328_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-generic"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_ADC is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
--- a/configs/generic-rk3399_defconfig
+++ b/configs/generic-rk3399_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-generic"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+# CONFIG_ROCKCHIP_IODOMAIN is not set
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
--- a/configs/generic-rk3528_defconfig
+++ b/configs/generic-rk3528_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ERRNO_STR=y
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -28,6 +28,8 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
 CONFIG_SPL_ATF=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MISC=y
@@ -35,6 +37,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -22,6 +22,8 @@ CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ATF=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MISC=y
@@ -29,6 +31,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_ROCKUSB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIVE=y
--- a/configs/radxa-e20c-rk3528_defconfig
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DEFAULT_DEVICE_TREE="rockchip/px30-ringneck-haikou"
+CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_PX30=y
 # CONFIG_TPL_ROCKCHIP_COMMON_BOARD is not set
--- a/configs/roc-pc-rk3576_defconfig
+++ b/configs/roc-pc-rk3576_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-roc-pc"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_TARGET_ROC_PC_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0x40c00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-roc-pc.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -66,6 +66,7 @@ List of mainline supported Rockchip boards:
     - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328)
     - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328)
     - FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328)
+     - Generic RK3328 (generic-rk3328)
     - Pine64 Rock64 (rock64-rk3328)
     - Radxa ROCK Pi E (rock-pi-e-rk3328)
     - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328)
@@ -83,6 +84,7 @@ List of mainline supported Rockchip boards:
     - FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
     - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
     - FriendlyARM NanoPi NEO4 (nanopi-neo4-rk3399)
+     - Generic RK3399 (generic-rk3399)
     - Google Bob (chromebook_bob)
     - Google Kevin (chromebook_kevin)
     - Khadas Edge (khadas-edge-rk3399)
@@ -97,6 +99,10 @@ List of mainline supported Rockchip boards:
     - Rockchip Evb-RK3399 (evb_rk3399)
     - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)

+* rk3528
+     - Generic RK3528 (generic-rk3528)
+     - Radxa E20C (radxa-e20c-rk3528)
+
 * rk3566
     - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
     - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
@@ -126,6 +132,9 @@ List of mainline supported Rockchip boards:
     - Radxa ROCK 3A (rock-3a-rk3568)
     - Radxa ROCK 3B (rock-3b-rk3568)

+* rk3576
+     - Firefly ROC-RK3576-PC (roc-pc-rk3576)
+
 * rk3588
     - ArmSoM Sige7 (sige7-rk3588)
     - Rockchip EVB (evb-rk3588)
@@ -258,6 +267,15 @@ To build rk3399 boards:
        make evb-rk3399_defconfig
        make CROSS_COMPILE=aarch64-linux-gnu-

+To build rk3528 boards:
+
+.. code-block:: bash
+
+        export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf
+        export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin
+        make generic-rk3528_defconfig
+        make CROSS_COMPILE=aarch64-linux-gnu-
+
 To build rk3568 boards:

 .. code-block:: bash
@@ -268,6 +286,15 @@ To build rk3568 boards:
        make evb-rk3568_defconfig
        make CROSS_COMPILE=aarch64-linux-gnu-

+To build rk3576 boards:
+
+.. code-block:: bash
+
+        export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf
+        export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin
+        make roc-pc-rk3576_defconfig
+        make CROSS_COMPILE=aarch64-linux-gnu-
+
 To build rk3588 boards:

 .. code-block:: bash
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -339,6 +339,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = {
 	.stop = rockchip_saradc_stop_v1,
 };

+static const struct rockchip_saradc_data rk3528_saradc_data = {
+	.num_bits = 10,
+	.num_channels = 4,
+	.clk_rate = 1000000,
+	.channel_data = rockchip_saradc_channel_data_v2,
+	.start_channel = rockchip_saradc_start_channel_v2,
+};
+
 static const struct rockchip_saradc_data rk3588_saradc_data = {
 	.num_bits = 12,
 	.num_channels = 8,
@@ -354,6 +362,8 @@ static const struct udevice_id rockchip_saradc_ids[] = {
 	  .data = (ulong)&rk3066_tsadc_data },
 	{ .compatible = "rockchip,rk3399-saradc",
 	  .data = (ulong)&rk3399_saradc_data },
+	{ .compatible = "rockchip,rk3528-saradc",
+	  .data = (ulong)&rk3528_saradc_data },
 	{ .compatible = "rockchip,rk3588-saradc",
 	  .data = (ulong)&rk3588_saradc_data },
 	{ }
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -15,7 +15,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
 obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
 obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -309,9 +309,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
 	 * When power on or changing PLL setting,
 	 * we must force PLL into slow mode to ensure output stable clock.
 	 */
-	rk_clrsetreg(base + pll->mode_offset,
-		     pll->mode_mask << pll->mode_shift,
-		     RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+		rk_clrsetreg(base + pll->mode_offset,
+			     pll->mode_mask << pll->mode_shift,
+			     RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+	}

 	/* Power down */
 	rk_setreg(base + pll->con_offset + 0x4,
@@ -345,8 +347,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
 	while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
 		udelay(1);

-	rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
-		     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+		rk_clrsetreg(base + pll->mode_offset,
+			     pll->mode_mask << pll->mode_shift,
+			     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+	}
 	debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
 	      pll, readl(base + pll->con_offset),
 	      readl(base + pll->con_offset + 0x4),
@@ -362,12 +367,18 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
 	u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
 	u32 con = 0, shift, mask;
 	ulong rate;
+	int mode;

 	con = readl(base + pll->mode_offset);
 	shift = pll->mode_shift;
 	mask = pll->mode_mask << shift;

-	switch ((con & mask) >> shift) {
+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
+		mode = (con & mask) >> shift;
+	else
+		mode = RKCLK_PLL_MODE_NORMAL;
+
+	switch (mode) {
 	case RKCLK_PLL_MODE_SLOW:
 		return OSC_HZ;
 	case RKCLK_PLL_MODE_NORMAL:
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -361,6 +361,13 @@ static const struct rockchip_otp_data rk3568_data = {
 	.block_size = 2,
 };

+static const struct rockchip_otp_data rk3576_data = {
+	.read = rockchip_rk3588_otp_read,
+	.offset = 0x700,
+	.size = 0x100,
+	.block_size = 4,
+};
+
 static const struct rockchip_otp_data rk3588_data = {
 	.read = rockchip_rk3588_otp_read,
 	.offset = 0xC00,
@@ -383,10 +390,18 @@ static const struct udevice_id rockchip_otp_ids[] = {
 		.compatible = "rockchip,rk3308-otp",
 		.data = (ulong)&px30_data,
 	},
+	{
+		.compatible = "rockchip,rk3528-otp",
+		.data = (ulong)&rk3568_data,
+	},
 	{
 		.compatible = "rockchip,rk3568-otp",
 		.data = (ulong)&rk3568_data,
 	},
+	{
+		.compatible = "rockchip,rk3576-otp",
+		.data = (ulong)&rk3576_data,
+	},
 	{
 		.compatible = "rockchip,rk3588-otp",
 		.data = (ulong)&rk3588_data,
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -171,6 +171,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
 static const struct udevice_id rockchip_dwmmc_ids[] = {
 	{ .compatible = "rockchip,rk2928-dw-mshc" },
 	{ .compatible = "rockchip,rk3288-dw-mshc" },
+	{ .compatible = "rockchip,rk3576-dw-mshc" },
 	{ }
 };

--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -50,6 +50,10 @@
 #define DWCMSHC_EMMC_EMMC_CTRL		0x52c
 #define DWCMSHC_CARD_IS_EMMC		BIT(0)
 #define DWCMSHC_ENHANCED_STROBE		BIT(8)
+#define DWCMSHC_EMMC_AT_CTRL		0x540
+#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN	BIT(16)
+#define EMMC_AT_CTRL_PRE_CHANGE_DLY	17
+#define EMMC_AT_CTRL_POST_CHANGE_DLY	19
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
 #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
 #define DWCMSHC_EMMC_DLL_RXCLK		0x804
@@ -156,6 +160,9 @@ struct sdhci_data {
 	u32 flags;
 	u8 hs200_txclk_tapnum;
 	u8 hs400_txclk_tapnum;
+	u8 hs400_cmdout_tapnum;
+	u8 hs400_strbin_tapnum;
+	u8 ddr50_strbin_delay_num;
 };

 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -323,6 +330,11 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
 		udelay(1);
 		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);

+		extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
+			0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
+			EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
+		sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
+
 		/* Init DLL settings */
 		extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
 			DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
@@ -348,7 +360,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
 			extra = DLL_CMDOUT_SRC_CLK_NEG |
 				DLL_CMDOUT_BOTH_CLK_EDGE |
 				DWCMSHC_EMMC_DLL_DLYENA |
-				DLL_CMDOUT_TAPNUM_90_DEGREES |
+				data->hs400_cmdout_tapnum |
 				DLL_CMDOUT_TAPNUM_FROM_SW;
 			sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
 		}
@@ -360,7 +372,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);

 		extra = DWCMSHC_EMMC_DLL_DLYENA |
-			DLL_STRBIN_TAPNUM_DEFAULT |
+			data->hs400_strbin_tapnum |
 			DLL_STRBIN_TAPNUM_FROM_SW;
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 	} else {
@@ -380,7 +392,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
 		 */
 		extra = DWCMSHC_EMMC_DLL_DLYENA |
 			DLL_STRBIN_DELAY_NUM_SEL |
-			DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+			data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
 		sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 	}

@@ -647,6 +659,17 @@ static const struct sdhci_data rk3399_data = {
 	.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
 };

+static const struct sdhci_data rk3528_data = {
+	.set_ios_post = rk3568_sdhci_set_ios_post,
+	.set_clock = rk3568_sdhci_set_clock,
+	.config_dll = rk3568_sdhci_config_dll,
+	.hs200_txclk_tapnum = 0xc,
+	.hs400_txclk_tapnum = 0x6,
+	.hs400_cmdout_tapnum = 0x6,
+	.hs400_strbin_tapnum = 0x3,
+	.ddr50_strbin_delay_num = 0xa,
+};
+
 static const struct sdhci_data rk3568_data = {
 	.set_ios_post = rk3568_sdhci_set_ios_post,
 	.set_clock = rk3568_sdhci_set_clock,
@@ -654,6 +677,20 @@ static const struct sdhci_data rk3568_data = {
 	.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
 	.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
 	.hs400_txclk_tapnum = 0x8,
+	.hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+	.hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+	.ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
+};
+
+static const struct sdhci_data rk3576_data = {
+	.set_ios_post = rk3568_sdhci_set_ios_post,
+	.set_clock = rk3568_sdhci_set_clock,
+	.config_dll = rk3568_sdhci_config_dll,
+	.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+	.hs400_txclk_tapnum = 0x7,
+	.hs400_cmdout_tapnum = 0x7,
+	.hs400_strbin_tapnum = 0x5,
+	.ddr50_strbin_delay_num = 0xa,
 };

 static const struct sdhci_data rk3588_data = {
@@ -662,6 +699,9 @@ static const struct sdhci_data rk3588_data = {
 	.config_dll = rk3568_sdhci_config_dll,
 	.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
 	.hs400_txclk_tapnum = 0x9,
+	.hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+	.hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+	.ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
 };

 static const struct udevice_id sdhci_ids[] = {
@@ -669,10 +709,18 @@ static const struct udevice_id sdhci_ids[] = {
 		.compatible = "arasan,sdhci-5.1",
 		.data = (ulong)&rk3399_data,
 	},
+	{
+		.compatible = "rockchip,rk3528-dwcmshc",
+		.data = (ulong)&rk3528_data,
+	},
 	{
 		.compatible = "rockchip,rk3568-dwcmshc",
 		.data = (ulong)&rk3568_data,
 	},
+	{
+		.compatible = "rockchip,rk3576-dwcmshc",
+		.data = (ulong)&rk3576_data,
+	},
 	{
 		.compatible = "rockchip,rk3588-dwcmshc",
 		.data = (ulong)&rk3588_data,
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1611,10 +1611,18 @@ static const struct udevice_id eqos_ids[] = {
 	},
 #endif
 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
+	{
+		.compatible = "rockchip,rk3528-gmac",
+		.data = (ulong)&eqos_rockchip_config
+	},
 	{
 		.compatible = "rockchip,rk3568-gmac",
 		.data = (ulong)&eqos_rockchip_config
 	},
+	{
+		.compatible = "rockchip,rk3576-gmac",
+		.data = (ulong)&eqos_rockchip_config
+	},
 	{
 		.compatible = "rockchip,rk3588-gmac",
 		.data = (ulong)&eqos_rockchip_config
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -50,6 +50,132 @@ struct rockchip_platform_data {
 	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
 	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))

+#define RK3528_VO_GRF_GMAC_CON		0x0018
+#define RK3528_VPU_GRF_GMAC_CON5	0x0018
+#define RK3528_VPU_GRF_GMAC_CON6	0x001c
+
+#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
+#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
+#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
+#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
+
+#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)
+
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)
+
+#define RK3528_GMAC1_CLK_SELECT_CRU	GRF_CLR_BIT(12)
+#define RK3528_GMAC1_CLK_SELECT_IO	GRF_BIT(12)
+
+#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)
+#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)
+#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)
+#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)
+
+#define RK3528_GMAC1_CLK_RGMII_DIV1	(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV5	(GRF_BIT(11) | GRF_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV50	(GRF_BIT(11) | GRF_CLR_BIT(10))
+
+#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)
+#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)
+#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)
+#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)
+
+static int rk3528_set_to_rgmii(struct udevice *dev,
+			       int tx_delay, int rx_delay)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+
+	regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);
+
+	regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));
+
+	regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON6,
+		     RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+		     RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+	return 0;
+}
+
+static int rk3528_set_to_rmii(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+
+	if (data->id == 1)
+		regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
+	else
+		regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON,
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII |
+			     RK3528_GMAC0_CLK_RMII_DIV2);
+
+	return 0;
+}
+
+static int rk3528_set_gmac_speed(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 val, reg;
+
+	switch (eqos->phy->speed) {
+	case SPEED_10:
+		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+			val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
+					      RK3528_GMAC0_CLK_RMII_DIV20;
+		else
+			val = RK3528_GMAC1_CLK_RGMII_DIV50;
+		break;
+	case SPEED_100:
+		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+			val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
+					      RK3528_GMAC0_CLK_RMII_DIV2;
+		else
+			val = RK3528_GMAC1_CLK_RGMII_DIV5;
+		break;
+	case SPEED_1000:
+		if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+			val = RK3528_GMAC1_CLK_RGMII_DIV1;
+		else
+			return -EINVAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	reg = data->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
+			      RK3528_VO_GRF_GMAC_CON;
+	regmap_write(data->grf, reg, val);
+
+	return 0;
+}
+
+static void rk3528_set_clock_selection(struct udevice *dev, bool enable)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 val;
+
+	if (data->id == 1) {
+		val = data->clock_input ? RK3528_GMAC1_CLK_SELECT_IO :
+					  RK3528_GMAC1_CLK_SELECT_CRU;
+		val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
+				RK3528_GMAC1_CLK_RMII_GATE;
+		regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, val);
+	} else {
+		val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
+			       RK3528_GMAC0_CLK_RMII_GATE;
+		regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, val);
+	}
+}
+
 #define RK3568_GRF_GMAC0_CON0		0x0380
 #define RK3568_GRF_GMAC0_CON1		0x0384
 #define RK3568_GRF_GMAC1_CON0		0x0388
@@ -134,6 +260,145 @@ static int rk3568_set_gmac_speed(struct udevice *dev)
 	return 0;
 }

+/* VCCIO0_1_3_IOC */
+#define RK3576_VCCIO0_1_3_IOC_CON2		0x6408
+#define RK3576_VCCIO0_1_3_IOC_CON3		0x640c
+#define RK3576_VCCIO0_1_3_IOC_CON4		0x6410
+#define RK3576_VCCIO0_1_3_IOC_CON5		0x6414
+
+#define RK3576_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(15)
+#define RK3576_GMAC_RXCLK_DLY_DISABLE		GRF_CLR_BIT(15)
+#define RK3576_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(7)
+#define RK3576_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3576_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0x7F, 0)
+
+/* SDGMAC_GRF */
+#define RK3576_GRF_GMAC_CON0			0x0020
+#define RK3576_GRF_GMAC_CON1			0x0024
+
+#define RK3576_GMAC_RMII_MODE			GRF_BIT(3)
+#define RK3576_GMAC_RGMII_MODE			GRF_CLR_BIT(3)
+
+#define RK3576_GMAC_CLK_SELECT_IO		GRF_BIT(7)
+#define RK3576_GMAC_CLK_SELECT_CRU		GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_RMII_DIV2		GRF_BIT(5)
+#define RK3576_GMAC_CLK_RMII_DIV20		GRF_CLR_BIT(5)
+
+#define RK3576_GMAC_CLK_RGMII_DIV1		\
+			(GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV5		\
+			(GRF_BIT(6) | GRF_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV50		\
+			(GRF_BIT(6) | GRF_CLR_BIT(5))
+
+#define RK3576_GMAC_CLK_RMII_GATE		GRF_BIT(4)
+#define RK3576_GMAC_CLK_RMII_NOGATE		GRF_CLR_BIT(4)
+
+static int rk3576_set_to_rgmii(struct udevice *dev,
+			       int tx_delay, int rx_delay)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 offset_con;
+
+	offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+				     RK3576_GRF_GMAC_CON0;
+
+	regmap_write(data->grf, offset_con, RK3576_GMAC_RGMII_MODE);
+
+	offset_con = data->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
+				     RK3576_VCCIO0_1_3_IOC_CON2;
+
+	/* m0 && m1 delay enabled */
+	regmap_write(data->php_grf, offset_con,
+		     DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+	regmap_write(data->php_grf, offset_con + 0x4,
+		     DELAY_ENABLE(RK3576, tx_delay, rx_delay));
+
+	/* m0 && m1 delay value */
+	regmap_write(data->php_grf, offset_con,
+		     RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+		     RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+	regmap_write(data->php_grf, offset_con + 0x4,
+		     RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
+		     RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
+
+	return 0;
+}
+
+static int rk3576_set_to_rmii(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 offset_con;
+
+	offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+				     RK3576_GRF_GMAC_CON0;
+
+	regmap_write(data->grf, offset_con, RK3576_GMAC_RMII_MODE);
+
+	return 0;
+}
+
+static int rk3576_set_gmac_speed(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+	u32 val = 0, offset_con;
+
+	switch (eqos->phy->speed) {
+	case SPEED_10:
+		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+			val = RK3576_GMAC_CLK_RMII_DIV20;
+		else
+			val = RK3576_GMAC_CLK_RGMII_DIV50;
+		break;
+	case SPEED_100:
+		if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+			val = RK3576_GMAC_CLK_RMII_DIV2;
+		else
+			val = RK3576_GMAC_CLK_RGMII_DIV5;
+		break;
+	case SPEED_1000:
+		if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+			val = RK3576_GMAC_CLK_RGMII_DIV1;
+		else
+			return -EINVAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+				     RK3576_GRF_GMAC_CON0;
+
+	regmap_write(data->grf, offset_con, val);
+
+	return 0;
+}
+
+static void rk3576_set_clock_selection(struct udevice *dev, bool enable)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct rockchip_platform_data *data = pdata->priv_pdata;
+
+	u32 val = data->clock_input ? RK3576_GMAC_CLK_SELECT_IO :
+				      RK3576_GMAC_CLK_SELECT_CRU;
+	u32 offset_con;
+
+	val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
+			RK3576_GMAC_CLK_RMII_GATE;
+
+	offset_con = data->id == 1 ? RK3576_GRF_GMAC_CON1 :
+				     RK3576_GRF_GMAC_CON0;
+
+	regmap_write(data->grf, offset_con, val);
+}
+
 #define RK3588_DELAY_ENABLE(id, tx, rx) \
 	(((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \
 	 ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id)))
@@ -269,6 +534,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
 }

 static const struct rk_gmac_ops rk_gmac_ops[] = {
+	{
+		.compatible = "rockchip,rk3528-gmac",
+		.set_to_rgmii = rk3528_set_to_rgmii,
+		.set_to_rmii = rk3528_set_to_rmii,
+		.set_gmac_speed = rk3528_set_gmac_speed,
+		.set_clock_selection = rk3528_set_clock_selection,
+		.regs = {
+			0xffbd0000, /* gmac0 */
+			0xffbe0000, /* gmac1 */
+			0x0, /* sentinel */
+		},
+	},
 	{
 		.compatible = "rockchip,rk3568-gmac",
 		.set_to_rgmii = rk3568_set_to_rgmii,
@@ -280,6 +557,18 @@ static const struct rk_gmac_ops rk_gmac_ops[] = {
 			0x0, /* sentinel */
 		},
 	},
+	{
+		.compatible = "rockchip,rk3576-gmac",
+		.set_to_rgmii = rk3576_set_to_rgmii,
+		.set_to_rmii = rk3576_set_to_rmii,
+		.set_gmac_speed = rk3576_set_gmac_speed,
+		.set_clock_selection = rk3576_set_clock_selection,
+		.regs = {
+			0x2a220000, /* gmac0 */
+			0x2a230000, /* gmac1 */
+			0x0, /* sentinel */
+		},
+	},
 	{
 		.compatible = "rockchip,rk3588-gmac",
 		.set_to_rgmii = rk3588_set_to_rgmii,
@@ -357,7 +646,8 @@ static int eqos_probe_resources_rk(struct udevice *dev)
 		goto err_free;
 	}

-	if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
+	if (device_is_compatible(dev, "rockchip,rk3588-gmac") ||
+	    device_is_compatible(dev, "rockchip,rk3576-gmac")) {
 		data->php_grf =
 			syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
 		if (IS_ERR(data->php_grf)) {
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -40,11 +40,13 @@ struct rockchip_usb2phy_port_cfg {
 struct rockchip_usb2phy_cfg {
 	unsigned int reg;
 	struct usb2phy_reg	clkout_ctl;
+	struct usb2phy_reg	clkout_ctl_phy;
 	const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
 };

 struct rockchip_usb2phy {
 	struct regmap *reg_base;
+	struct regmap *phy_base;
 	struct clk phyclk;
 	const struct rockchip_usb2phy_cfg *phy_cfg;
 };
@@ -165,6 +167,22 @@ static struct phy_ops rockchip_usb2phy_ops = {
 	.of_xlate = rockchip_usb2phy_of_xlate,
 };

+static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+					const struct usb2phy_reg **clkout_ctl)
+{
+	struct udevice *parent = dev_get_parent(clk->dev);
+	struct rockchip_usb2phy *priv = dev_get_priv(parent);
+	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+	if (priv->phy_cfg->clkout_ctl_phy.enable) {
+		*base = priv->phy_base;
+		*clkout_ctl = &phy_cfg->clkout_ctl_phy;
+	} else {
+		*base = priv->reg_base;
+		*clkout_ctl = &phy_cfg->clkout_ctl;
+	}
+}
+
 /**
 * round_rate() - Adjust a rate to the exact rate a clock can provide.
 * @clk:	The clock to manipulate.
@@ -185,13 +203,14 @@ ulong rockchip_usb2phy_clk_round_rate(struct clk *clk, ulong rate)
 */
 int rockchip_usb2phy_clk_enable(struct clk *clk)
 {
-	struct udevice *parent = dev_get_parent(clk->dev);
-	struct rockchip_usb2phy *priv = dev_get_priv(parent);
-	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+	const struct usb2phy_reg *clkout_ctl;
+	struct regmap *base;
+
+	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);

 	/* turn on 480m clk output if it is off */
-	if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
-		property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
+	if (!property_enabled(base, clkout_ctl)) {
+		property_enable(base, clkout_ctl, true);

 		/* waiting for the clk become stable */
 		usleep_range(1200, 1300);
@@ -208,12 +227,13 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
 */
 int rockchip_usb2phy_clk_disable(struct clk *clk)
 {
-	struct udevice *parent = dev_get_parent(clk->dev);
-	struct rockchip_usb2phy *priv = dev_get_priv(parent);
-	const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+	const struct usb2phy_reg *clkout_ctl;
+	struct regmap *base;
+
+	rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);

 	/* turn off 480m clk output */
-	property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
+	property_enable(base, clkout_ctl, false);

 	return 0;
 }
@@ -281,7 +301,10 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
 		return ret;
 	}

-	return 0;
+	if (priv->phy_cfg->clkout_ctl_phy.enable)
+		ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0);
+
+	return ret;
 }

 static int rockchip_usb2phy_bind(struct udevice *dev)
@@ -389,6 +412,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
 	{ /* sentinel */ }
 };

+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+	{
+		.reg		= 0xffdf0000,
+		.clkout_ctl_phy	= { 0x041c, 7, 2, 0, 0x27 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x004c, 1, 0, 2, 1 },
+			},
+			[USB2PHY_PORT_HOST] = {
+				.phy_sus	= { 0x005c, 1, 0, 2, 1 },
+			}
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
 	{
 		.reg		= 0xfe8a0000,
@@ -470,6 +509,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
 		.compatible = "rockchip,rk3399-usb2phy",
 		.data = (ulong)&rk3399_usb2phy_cfgs,
 	},
+	{
+		.compatible = "rockchip,rk3528-usb2phy",
+		.data = (ulong)&rk3528_phy_cfgs,
+	},
 	{
 		.compatible = "rockchip,rk3568-usb2phy",
 		.data = (ulong)&rk3568_phy_cfgs,
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
 obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
 obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
--- a/drivers/pinctrl/rockchip/pinctrl-rk3528.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, mask;
+	u8 bit;
+	u32 data, rmask;
+
+	regmap = priv->regmap_base;
+	reg = bank->iomux[iomux_num].offset;
+	if ((pin % 8) >= 4)
+		reg += 0x4;
+	bit = (pin % 4) * 4;
+	mask = 0xf;
+
+	data = (mask << (bit + 16));
+	rmask = data | (data >> 16);
+	data |= (mux & mask) << bit;
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_DRV_BITS_PER_PIN		8
+#define RK3528_DRV_PINS_PER_REG		2
+#define RK3528_DRV_GPIO0_OFFSET		0x100
+#define RK3528_DRV_GPIO1_OFFSET		0x20120
+#define RK3528_DRV_GPIO2_OFFSET		0x30160
+#define RK3528_DRV_GPIO3_OFFSET		0x20190
+#define RK3528_DRV_GPIO4_OFFSET		0x101C0
+
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+
+	if (bank->bank_num == 0) {
+		*reg = RK3528_DRV_GPIO0_OFFSET;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3528_DRV_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3528_DRV_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3528_DRV_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3528_DRV_GPIO4_OFFSET;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3528_DRV_PINS_PER_REG;
+	*bit *= RK3528_DRV_BITS_PER_PIN;
+}
+
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data, rmask;
+	u8 bit;
+	int drv = (1 << (strength + 1)) - 1;
+
+	rk3528_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (drv << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_PULL_BITS_PER_PIN		2
+#define RK3528_PULL_PINS_PER_REG		8
+#define RK3528_PULL_GPIO0_OFFSET		0x200
+#define RK3528_PULL_GPIO1_OFFSET		0x20210
+#define RK3528_PULL_GPIO2_OFFSET		0x30220
+#define RK3528_PULL_GPIO3_OFFSET		0x20230
+#define RK3528_PULL_GPIO4_OFFSET		0x10240
+
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					 int pin_num, struct regmap **regmap,
+					 int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+
+	if (bank->bank_num == 0) {
+		*reg = RK3528_PULL_GPIO0_OFFSET;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3528_PULL_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3528_PULL_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3528_PULL_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3528_PULL_GPIO4_OFFSET;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3528_PULL_PINS_PER_REG;
+	*bit *= RK3528_PULL_BITS_PER_PIN;
+}
+
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data, rmask;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -EOPNOTSUPP;
+
+	rk3528_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = bank->pull_type[pin_num / 8];
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (ret << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_SMT_BITS_PER_PIN		1
+#define RK3528_SMT_PINS_PER_REG		8
+#define RK3528_SMT_GPIO0_OFFSET		0x400
+#define RK3528_SMT_GPIO1_OFFSET		0x20410
+#define RK3528_SMT_GPIO2_OFFSET		0x30420
+#define RK3528_SMT_GPIO3_OFFSET		0x20430
+#define RK3528_SMT_GPIO4_OFFSET		0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+					   int pin_num,
+					   struct regmap **regmap,
+					   int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+
+	if (bank->bank_num == 0) {
+		*reg = RK3528_SMT_GPIO0_OFFSET;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3528_SMT_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3528_SMT_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3528_SMT_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3528_SMT_GPIO4_OFFSET;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3528_SMT_PINS_PER_REG;
+	*bit *= RK3528_SMT_BITS_PER_PIN;
+
+	return 0;
+}
+
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data, rmask;
+	u8 bit;
+
+	rk3528_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (enable << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+	PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0, 0, 0, 0),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x20020, 0x20028, 0x20030, 0x20038),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x30040, 0, 0, 0),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x20060, 0x20068, 0x20070, 0),
+	PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    IOMUX_WIDTH_4BIT,
+				    0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+	.pin_banks		= rk3528_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3528_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.set_mux		= rk3528_set_mux,
+	.set_pull		= rk3528_set_pull,
+	.set_drive		= rk3528_set_drive,
+	.set_schmitt		= rk3528_set_schmitt,
+};
+
+static const struct udevice_id rk3528_pinctrl_ids[] = {
+	{
+		.compatible = "rockchip,rk3528-pinctrl",
+		.data = (ulong)&rk3528_pin_ctrl
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
+	.name		= "rockchip_rk3528_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk3528_pinctrl_ids,
+	.priv_auto	= sizeof(struct rockchip_pinctrl_priv),
+	.ops		= &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.probe		= rockchip_pinctrl_probe,
+};
--- a/drivers/pinctrl/rockchip/pinctrl-rk3576.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+	int iomux_num = (pin / 8);
+	struct regmap *regmap;
+	int reg, mask;
+	u8 bit;
+	u32 data, rmask;
+
+	regmap = priv->regmap_base;
+	reg = bank->iomux[iomux_num].offset;
+	if ((pin % 8) >= 4)
+		reg += 0x4;
+	bit = (pin % 4) * 4;
+	mask = 0xf;
+
+	data = (mask << (bit + 16));
+	rmask = data | (data >> 16);
+	data |= (mux & mask) << bit;
+
+	if (bank->bank_num == 0 && pin >= RK_PB4 && pin <= RK_PB7)
+		reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_DRV_BITS_PER_PIN		4
+#define RK3576_DRV_PINS_PER_REG		4
+#define RK3576_DRV_GPIO0_AL_OFFSET	0x10
+#define RK3576_DRV_GPIO0_BH_OFFSET	0x2014
+#define RK3576_DRV_GPIO1_OFFSET		0x6020
+#define RK3576_DRV_GPIO2_OFFSET		0x6040
+#define RK3576_DRV_GPIO3_OFFSET		0x6060
+#define RK3576_DRV_GPIO4_AL_OFFSET	0x6080
+#define RK3576_DRV_GPIO4_CL_OFFSET	0xA090
+#define RK3576_DRV_GPIO4_DL_OFFSET	0xB098
+
+static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+					int pin_num, struct regmap **regmap,
+					int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+	if (bank->bank_num == 0 && pin_num < 12) {
+		*reg = RK3576_DRV_GPIO0_AL_OFFSET;
+	} else if (bank->bank_num == 0) {
+		*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3576_DRV_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3576_DRV_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3576_DRV_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 16) {
+		*reg = RK3576_DRV_GPIO4_AL_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 24) {
+		*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3576_DRV_PINS_PER_REG;
+	*bit *= RK3576_DRV_BITS_PER_PIN;
+}
+
+static int rk3576_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data, rmask;
+	u8 bit;
+	int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
+
+	rk3576_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (drv << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_PULL_BITS_PER_PIN	2
+#define RK3576_PULL_PINS_PER_REG	8
+#define RK3576_PULL_GPIO0_AL_OFFSET	0x20
+#define RK3576_PULL_GPIO0_BH_OFFSET	0x2028
+#define RK3576_PULL_GPIO1_OFFSET	0x6110
+#define RK3576_PULL_GPIO2_OFFSET	0x6120
+#define RK3576_PULL_GPIO3_OFFSET	0x6130
+#define RK3576_PULL_GPIO4_AL_OFFSET	0x6140
+#define RK3576_PULL_GPIO4_CL_OFFSET	0xA148
+#define RK3576_PULL_GPIO4_DL_OFFSET	0xB14C
+
+static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+					 int pin_num, struct regmap **regmap,
+					 int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+	if (bank->bank_num == 0 && pin_num < 12) {
+		*reg = RK3576_PULL_GPIO0_AL_OFFSET;
+	} else if (bank->bank_num == 0) {
+		*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3576_PULL_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3576_PULL_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3576_PULL_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 16) {
+		*reg = RK3576_PULL_GPIO4_AL_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 24) {
+		*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3576_PULL_PINS_PER_REG;
+	*bit *= RK3576_PULL_BITS_PER_PIN;
+}
+
+static int rk3576_set_pull(struct rockchip_pin_bank *bank,
+			   int pin_num, int pull)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u8 bit, type;
+	u32 data, rmask;
+
+	if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+		return -ENOTSUPP;
+
+	rk3576_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	type = 1; /* FIXME: was always set to 1 in vendor kernel */
+	ret = rockchip_translate_pull_value(type, pull);
+	if (ret < 0) {
+		debug("unsupported pull setting %d\n", pull);
+		return ret;
+	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (ret << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3576_SMT_BITS_PER_PIN		1
+#define RK3576_SMT_PINS_PER_REG		8
+#define RK3576_SMT_GPIO0_AL_OFFSET	0x30
+#define RK3576_SMT_GPIO0_BH_OFFSET	0x2040
+#define RK3576_SMT_GPIO1_OFFSET		0x6210
+#define RK3576_SMT_GPIO2_OFFSET		0x6220
+#define RK3576_SMT_GPIO3_OFFSET		0x6230
+#define RK3576_SMT_GPIO4_AL_OFFSET	0x6240
+#define RK3576_SMT_GPIO4_CL_OFFSET	0xA248
+#define RK3576_SMT_GPIO4_DL_OFFSET	0xB24C
+
+static void rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+					    int pin_num,
+					    struct regmap **regmap,
+					    int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl_priv *priv = bank->priv;
+
+	*regmap = priv->regmap_base;
+	if (bank->bank_num == 0 && pin_num < 12) {
+		*reg = RK3576_SMT_GPIO0_AL_OFFSET;
+	} else if (bank->bank_num == 0) {
+		*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
+	} else if (bank->bank_num == 1) {
+		*reg = RK3576_SMT_GPIO1_OFFSET;
+	} else if (bank->bank_num == 2) {
+		*reg = RK3576_SMT_GPIO2_OFFSET;
+	} else if (bank->bank_num == 3) {
+		*reg = RK3576_SMT_GPIO3_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 16) {
+		*reg = RK3576_SMT_GPIO4_AL_OFFSET;
+	} else if (bank->bank_num == 4 && pin_num < 24) {
+		*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
+	} else if (bank->bank_num == 4) {
+		*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
+	} else {
+		*reg = 0;
+		debug("unsupported bank_num %d\n", bank->bank_num);
+	}
+
+	*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
+	*bit = pin_num % RK3576_SMT_PINS_PER_REG;
+	*bit *= RK3576_SMT_BITS_PER_PIN;
+}
+
+static int rk3576_set_schmitt(struct rockchip_pin_bank *bank,
+			      int pin_num, int enable)
+{
+	struct regmap *regmap;
+	int reg;
+	u32 data, rmask;
+	u8 bit;
+
+	rk3576_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+	rmask = data | (data >> 16);
+	data |= (enable << bit);
+
+	return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3576_pin_banks[] = {
+	RK3576_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_4BIT,
+			      0, 0x8, 0x2004, 0x200C),
+	RK3576_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+			      0x4020, 0x4028, 0x4030, 0x4038),
+	RK3576_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+			      0x4040, 0x4048, 0x4050, 0x4058),
+	RK3576_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+			      0x4060, 0x4068, 0x4070, 0x4078),
+	RK3576_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+			      0x4080, 0x4088, 0xA390, 0xB398),
+};
+
+static const struct rockchip_pin_ctrl rk3576_pin_ctrl = {
+	.pin_banks		= rk3576_pin_banks,
+	.nr_banks		= ARRAY_SIZE(rk3576_pin_banks),
+	.grf_mux_offset		= 0x0,
+	.set_mux		= rk3576_set_mux,
+	.set_pull		= rk3576_set_pull,
+	.set_drive		= rk3576_set_drive,
+	.set_schmitt		= rk3576_set_schmitt,
+};
+
+static const struct udevice_id rk3576_pinctrl_ids[] = {
+	{
+		.compatible = "rockchip,rk3576-pinctrl",
+		.data = (ulong)&rk3576_pin_ctrl
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3576) = {
+	.name		= "rockchip_rk3576_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk3576_pinctrl_ids,
+	.priv_auto	= sizeof(struct rockchip_pinctrl_priv),
+	.ops		= &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.probe		= rockchip_pinctrl_probe,
+};
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -458,6 +458,9 @@ struct rockchip_pin_bank {
 #define MR_PMUGRF(ID, PIN, FUNC, REG, VAL)	\
 	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)

+#define RK3576_PIN_BANK_FLAGS(ID, PIN, LABEL, M, O1, O2, O3, O4)	\
+	PIN_BANK_IOMUX_FLAGS_OFFSET(ID, PIN, LABEL, M, M, M, M, O1, O2, O3, O4)
+
 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P)			\
 	PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)

--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -13,7 +13,9 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
 obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
 obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
 obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
 obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
--- a/drivers/ram/rockchip/sdram_rk3528.c
+++ b/drivers/ram/rockchip/sdram_rk3528.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMUGRF_BASE			0xff370000
+#define OS_REG18_REG			0x248
+
+static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	info->base = CFG_SYS_SDRAM_BASE;
+	info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG);
+
+	return 0;
+}
+
+static struct ram_ops rk3528_dmc_ops = {
+	.get_info = rk3528_dmc_get_info,
+};
+
+static const struct udevice_id rk3528_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3528-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_dmc) = {
+	.name = "rockchip_rk3528_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3528_dmc_ids,
+	.ops = &rk3528_dmc_ops,
+};
--- a/drivers/ram/rockchip/sdram_rk3576.c
+++ b/drivers/ram/rockchip/sdram_rk3576.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMU1GRF_BASE			0x26026000
+#define OS_REG2_REG			0x208
+
+static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	info->base = CFG_SYS_SDRAM_BASE;
+	info->size = rockchip_sdram_size(PMU1GRF_BASE + OS_REG2_REG);
+
+	return 0;
+}
+
+static struct ram_ops rk3576_dmc_ops = {
+	.get_info = rk3576_dmc_get_info,
+};
+
+static const struct udevice_id rk3576_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3576-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_dmc) = {
+	.name = "rockchip_rk3576_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3576_dmc_ids,
+	.ops = &rk3576_dmc_ops,
+};
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
 obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
--- a/drivers/reset/rst-rk3528.c
+++ b/drivers/reset/rst-rk3528.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
+
+/* 0xFF4A0000 + 0x0A00 */
+#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3528_register_offset[] = {
+	/* CRU_SOFTRST_CON03 */
+	RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
+
+	/* CRU_SOFTRST_CON05 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
+
+	/* CRU_SOFTRST_CON06 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
+
+	/* CRU_SOFTRST_CON08 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
+
+	/* CRU_SOFTRST_CON09 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
+
+	/* CRU_SOFTRST_CON10 */
+	RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
+
+	/* CRU_SOFTRST_CON11 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
+
+	/* CRU_SOFTRST_CON25 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
+
+	/* CRU_SOFTRST_CON26 */
+	RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
+
+	/* CRU_SOFTRST_CON27 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
+
+	/* CRU_SOFTRST_CON28 */
+	RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
+
+	/* CRU_SOFTRST_CON30 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
+
+	/* CRU_SOFTRST_CON32 */
+	RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
+
+	/* CRU_SOFTRST_CON33 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
+
+	/* CRU_SOFTRST_CON34 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
+
+	/* CRU_SOFTRST_CON36 */
+	RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
+
+	/* CRU_SOFTRST_CON37 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
+
+	/* CRU_SOFTRST_CON38 */
+	RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
+
+	/* CRU_SOFTRST_CON39 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
+
+	/* CRU_SOFTRST_CON40 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
+
+	/* CRU_SOFTRST_CON41 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
+
+	/* CRU_SOFTRST_CON42 */
+	RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
+
+	/* CRU_SOFTRST_CON43 */
+	RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
+
+	/* CRU_SOFTRST_CON44 */
+	RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
+	RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
+
+	/* CRU_SOFTRST_CON45 */
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
+	RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
+	RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
+	RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
+	RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
+	RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
+	RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
+	RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
+	RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
+	RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
+
+	/* CRU_SOFTRST_CON46 */
+	RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
+};
+
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+	return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
+				       reg_offset, reg_number);
+}
--- a/drivers/reset/rst-rk3576.c
+++ b/drivers/reset/rst-rk3576.c
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3576-cru.h>
+
+/* 0x27200000 + 0x0A00 */
+#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + (reg) * 16 + (bit))
+/* 0x27208000 + 0x0A00 */
+#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000 * 4 + (reg) * 16 + (bit))
+/* 0x27210000 + 0x0A00 */
+#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + (reg) * 16 + (bit))
+/* 0x27220000 + 0x0A00 */
+#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + (reg) * 16 + (bit))
+
+/* mapping table for reset ID to register offset */
+static const int rk3576_register_offset[] = {
+	/* SOFTRST_CON01 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
+
+	/* SOFTRST_CON02 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
+
+	/* SOFTRST_CON06 */
+	RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
+
+	/* SOFTRST_CON07 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
+
+	/* SOFTRST_CON08 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
+
+	/* SOFTRST_CON09 */
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
+
+	/* SOFTRST_CON11 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
+
+	/* SOFTRST_CON12 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
+
+	/* SOFTRST_CON13 */
+	RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
+
+	/* SOFTRST_CON14 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
+
+	/* SOFTRST_CON15 */
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
+
+	/* SOFTRST_CON16 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
+
+	/* SOFTRST_CON17 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
+
+	/* SOFTRST_CON18 */
+	RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
+
+	/* SOFTRST_CON19 */
+	RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13),
+
+	/* SOFTRST_CON20 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13),
+
+	/* SOFTRST_CON21 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
+
+	/* SOFTRST_CON22 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
+
+	/* SOFTRST_CON23 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
+
+	/* SOFTRST_CON25 */
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6),
+
+	/* SOFTRST_CON26 */
+	RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6),
+
+	/* SOFTRST_CON27 */
+	RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
+
+	/* SOFTRST_CON28 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12),
+
+	/* SOFTRST_CON29 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
+
+	/* SOFTRST_CON31 */
+	RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
+
+	/* SOFTRST_CON32 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13),
+
+	/* SOFTRST_CON33 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12),
+
+	/* SOFTRST_CON34 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
+
+	/* SOFTRST_CON35 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
+
+	/* SOFTRST_CON36 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
+
+	/* SOFTRST_CON37 */
+	RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
+
+	/* SOFTRST_CON40 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
+
+	/* SOFTRST_CON42 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12),
+
+	/* SOFTRST_CON43 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13),
+
+	/* SOFTRST_CON45 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
+
+	/* SOFTRST_CON47 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
+
+	/* SOFTRST_CON48 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
+
+	/* SOFTRST_CON49 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
+
+	/* SOFTRST_CON50 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12),
+
+	/* SOFTRST_CON51 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6),
+
+	/* SOFTRST_CON53 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
+
+	/* SOFTRST_CON54 */
+	RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
+
+	/* SOFTRST_CON59 */
+	RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5),
+
+	/* SOFTRST_CON61 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13),
+
+	/* SOFTRST_CON62 */
+	RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
+
+	/* SOFTRST_CON63 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
+
+	/* SOFTRST_CON64 */
+	RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
+
+	/* SOFTRST_CON65 */
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
+
+	/* SOFTRST_CON66 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
+
+	/* SOFTRST_CON67 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
+
+	/* SOFTRST_CON68 */
+	RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
+	RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12),
+	RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13),
+
+	/* SOFTRST_CON69 */
+	RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
+	RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
+	RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
+
+	/* SOFTRST_CON72 */
+	RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6),
+	RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
+	RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
+	RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10),
+	RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
+	RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12),
+
+	/* SOFTRST_CON75 */
+	RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
+
+	/* SOFTRST_CON78 */
+	RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4),
+
+	/* SOFTRST_CON79 */
+	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
+	RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
+	RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4),
+	RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5),
+
+	/* PPLL_SOFTRST_CON00 */
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
+
+	/* PPLL_SOFTRST_CON01 */
+	RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
+	RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
+
+	/* SECURENS_SOFTRST_CON00 */
+	RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
+	RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
+	RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
+	RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
+
+	/* PMU1_SOFTRST_CON00 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
+
+	/* PMU1_SOFTRST_CON01 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
+
+	/* PMU1_SOFTRST_CON02 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
+
+	/* PMU1_SOFTRST_CON03 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
+
+	/* PMU1_SOFTRST_CON04 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
+
+	/* PMU1_SOFTRST_CON05 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
+
+	/* PMU1_SOFTRST_CON06 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
+
+	/* PMU1_SOFTRST_CON07 */
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
+	RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),
+};
+
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+	return rockchip_reset_bind_lut(pdev, rk3576_register_offset,
+				       reg_offset, reg_number);
+}
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -70,6 +70,27 @@
 #define TRNG_v1_VERSION_CODE			0x46BC
 /* end of TRNG V1 register define */

+/* start of RKRNG register define */
+#define RKRNG_CTRL				0x0010
+#define RKRNG_CTRL_INST_REQ			BIT(0)
+#define RKRNG_CTRL_RESEED_REQ			BIT(1)
+#define RKRNG_CTRL_TEST_REQ			BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ			BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ			BIT(4)
+
+#define RKRNG_STATE				0x0014
+#define RKRNG_STATE_INST_ACK			BIT(0)
+#define RKRNG_STATE_RESEED_ACK			BIT(1)
+#define RKRNG_STATE_TEST_ACK			BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK			BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK			BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0			0x0070
+#define RKRNG_DRNG_DATA_7			0x008C
+
+/* end of RKRNG register define */
+
 #define RK_RNG_TIME_OUT	50000  /* max 50ms */

 #define trng_write(pdata, pos, val)	writel(val, (pdata)->base + (pos))
@@ -228,6 +249,49 @@ exit:
 	return retval;
 }

+static int rkrng_init(struct udevice *dev)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+
+	rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+	reg = trng_read(pdata, RKRNG_STATE);
+	trng_write(pdata, RKRNG_STATE, reg);
+
+	return 0;
+}
+
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct rk_rng_plat *pdata = dev_get_priv(dev);
+	u32 reg = 0;
+	int retval;
+
+	if (len > RK_HW_RNG_MAX)
+		return -EINVAL;
+
+	reg = RKRNG_CTRL_SW_DRNG_REQ;
+
+	rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
+
+	retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
+				    (reg & RKRNG_STATE_SW_DRNG_ACK),
+				    RK_RNG_TIME_OUT);
+	if (retval)
+		goto exit;
+
+	trng_write(pdata, RKRNG_STATE, reg);
+
+	rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
+
+exit:
+	/* close TRNG */
+	rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+	return retval;
+}
+
 static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
 {
 	unsigned char *buf = data;
@@ -295,6 +359,11 @@ static const struct rk_rng_soc_data rk_trngv1_soc_data = {
 	.rk_rng_read = rk_trngv1_rng_read,
 };

+static const struct rk_rng_soc_data rkrng_soc_data = {
+	.rk_rng_init = rkrng_init,
+	.rk_rng_read = rkrng_rng_read,
+};
+
 static const struct dm_rng_ops rockchip_rng_ops = {
 	.read = rockchip_rng_read,
 };
@@ -312,14 +381,22 @@ static const struct udevice_id rockchip_rng_match[] = {
 		.compatible = "rockchip,rk3399-crypto",
 		.data = (ulong)&rk_cryptov1_soc_data,
 	},
+	{
+		.compatible = "rockchip,rk3568-rng",
+		.data = (ulong)&rk_cryptov2_soc_data,
+	},
 	{
 		.compatible = "rockchip,cryptov2-rng",
 		.data = (ulong)&rk_cryptov2_soc_data,
 	},
 	{
-		.compatible = "rockchip,trngv1",
+		.compatible = "rockchip,rk3588-rng",
 		.data = (ulong)&rk_trngv1_soc_data,
 	},
+	{
+		.compatible = "rockchip,rkrng",
+		.data = (ulong)&rkrng_soc_data,
+	},
 	{},
 };

--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -85,6 +85,7 @@ config USB_GADGET_PRODUCT_NUM
 	default 0x330e if ROCKCHIP_RK3308
 	default 0x350a if ROCKCHIP_RK3568
 	default 0x350b if ROCKCHIP_RK3588
+	default 0x350c if ROCKCHIP_RK3528
 	default 0x0
 	help
 	  Product ID of the USB device emulated, reported to the host device.
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -236,6 +236,11 @@ properties:
              - firefly,roc-rk3399-pc-plus
          - const: rockchip,rk3399

+      - description: Firefly ROC-RK3576-PC
+        items:
+          - const: firefly,roc-rk3576-pc
+          - const: rockchip,rk3576
+
      - description: Firefly Station M2
        items:
          - const: firefly,rk3566-roc-pc
--- a/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
+++ b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3528 Clock and Reset Controller
+
+maintainers:
+  - Yao Zi <ziyao@disroot.org>
+
+description: |
+  The RK3528 clock controller generates the clock and also implements a reset
+  controller for SoC peripherals. For example, it provides SCLK_UART0 and
+  PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
+  module.
+  Each clock is assigned an identifier, consumer nodes can use it to specify
+  the clock. All available clock and reset IDs are defined in dt-binding
+  headers.
+
+properties:
+  compatible:
+    const: rockchip,rk3528-cru
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: External 24MHz oscillator clock
+      - description: >
+          50MHz clock generated by PHY module, for generating GMAC0 clocks only.
+
+  clock-names:
+    items:
+      - const: xin24m
+      - const: gmac0
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@ff4a0000 {
+        compatible = "rockchip,rk3528-cru";
+        reg = <0xff4a0000 0x30000>;
+        clocks = <&xin24m>, <&gmac0_clk>;
+        clock-names = "xin24m", "gmac0";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+    };
--- a/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
+++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+#define PLL_APLL			0
+#define PLL_CPLL			1
+#define PLL_GPLL			2
+#define PLL_PPLL			3
+#define PLL_DPLL			4
+#define ARMCLK				5
+#define XIN_OSC0_HALF			6
+#define CLK_MATRIX_50M_SRC		7
+#define CLK_MATRIX_100M_SRC		8
+#define CLK_MATRIX_150M_SRC		9
+#define CLK_MATRIX_200M_SRC		10
+#define CLK_MATRIX_250M_SRC		11
+#define CLK_MATRIX_300M_SRC		12
+#define CLK_MATRIX_339M_SRC		13
+#define CLK_MATRIX_400M_SRC		14
+#define CLK_MATRIX_500M_SRC		15
+#define CLK_MATRIX_600M_SRC		16
+#define CLK_UART0_SRC			17
+#define CLK_UART0_FRAC			18
+#define SCLK_UART0			19
+#define CLK_UART1_SRC			20
+#define CLK_UART1_FRAC			21
+#define SCLK_UART1			22
+#define CLK_UART2_SRC			23
+#define CLK_UART2_FRAC			24
+#define SCLK_UART2			25
+#define CLK_UART3_SRC			26
+#define CLK_UART3_FRAC			27
+#define SCLK_UART3			28
+#define CLK_UART4_SRC			29
+#define CLK_UART4_FRAC			30
+#define SCLK_UART4			31
+#define CLK_UART5_SRC			32
+#define CLK_UART5_FRAC			33
+#define SCLK_UART5			34
+#define CLK_UART6_SRC			35
+#define CLK_UART6_FRAC			36
+#define SCLK_UART6			37
+#define CLK_UART7_SRC			38
+#define CLK_UART7_FRAC			39
+#define SCLK_UART7			40
+#define CLK_I2S0_2CH_SRC		41
+#define CLK_I2S0_2CH_FRAC		42
+#define MCLK_I2S0_2CH_SAI_SRC		43
+#define CLK_I2S3_8CH_SRC		44
+#define CLK_I2S3_8CH_FRAC		45
+#define MCLK_I2S3_8CH_SAI_SRC		46
+#define CLK_I2S1_8CH_SRC		47
+#define CLK_I2S1_8CH_FRAC		48
+#define MCLK_I2S1_8CH_SAI_SRC		49
+#define CLK_I2S2_2CH_SRC		50
+#define CLK_I2S2_2CH_FRAC		51
+#define MCLK_I2S2_2CH_SAI_SRC		52
+#define CLK_SPDIF_SRC			53
+#define CLK_SPDIF_FRAC			54
+#define MCLK_SPDIF_SRC			55
+#define DCLK_VOP_SRC0			56
+#define DCLK_VOP_SRC1			57
+#define CLK_HSM				58
+#define CLK_CORE_SRC_ACS		59
+#define CLK_CORE_SRC_PVTMUX		60
+#define CLK_CORE_SRC			61
+#define CLK_CORE			62
+#define ACLK_M_CORE_BIU			63
+#define CLK_CORE_PVTPLL_SRC		64
+#define PCLK_DBG			65
+#define SWCLKTCK			66
+#define CLK_SCANHS_CORE			67
+#define CLK_SCANHS_ACLKM_CORE		68
+#define CLK_SCANHS_PCLK_DBG		69
+#define CLK_SCANHS_PCLK_CPU_BIU		70
+#define PCLK_CPU_ROOT			71
+#define PCLK_CORE_GRF			72
+#define PCLK_DAPLITE_BIU		73
+#define PCLK_CPU_BIU			74
+#define CLK_REF_PVTPLL_CORE		75
+#define ACLK_BUS_VOPGL_ROOT		76
+#define ACLK_BUS_VOPGL_BIU		77
+#define ACLK_BUS_H_ROOT			78
+#define ACLK_BUS_H_BIU			79
+#define ACLK_BUS_ROOT			80
+#define HCLK_BUS_ROOT			81
+#define PCLK_BUS_ROOT			82
+#define ACLK_BUS_M_ROOT			83
+#define ACLK_SYSMEM_BIU			84
+#define CLK_TIMER_ROOT			85
+#define ACLK_BUS_BIU			86
+#define HCLK_BUS_BIU			87
+#define PCLK_BUS_BIU			88
+#define PCLK_DFT2APB			89
+#define PCLK_BUS_GRF			90
+#define ACLK_BUS_M_BIU			91
+#define ACLK_GIC			92
+#define ACLK_SPINLOCK			93
+#define ACLK_DMAC			94
+#define PCLK_TIMER			95
+#define CLK_TIMER0			96
+#define CLK_TIMER1			97
+#define CLK_TIMER2			98
+#define CLK_TIMER3			99
+#define CLK_TIMER4			100
+#define CLK_TIMER5			101
+#define PCLK_JDBCK_DAP			102
+#define CLK_JDBCK_DAP			103
+#define PCLK_WDT_NS			104
+#define TCLK_WDT_NS			105
+#define HCLK_TRNG_NS			106
+#define PCLK_UART0			107
+#define PCLK_DMA2DDR			108
+#define ACLK_DMA2DDR			109
+#define PCLK_PWM0			110
+#define CLK_PWM0			111
+#define CLK_CAPTURE_PWM0		112
+#define PCLK_PWM1			113
+#define CLK_PWM1			114
+#define CLK_CAPTURE_PWM1		115
+#define PCLK_SCR			116
+#define ACLK_DCF			117
+#define PCLK_INTMUX			118
+#define CLK_PPLL_I			119
+#define CLK_PPLL_MUX			120
+#define CLK_PPLL_100M_MATRIX		121
+#define CLK_PPLL_50M_MATRIX		122
+#define CLK_REF_PCIE_INNER_PHY		123
+#define CLK_REF_PCIE_100M_PHY		124
+#define ACLK_VPU_L_ROOT			125
+#define CLK_GMAC1_VPU_25M		126
+#define CLK_PPLL_125M_MATRIX		127
+#define ACLK_VPU_ROOT			128
+#define HCLK_VPU_ROOT			129
+#define PCLK_VPU_ROOT			130
+#define ACLK_VPU_BIU			131
+#define HCLK_VPU_BIU			132
+#define PCLK_VPU_BIU			133
+#define ACLK_VPU			134
+#define HCLK_VPU			135
+#define PCLK_CRU_PCIE			136
+#define PCLK_VPU_GRF			137
+#define HCLK_SFC			138
+#define SCLK_SFC			139
+#define CCLK_SRC_EMMC			140
+#define HCLK_EMMC			141
+#define ACLK_EMMC			142
+#define BCLK_EMMC			143
+#define TCLK_EMMC			144
+#define PCLK_GPIO1			145
+#define DBCLK_GPIO1			146
+#define ACLK_VPU_L_BIU			147
+#define PCLK_VPU_IOC			148
+#define HCLK_SAI_I2S0			149
+#define MCLK_SAI_I2S0			150
+#define HCLK_SAI_I2S2			151
+#define MCLK_SAI_I2S2			152
+#define PCLK_ACODEC			153
+#define MCLK_ACODEC_TX			154
+#define PCLK_GPIO3			155
+#define DBCLK_GPIO3			156
+#define PCLK_SPI1			157
+#define CLK_SPI1			158
+#define SCLK_IN_SPI1			159
+#define PCLK_UART2			160
+#define PCLK_UART5			161
+#define PCLK_UART6			162
+#define PCLK_UART7			163
+#define PCLK_I2C3			164
+#define CLK_I2C3			165
+#define PCLK_I2C5			166
+#define CLK_I2C5			167
+#define PCLK_I2C6			168
+#define CLK_I2C6			169
+#define ACLK_MAC_VPU			170
+#define PCLK_MAC_VPU			171
+#define CLK_GMAC1_RMII_VPU		172
+#define CLK_GMAC1_SRC_VPU		173
+#define PCLK_PCIE			174
+#define CLK_PCIE_AUX			175
+#define ACLK_PCIE			176
+#define HCLK_PCIE_SLV			177
+#define HCLK_PCIE_DBI			178
+#define PCLK_PCIE_PHY			179
+#define PCLK_PIPE_GRF			180
+#define CLK_PIPE_USB3OTG_COMBO		181
+#define CLK_UTMI_USB3OTG		182
+#define CLK_PCIE_PIPE_PHY		183
+#define CCLK_SRC_SDIO0			184
+#define HCLK_SDIO0			185
+#define CCLK_SRC_SDIO1			186
+#define HCLK_SDIO1			187
+#define CLK_TS_0			188
+#define CLK_TS_1			189
+#define PCLK_CAN2			190
+#define CLK_CAN2			191
+#define PCLK_CAN3			192
+#define CLK_CAN3			193
+#define PCLK_SARADC			194
+#define CLK_SARADC			195
+#define PCLK_TSADC			196
+#define CLK_TSADC			197
+#define CLK_TSADC_TSEN			198
+#define ACLK_USB3OTG			199
+#define CLK_REF_USB3OTG			200
+#define CLK_SUSPEND_USB3OTG		201
+#define ACLK_GPU_ROOT			202
+#define PCLK_GPU_ROOT			203
+#define ACLK_GPU_BIU			204
+#define PCLK_GPU_BIU			205
+#define ACLK_GPU			206
+#define CLK_GPU_PVTPLL_SRC		207
+#define ACLK_GPU_MALI			208
+#define HCLK_RKVENC_ROOT		209
+#define ACLK_RKVENC_ROOT		210
+#define PCLK_RKVENC_ROOT		211
+#define HCLK_RKVENC_BIU			212
+#define ACLK_RKVENC_BIU			213
+#define PCLK_RKVENC_BIU			214
+#define HCLK_RKVENC			215
+#define ACLK_RKVENC			216
+#define CLK_CORE_RKVENC			217
+#define HCLK_SAI_I2S1			218
+#define MCLK_SAI_I2S1			219
+#define PCLK_I2C1			220
+#define CLK_I2C1			221
+#define PCLK_I2C0			222
+#define CLK_I2C0			223
+#define CLK_UART_JTAG			224
+#define PCLK_SPI0			225
+#define CLK_SPI0			226
+#define SCLK_IN_SPI0			227
+#define PCLK_GPIO4			228
+#define DBCLK_GPIO4			229
+#define PCLK_RKVENC_IOC			230
+#define HCLK_SPDIF			231
+#define MCLK_SPDIF			232
+#define HCLK_PDM			233
+#define MCLK_PDM			234
+#define PCLK_UART1			235
+#define PCLK_UART3			236
+#define PCLK_RKVENC_GRF			237
+#define PCLK_CAN0			238
+#define CLK_CAN0			239
+#define PCLK_CAN1			240
+#define CLK_CAN1			241
+#define ACLK_VO_ROOT			242
+#define HCLK_VO_ROOT			243
+#define PCLK_VO_ROOT			244
+#define ACLK_VO_BIU			245
+#define HCLK_VO_BIU			246
+#define PCLK_VO_BIU			247
+#define HCLK_RGA2E			248
+#define ACLK_RGA2E			249
+#define CLK_CORE_RGA2E			250
+#define HCLK_VDPP			251
+#define ACLK_VDPP			252
+#define CLK_CORE_VDPP			253
+#define PCLK_VO_GRF			254
+#define PCLK_CRU			255
+#define ACLK_VOP_ROOT			256
+#define ACLK_VOP_BIU			257
+#define HCLK_VOP			258
+#define DCLK_VOP0			259
+#define DCLK_VOP1			260
+#define ACLK_VOP			261
+#define PCLK_HDMI			262
+#define CLK_SFR_HDMI			263
+#define CLK_CEC_HDMI			264
+#define CLK_SPDIF_HDMI			265
+#define CLK_HDMIPHY_TMDSSRC		266
+#define CLK_HDMIPHY_PREP		267
+#define PCLK_HDMIPHY			268
+#define HCLK_HDCP_KEY			269
+#define ACLK_HDCP			270
+#define HCLK_HDCP			271
+#define PCLK_HDCP			272
+#define HCLK_CVBS			273
+#define DCLK_CVBS			274
+#define DCLK_4X_CVBS			275
+#define ACLK_JPEG_DECODER		276
+#define HCLK_JPEG_DECODER		277
+#define ACLK_VO_L_ROOT			278
+#define ACLK_VO_L_BIU			279
+#define ACLK_MAC_VO			280
+#define PCLK_MAC_VO			281
+#define CLK_GMAC0_SRC			282
+#define CLK_GMAC0_RMII_50M		283
+#define CLK_GMAC0_TX			284
+#define CLK_GMAC0_RX			285
+#define ACLK_JPEG_ROOT			286
+#define ACLK_JPEG_BIU			287
+#define HCLK_SAI_I2S3			288
+#define MCLK_SAI_I2S3			289
+#define CLK_MACPHY			290
+#define PCLK_VCDCPHY			291
+#define PCLK_GPIO2			292
+#define DBCLK_GPIO2			293
+#define PCLK_VO_IOC			294
+#define CCLK_SRC_SDMMC0			295
+#define HCLK_SDMMC0			296
+#define PCLK_OTPC_NS			297
+#define CLK_SBPI_OTPC_NS		298
+#define CLK_USER_OTPC_NS		299
+#define CLK_HDMIHDP0			300
+#define HCLK_USBHOST			301
+#define HCLK_USBHOST_ARB		302
+#define CLK_USBHOST_OHCI		303
+#define CLK_USBHOST_UTMI		304
+#define PCLK_UART4			305
+#define PCLK_I2C4			306
+#define CLK_I2C4			307
+#define PCLK_I2C7			308
+#define CLK_I2C7			309
+#define PCLK_USBPHY			310
+#define CLK_REF_USBPHY			311
+#define HCLK_RKVDEC_ROOT		312
+#define ACLK_RKVDEC_ROOT_NDFT		313
+#define PCLK_DDRPHY_CRU			314
+#define HCLK_RKVDEC_BIU			315
+#define ACLK_RKVDEC_BIU			316
+#define ACLK_RKVDEC			317
+#define HCLK_RKVDEC			318
+#define CLK_HEVC_CA_RKVDEC		319
+#define ACLK_RKVDEC_PVTMUX_ROOT		320
+#define CLK_RKVDEC_PVTPLL_SRC		321
+#define PCLK_DDR_ROOT			322
+#define PCLK_DDR_BIU			323
+#define PCLK_DDRC			324
+#define PCLK_DDRMON			325
+#define CLK_TIMER_DDRMON		326
+#define PCLK_MSCH_BIU			327
+#define PCLK_DDR_GRF			328
+#define PCLK_DDR_HWLP			329
+#define PCLK_DDRPHY			330
+#define CLK_MSCH_BIU			331
+#define ACLK_DDR_UPCTL			332
+#define CLK_DDR_UPCTL			333
+#define CLK_DDRMON			334
+#define ACLK_DDR_SCRAMBLE		335
+#define ACLK_SPLIT			336
+#define CLK_DDRC_SRC			337
+#define CLK_DDR_PHY			338
+#define PCLK_OTPC_S			339
+#define CLK_SBPI_OTPC_S			340
+#define CLK_USER_OTPC_S			341
+#define PCLK_KEYREADER			342
+#define PCLK_BUS_SGRF			343
+#define PCLK_STIMER			344
+#define CLK_STIMER0			345
+#define CLK_STIMER1			346
+#define PCLK_WDT_S			347
+#define TCLK_WDT_S			348
+#define HCLK_TRNG_S			349
+#define HCLK_BOOTROM			350
+#define PCLK_DCF			351
+#define ACLK_SYSMEM			352
+#define HCLK_TSP			353
+#define ACLK_TSP			354
+#define CLK_CORE_TSP			355
+#define CLK_OTPC_ARB			356
+#define PCLK_OTP_MASK			357
+#define CLK_PMC_OTP			358
+#define PCLK_PMU_ROOT			359
+#define HCLK_PMU_ROOT			360
+#define PCLK_I2C2			361
+#define CLK_I2C2			362
+#define HCLK_PMU_BIU			363
+#define PCLK_PMU_BIU			364
+#define FCLK_MCU			365
+#define RTC_CLK_MCU			366
+#define PCLK_OSCCHK			367
+#define CLK_PMU_MCU_JTAG		368
+#define PCLK_PMU			369
+#define PCLK_GPIO0			370
+#define DBCLK_GPIO0			371
+#define XIN_OSC0_DIV			372
+#define CLK_DEEPSLOW			373
+#define CLK_DDR_FAIL_SAFE		374
+#define PCLK_PMU_HP_TIMER		375
+#define CLK_PMU_HP_TIMER		376
+#define CLK_PMU_32K_HP_TIMER		377
+#define PCLK_PMU_IOC			378
+#define PCLK_PMU_CRU			379
+#define PCLK_PMU_GRF			380
+#define PCLK_PMU_WDT			381
+#define TCLK_PMU_WDT			382
+#define PCLK_PMU_MAILBOX		383
+#define PCLK_SCRKEYGEN			384
+#define CLK_SCRKEYGEN			385
+#define CLK_PVTM_OSCCHK			386
+#define CLK_REFOUT			387
+#define CLK_PVTM_PMU			388
+#define PCLK_PVTM_PMU			389
+#define PCLK_PMU_SGRF			390
+#define HCLK_PMU_SRAM			391
+#define CLK_UART0			392
+#define CLK_UART1			393
+#define CLK_UART2			394
+#define CLK_UART3			395
+#define CLK_UART4			396
+#define CLK_UART5			397
+#define CLK_UART6			398
+#define CLK_UART7			399
+#define MCLK_I2S0_2CH_SAI_SRC_PRE	400
+#define MCLK_I2S1_8CH_SAI_SRC_PRE	401
+#define MCLK_I2S2_2CH_SAI_SRC_PRE	402
+#define MCLK_I2S3_8CH_SAI_SRC_PRE	403
+#define MCLK_SDPDIF_SRC_PRE		404
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER		0
+#define SCMI_HCLK_KLAD			1
+#define SCMI_PCLK_KLAD			2
+#define SCMI_HCLK_TRNG_S		3
+#define SCMI_HCLK_CRYPTO_S		4
+#define SCMI_PCLK_WDT_S			5
+#define SCMI_TCLK_WDT_S			6
+#define SCMI_PCLK_STIMER		7
+#define SCMI_CLK_STIMER0		8
+#define SCMI_CLK_STIMER1		9
+#define SCMI_PCLK_OTP_MASK		10
+#define SCMI_PCLK_OTPC_S		11
+#define SCMI_CLK_SBPI_OTPC_S		12
+#define SCMI_CLK_USER_OTPC_S		13
+#define SCMI_CLK_PMC_OTP		14
+#define SCMI_CLK_OTPC_ARB		15
+#define SCMI_CLK_CORE_TSP		16
+#define SCMI_ACLK_TSP			17
+#define SCMI_HCLK_TSP			18
+#define SCMI_PCLK_DCF			19
+#define SCMI_CLK_DDR			20
+#define SCMI_CLK_CPU			21
+#define SCMI_CLK_GPU			22
+#define SCMI_CORE_CRYPTO		23
+#define SCMI_ACLK_CRYPTO		24
+#define SCMI_PKA_CRYPTO			25
+#define SCMI_HCLK_CRYPTO		26
+#define SCMI_CORE_CRYPTO_S		27
+#define SCMI_ACLK_CRYPTO_S		28
+#define SCMI_PKA_CRYPTO_S		29
+#define SCMI_CORE_KLAD			30
+#define SCMI_ACLK_KLAD			31
+#define SCMI_HCLK_TRNG			32
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
--- a/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
+++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_NL2		8
+#define SRST_CORE_BIU		9
+#define SRST_CORE_CRYPTO	10
+#define SRST_P_DBG		11
+#define SRST_POT_DBG		12
+#define SRST_NT_DBG		13
+#define SRST_P_CORE_GRF		14
+#define SRST_P_DAPLITE_BIU	15
+#define SRST_P_CPU_BIU		16
+#define SRST_REF_PVTPLL_CORE	17
+#define SRST_A_BUS_VOPGL_BIU	18
+#define SRST_A_BUS_H_BIU	19
+#define SRST_A_SYSMEM_BIU	20
+#define SRST_A_BUS_BIU		21
+#define SRST_H_BUS_BIU		22
+#define SRST_P_BUS_BIU		23
+#define SRST_P_DFT2APB		24
+#define SRST_P_BUS_GRF		25
+#define SRST_A_BUS_M_BIU	26
+#define SRST_A_GIC		27
+#define SRST_A_SPINLOCK		28
+#define SRST_A_DMAC		29
+#define SRST_P_TIMER		30
+#define SRST_TIMER0		31
+#define SRST_TIMER1		32
+#define SRST_TIMER2		33
+#define SRST_TIMER3		34
+#define SRST_TIMER4		35
+#define SRST_TIMER5		36
+#define SRST_P_JDBCK_DAP	37
+#define SRST_JDBCK_DAP		38
+#define SRST_P_WDT_NS		39
+#define SRST_T_WDT_NS		40
+#define SRST_H_TRNG_NS		41
+#define SRST_P_UART0		42
+#define SRST_S_UART0		43
+#define SRST_PKA_CRYPTO		44
+#define SRST_A_CRYPTO		45
+#define SRST_H_CRYPTO		46
+#define SRST_P_DMA2DDR		47
+#define SRST_A_DMA2DDR		48
+#define SRST_P_PWM0		49
+#define SRST_PWM0		50
+#define SRST_P_PWM1		51
+#define SRST_PWM1		52
+#define SRST_P_SCR		53
+#define SRST_A_DCF		54
+#define SRST_P_INTMUX		55
+#define SRST_A_VPU_BIU		56
+#define SRST_H_VPU_BIU		57
+#define SRST_P_VPU_BIU		58
+#define SRST_A_VPU		59
+#define SRST_H_VPU		60
+#define SRST_P_CRU_PCIE		61
+#define SRST_P_VPU_GRF		62
+#define SRST_H_SFC		63
+#define SRST_S_SFC		64
+#define SRST_C_EMMC		65
+#define SRST_H_EMMC		66
+#define SRST_A_EMMC		67
+#define SRST_B_EMMC		68
+#define SRST_T_EMMC		69
+#define SRST_P_GPIO1		70
+#define SRST_DB_GPIO1		71
+#define SRST_A_VPU_L_BIU	72
+#define SRST_P_VPU_IOC		73
+#define SRST_H_SAI_I2S0		74
+#define SRST_M_SAI_I2S0		75
+#define SRST_H_SAI_I2S2		76
+#define SRST_M_SAI_I2S2		77
+#define SRST_P_ACODEC		78
+#define SRST_P_GPIO3		79
+#define SRST_DB_GPIO3		80
+#define SRST_P_SPI1		81
+#define SRST_SPI1		82
+#define SRST_P_UART2		83
+#define SRST_S_UART2		84
+#define SRST_P_UART5		85
+#define SRST_S_UART5		86
+#define SRST_P_UART6		87
+#define SRST_S_UART6		88
+#define SRST_P_UART7		89
+#define SRST_S_UART7		90
+#define SRST_P_I2C3		91
+#define SRST_I2C3		92
+#define SRST_P_I2C5		93
+#define SRST_I2C5		94
+#define SRST_P_I2C6		95
+#define SRST_I2C6		96
+#define SRST_A_MAC		97
+#define SRST_P_PCIE		98
+#define SRST_PCIE_PIPE_PHY	99
+#define SRST_PCIE_POWER_UP	100
+#define SRST_P_PCIE_PHY		101
+#define SRST_P_PIPE_GRF		102
+#define SRST_H_SDIO0		103
+#define SRST_H_SDIO1		104
+#define SRST_TS_0		105
+#define SRST_TS_1		106
+#define SRST_P_CAN2		107
+#define SRST_CAN2		108
+#define SRST_P_CAN3		109
+#define SRST_CAN3		110
+#define SRST_P_SARADC		111
+#define SRST_SARADC		112
+#define SRST_SARADC_PHY		113
+#define SRST_P_TSADC		114
+#define SRST_TSADC		115
+#define SRST_A_USB3OTG		116
+#define SRST_A_GPU_BIU		117
+#define SRST_P_GPU_BIU		118
+#define SRST_A_GPU		119
+#define SRST_REF_PVTPLL_GPU	120
+#define SRST_H_RKVENC_BIU	121
+#define SRST_A_RKVENC_BIU	122
+#define SRST_P_RKVENC_BIU	123
+#define SRST_H_RKVENC		124
+#define SRST_A_RKVENC		125
+#define SRST_CORE_RKVENC	126
+#define SRST_H_SAI_I2S1		127
+#define SRST_M_SAI_I2S1		128
+#define SRST_P_I2C1		129
+#define SRST_I2C1		130
+#define SRST_P_I2C0		131
+#define SRST_I2C0		132
+#define SRST_P_SPI0		133
+#define SRST_SPI0		134
+#define SRST_P_GPIO4		135
+#define SRST_DB_GPIO4		136
+#define SRST_P_RKVENC_IOC	137
+#define SRST_H_SPDIF		138
+#define SRST_M_SPDIF		139
+#define SRST_H_PDM		140
+#define SRST_M_PDM		141
+#define SRST_P_UART1		142
+#define SRST_S_UART1		143
+#define SRST_P_UART3		144
+#define SRST_S_UART3		145
+#define SRST_P_RKVENC_GRF	146
+#define SRST_P_CAN0		147
+#define SRST_CAN0		148
+#define SRST_P_CAN1		149
+#define SRST_CAN1		150
+#define SRST_A_VO_BIU		151
+#define SRST_H_VO_BIU		152
+#define SRST_P_VO_BIU		153
+#define SRST_H_RGA2E		154
+#define SRST_A_RGA2E		155
+#define SRST_CORE_RGA2E		156
+#define SRST_H_VDPP		157
+#define SRST_A_VDPP		158
+#define SRST_CORE_VDPP		159
+#define SRST_P_VO_GRF		160
+#define SRST_P_CRU		161
+#define SRST_A_VOP_BIU		162
+#define SRST_H_VOP		163
+#define SRST_D_VOP0		164
+#define SRST_D_VOP1		165
+#define SRST_A_VOP		166
+#define SRST_P_HDMI		167
+#define SRST_HDMI		168
+#define SRST_P_HDMIPHY		169
+#define SRST_H_HDCP_KEY		170
+#define SRST_A_HDCP		171
+#define SRST_H_HDCP		172
+#define SRST_P_HDCP		173
+#define SRST_H_CVBS		174
+#define SRST_D_CVBS_VOP		175
+#define SRST_D_4X_CVBS_VOP	176
+#define SRST_A_JPEG_DECODER	177
+#define SRST_H_JPEG_DECODER	178
+#define SRST_A_VO_L_BIU		179
+#define SRST_A_MAC_VO		180
+#define SRST_A_JPEG_BIU		181
+#define SRST_H_SAI_I2S3		182
+#define SRST_M_SAI_I2S3		183
+#define SRST_MACPHY		184
+#define SRST_P_VCDCPHY		185
+#define SRST_P_GPIO2		186
+#define SRST_DB_GPIO2		187
+#define SRST_P_VO_IOC		188
+#define SRST_H_SDMMC0		189
+#define SRST_P_OTPC_NS		190
+#define SRST_SBPI_OTPC_NS	191
+#define SRST_USER_OTPC_NS	192
+#define SRST_HDMIHDP0		193
+#define SRST_H_USBHOST		194
+#define SRST_H_USBHOST_ARB	195
+#define SRST_HOST_UTMI		196
+#define SRST_P_UART4		197
+#define SRST_S_UART4		198
+#define SRST_P_I2C4		199
+#define SRST_I2C4		200
+#define SRST_P_I2C7		201
+#define SRST_I2C7		202
+#define SRST_P_USBPHY		203
+#define SRST_USBPHY_POR		204
+#define SRST_USBPHY_OTG		205
+#define SRST_USBPHY_HOST	206
+#define SRST_P_DDRPHY_CRU	207
+#define SRST_H_RKVDEC_BIU	208
+#define SRST_A_RKVDEC_BIU	209
+#define SRST_A_RKVDEC		210
+#define SRST_H_RKVDEC		211
+#define SRST_HEVC_CA_RKVDEC	212
+#define SRST_REF_PVTPLL_RKVDEC	213
+#define SRST_P_DDR_BIU		214
+#define SRST_P_DDRC		215
+#define SRST_P_DDRMON		216
+#define SRST_TIMER_DDRMON	217
+#define SRST_P_MSCH_BIU		218
+#define SRST_P_DDR_GRF		219
+#define SRST_P_DDR_HWLP		220
+#define SRST_P_DDRPHY		221
+#define SRST_MSCH_BIU		222
+#define SRST_A_DDR_UPCTL	223
+#define SRST_DDR_UPCTL		224
+#define SRST_DDRMON		225
+#define SRST_A_DDR_SCRAMBLE	226
+#define SRST_A_SPLIT		227
+#define SRST_DDR_PHY		228
+
+#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
--- a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -6,17 +6,150 @@
 */

 /dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "rk3528.dtsi"

 / {
 	model = "Radxa E20C";
 	compatible = "radxa,e20c", "rockchip,rk3528";

+	aliases {
+		mmc0 = &sdhci;
+	};
+
 	chosen {
 		stdout-path = "serial0:1500000n8";
 	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-maskrom {
+			label = "MASKROM";
+			linux,code = <KEY_SETUP>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_key>;
+
+		button-user {
+			gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+			label = "USER";
+			linux,code = <BTN_1>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>;
+
+		led-lan {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_LAN;
+			gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "netdev";
+		};
+
+		led-sys {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_HEARTBEAT;
+			gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+		};
+
+		led-wan {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			function = LED_FUNCTION_WAN;
+			gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "netdev";
+		};
+	};
+
+	vcc_1v8: regulator-1v8-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_3v3>;
+	};
+
+	vcc_3v3: regulator-3v3-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: regulator-5v0-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&pinctrl {
+	gpio-keys {
+		user_key: user-key {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	leds {
+		lan_led_g: lan-led-g {
+			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		sys_led_g: sys-led-g {
+			rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_g: wan-led-g {
+			rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	no-sd;
+	no-sdio;
+	non-removable;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&vcc_1v8>;
+	status = "okay";
 };

 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0m0_xfer>;
 	status = "okay";
 };
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -4,8 +4,12 @@
 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
 */

+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>

 / {
 	compatible = "rockchip,rk3528";
@@ -15,6 +19,11 @@
 	#size-cells = <2>;

 	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
 		serial0 = &uart0;
 		serial1 = &uart1;
 		serial2 = &uart2;
@@ -51,6 +60,7 @@
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};

 		cpu1: cpu@1 {
@@ -58,6 +68,7 @@
 			reg = <0x1>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};

 		cpu2: cpu@2 {
@@ -65,6 +76,7 @@
 			reg = <0x2>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
 		};

 		cpu3: cpu@3 {
@@ -72,6 +84,22 @@
 			reg = <0x3>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&scmi_clk SCMI_CLK_CPU>;
+		};
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82000010>;
+			shmem = <&scmi_shmem>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
 		};
 	};

@@ -80,6 +108,18 @@
 		method = "smc";
 	};

+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scmi_shmem: shmem@10f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x0010f000 0x0 0x100>;
+			no-map;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -95,6 +135,13 @@
 		#clock-cells = <0>;
 	};

+	gmac0_clk: clock-gmac50m {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "gmac0";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
@@ -114,10 +161,219 @@
 			#interrupt-cells = <3>;
 		};

+		qos_crypto_a: qos@ff200000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200000 0x0 0x20>;
+		};
+
+		qos_crypto_p: qos@ff200080 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200080 0x0 0x20>;
+		};
+
+		qos_dcf: qos@ff200100 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200100 0x0 0x20>;
+		};
+
+		qos_dft2apb: qos@ff200200 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200200 0x0 0x20>;
+		};
+
+		qos_dma2ddr: qos@ff200280 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200280 0x0 0x20>;
+		};
+
+		qos_dmac: qos@ff200300 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200300 0x0 0x20>;
+		};
+
+		qos_keyreader: qos@ff200380 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff200380 0x0 0x20>;
+		};
+
+		qos_cpu: qos@ff210000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff210000 0x0 0x20>;
+		};
+
+		qos_debug: qos@ff210080 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff210080 0x0 0x20>;
+		};
+
+		qos_gpu_m0: qos@ff220000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff220000 0x0 0x20>;
+		};
+
+		qos_gpu_m1: qos@ff220080 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff220080 0x0 0x20>;
+		};
+
+		qos_pmu_mcu: qos@ff240000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff240000 0x0 0x20>;
+		};
+
+		qos_rkvdec: qos@ff250000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff250000 0x0 0x20>;
+		};
+
+		qos_rkvenc: qos@ff260000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff260000 0x0 0x20>;
+		};
+
+		qos_gmac0: qos@ff270000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270000 0x0 0x20>;
+		};
+
+		qos_hdcp: qos@ff270080 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270080 0x0 0x20>;
+		};
+
+		qos_jpegdec: qos@ff270100 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270100 0x0 0x20>;
+		};
+
+		qos_rga2_m0ro: qos@ff270200 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270200 0x0 0x20>;
+		};
+
+		qos_rga2_m0wo: qos@ff270280 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270280 0x0 0x20>;
+		};
+
+		qos_sdmmc0: qos@ff270300 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270300 0x0 0x20>;
+		};
+
+		qos_usb2host: qos@ff270380 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270380 0x0 0x20>;
+		};
+
+		qos_vdpp: qos@ff270480 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270480 0x0 0x20>;
+		};
+
+		qos_vop: qos@ff270500 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff270500 0x0 0x20>;
+		};
+
+		qos_emmc: qos@ff280000 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280000 0x0 0x20>;
+		};
+
+		qos_fspi: qos@ff280080 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280080 0x0 0x20>;
+		};
+
+		qos_gmac1: qos@ff280100 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280100 0x0 0x20>;
+		};
+
+		qos_pcie: qos@ff280180 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280180 0x0 0x20>;
+		};
+
+		qos_sdio0: qos@ff280200 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280200 0x0 0x20>;
+		};
+
+		qos_sdio1: qos@ff280280 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280280 0x0 0x20>;
+		};
+
+		qos_tsp: qos@ff280300 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280300 0x0 0x20>;
+		};
+
+		qos_usb3otg: qos@ff280380 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280380 0x0 0x20>;
+		};
+
+		qos_vpu: qos@ff280400 {
+			compatible = "rockchip,rk3528-qos", "syscon";
+			reg = <0x0 0xff280400 0x0 0x20>;
+		};
+
+		cru: clock-controller@ff4a0000 {
+			compatible = "rockchip,rk3528-cru";
+			reg = <0x0 0xff4a0000 0x0 0x30000>;
+			assigned-clocks =
+				<&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
+				<&cru PLL_PPLL>, <&cru PLL_CPLL>,
+				<&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
+				<&cru CLK_MATRIX_500M_SRC>,
+				<&cru CLK_MATRIX_50M_SRC>,
+				<&cru CLK_MATRIX_100M_SRC>,
+				<&cru CLK_MATRIX_150M_SRC>,
+				<&cru CLK_MATRIX_200M_SRC>,
+				<&cru CLK_MATRIX_300M_SRC>,
+				<&cru CLK_MATRIX_339M_SRC>,
+				<&cru CLK_MATRIX_400M_SRC>,
+				<&cru CLK_MATRIX_600M_SRC>,
+				<&cru CLK_PPLL_50M_MATRIX>,
+				<&cru CLK_PPLL_100M_MATRIX>,
+				<&cru CLK_PPLL_125M_MATRIX>,
+				<&cru ACLK_BUS_VOPGL_ROOT>;
+			assigned-clock-rates =
+				<32768>, <1188000000>,
+				<1000000000>, <996000000>,
+				<408000000>, <250000000>,
+				<500000000>,
+				<50000000>,
+				<100000000>,
+				<150000000>,
+				<200000000>,
+				<300000000>,
+				<340000000>,
+				<400000000>,
+				<600000000>,
+				<50000000>,
+				<100000000>,
+				<125000000>,
+				<500000000>;
+			clocks = <&xin24m>, <&gmac0_clk>;
+			clock-names = "xin24m", "gmac0";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		ioc_grf: syscon@ff540000 {
+			compatible = "rockchip,rk3528-ioc-grf", "syscon";
+			reg = <0x0 0xff540000 0x0 0x40000>;
+		};
+
 		uart0: serial@ff9f0000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xff9f0000 0x0 0x100>;
-			clock-frequency = <24000000>;
+			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -127,6 +383,8 @@
 		uart1: serial@ff9f8000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xff9f8000 0x0 0x100>;
+			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -136,6 +394,8 @@
 		uart2: serial@ffa00000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xffa00000 0x0 0x100>;
+			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -144,6 +404,8 @@

 		uart3: serial@ffa08000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+			clock-names = "baudclk", "apb_pclk";
 			reg = <0x0 0xffa08000 0x0 0x100>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -153,6 +415,8 @@
 		uart4: serial@ffa10000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xffa10000 0x0 0x100>;
+			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -162,6 +426,8 @@
 		uart5: serial@ffa18000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xffa18000 0x0 0x100>;
+			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -171,6 +437,8 @@
 		uart6: serial@ffa20000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xffa20000 0x0 0x100>;
+			clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -180,10 +448,118 @@
 		uart7: serial@ffa28000 {
 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
 			reg = <0x0 0xffa28000 0x0 0x100>;
+			clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+			clock-names = "baudclk", "apb_pclk";
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			status = "disabled";
 		};
+
+		saradc: adc@ffae0000 {
+			compatible = "rockchip,rk3528-saradc";
+			reg = <0x0 0xffae0000 0x0 0x10000>;
+			clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+			clock-names = "saradc", "apb_pclk";
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&cru SRST_P_SARADC>;
+			reset-names = "saradc-apb";
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
+		sdhci: mmc@ffbf0000 {
+			compatible = "rockchip,rk3528-dwcmshc",
+				     "rockchip,rk3588-dwcmshc";
+			reg = <0x0 0xffbf0000 0x0 0x10000>;
+			assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
+					  <&cru CCLK_SRC_EMMC>;
+			assigned-clock-rates = <200000000>, <24000000>,
+					       <200000000>;
+			clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+				 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+				 <&cru TCLK_EMMC>;
+			clock-names = "core", "bus", "axi", "block", "timer";
+			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			max-frequency = <200000000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+				    <&emmc_strb>;
+			resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+				 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+				 <&cru SRST_T_EMMC>;
+			reset-names = "core", "bus", "axi", "block", "timer";
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl {
+			compatible = "rockchip,rk3528-pinctrl";
+			rockchip,grf = <&ioc_grf>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gpio0: gpio@ff610000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0x0 0xff610000 0x0 0x200>;
+				clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 0 32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio1: gpio@ffaf0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0x0 0xffaf0000 0x0 0x200>;
+				clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 32 32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio@ffb00000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0x0 0xffb00000 0x0 0x200>;
+				clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 64 32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio@ffb10000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0x0 0xffb10000 0x0 0x200>;
+				clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 96 32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio@ffb20000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0x0 0xffb20000 0x0 0x200>;
+				clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-ranges = <&pinctrl 0 128 32>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+		};
 	};
 };
+
+#include "rk3528-pinctrl.dtsi"
--- a/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Firefly Technology Co. Ltd
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3576.dtsi"
+
+/ {
+	model = "Firefly ROC-RK3576-PC";
+	compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+
+	adc-keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-maskrom {
+			label = "Maskrom";
+			linux,code = <KEY_SETUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	adc-keys-1 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	vbus5v0_typec: regulator-vbus5v0-typec {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg0_pwren_h>;
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_device_s0>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v2_ufs_vccq_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc5v0_sys_s5>;
+	};
+
+	vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_ufs_vccq2_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc3v3_pcie: regulator-vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_pwren_h>;
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_rtc_s5";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys_s5>;
+	};
+
+	vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5vd_en>;
+		regulator-name = "vcc5v0_device";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3_host_pwren_h>;
+		regulator-name = "vcc5v0_host1";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_device_s0>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys_s5>;
+	};
+
+	vcc_1v8_s0: regulator-vcc-1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_2v0_pldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <2000000>;
+		regulator-max-microvolt = <2000000>;
+		vin-supply = <&vcc5v0_sys_s5>;
+	};
+
+	vcc_3v3_s0: regulator-vcc-3v3-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_ufs_s0: regulator-vcc-ufs-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_ufs_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys_s5>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth0m0_miim
+		     &eth0m0_tx_bus2
+		     &eth0m0_rx_bus2
+		     &eth0m0_rgmii_clk
+		     &eth0m0_rgmii_bus
+		     &ethm0_clk0_25m_out>;
+	/* Use rgmii-rxid mode to disable rx delay inside Soc */
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&rgmii_phy0>;
+	tx_delay = <0x21>;
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+		/* Reset time is 20ms, 100ms for rtl8211f */
+		reset-delay-us = <20000>;
+		reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <100000>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	pmic@23 {
+		compatible = "rockchip,rk806";
+		reg = <0x23>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys_s5>;
+		vcc2-supply = <&vcc5v0_sys_s5>;
+		vcc3-supply = <&vcc5v0_sys_s5>;
+		vcc4-supply = <&vcc5v0_sys_s5>;
+		vcc5-supply = <&vcc5v0_sys_s5>;
+		vcc6-supply = <&vcc5v0_sys_s5>;
+		vcc7-supply = <&vcc5v0_sys_s5>;
+		vcc8-supply = <&vcc5v0_sys_s5>;
+		vcc9-supply = <&vcc5v0_sys_s5>;
+		vcc10-supply = <&vcc5v0_sys_s5>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys_s5>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys_s5>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs1_slp: dvs1-slp-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs1_rst: dvs1-rst-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_slp: dvs2-slp-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs2_rst: dvs2-rst-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_dvs: dvs2-dvs-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs2_gpio: dvs2-gpio-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun5";
+		};
+
+		rk806_dvs3_slp: dvs3-slp-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs3_rst: dvs3-rst-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs3_dvs: dvs3-dvs-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs3_gpio: dvs3-gpio-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun5";
+		};
+
+		regulators {
+			vdd_cpu_big_s0: dcdc-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_big_s0";
+				regulator-enable-ramp-delay = <400>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_npu_s0: dcdc-reg2 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_npu_s0";
+				regulator-enable-ramp-delay = <400>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_gpu_s0: dcdc-reg5 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <800000>;
+				regulator-name = "vdd_logic_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdd_ddr_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo2_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo2_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdda_1v2_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_3v3_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo6_s3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_ddr_pll_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v75_hdmi_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <837500>;
+				regulator-max-microvolt = <837500>;
+				regulator-name = "vdda0v75_hdmi_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_0v85_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdda_0v75_s0";
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	/* pc9202 watchdog@3c with enable-gpio gpio0-c3 */
+
+	/* hnyetek,husb311 typec-portc@4e */
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int_l>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	full-pwr-cycle-in-suspend;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&pinctrl {
+	hym8563 {
+		rtc_int_l: rtc-int-l {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	power {
+		vcc5vd_en: vcc5vd-en {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_pwren_h: pcie-pwren-h {
+			rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		hub_reset_h: hub-reset-h {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb3_host_pwren_h: usb3-host-pwren-h {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb_otg0_pwren_h: usb-otg0-pwren-h {
+			rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usbc0_int_l: usbc0-int-l {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	watchdog {
+		wd_en: wd-en {
+			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0m0_xfer>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>;
+	status = "okay";
+};
+
+/* On the extension pin header */
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart6m3_xfer>;
+	status = "okay";
+};
--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -1260,6 +1260,45 @@
 			status = "disabled";
 		};

+		otp: otp@2a580000 {
+			compatible = "rockchip,rk3576-otp";
+			reg = <0x0 0x2a580000 0x0 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+				 <&cru CLK_OTP_PHY_G>;
+			clock-names = "otp", "apb_pclk", "phy";
+			resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
+			reset-names = "otp", "apb";
+
+			/* Data cells */
+			cpu_code: cpu-code@2 {
+				reg = <0x02 0x2>;
+			};
+			otp_cpu_version: cpu-version@5 {
+				reg = <0x05 0x1>;
+				bits = <3 3>;
+			};
+			otp_id: id@a {
+				reg = <0x0a 0x10>;
+			};
+			cpub_leakage: cpub-leakage@1e {
+				reg = <0x1e 0x1>;
+			};
+			cpul_leakage: cpul-leakage@1f {
+				reg = <0x1f 0x1>;
+			};
+			npu_leakage: npu-leakage@20 {
+				reg = <0x20 0x1>;
+			};
+			gpu_leakage: gpu-leakage@21 {
+				reg = <0x21 0x1>;
+			};
+			log_leakage: log-leakage@22 {
+				reg = <0x22 0x1>;
+			};
+		};
+
 		gic: interrupt-controller@2a701000 {
 			compatible = "arm,gic-400";
 			reg = <0x0 0x2a701000 0 0x10000>,
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -1921,6 +1921,14 @@
 		status = "disabled";
 	};

+	rng@fe378000 {
+		compatible = "rockchip,rk3588-rng";
+		reg = <0x0 0xfe378000 0x0 0x200>;
+		interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+		resets = <&scmi_reset 48>;
+	};
+
 	i2s0_8ch: i2s@fe470000 {
 		compatible = "rockchip,rk3588-i2s-tdm";
 		reg = <0x0 0xfe470000 0x0 0x1000>;
--- a/include/configs/anbernic-rgxx3-rk3566.h
+++ b/include/configs/anbernic-rgxx3-rk3566.h
@@ -3,10 +3,10 @@
 #ifndef __ANBERNIC_RGXX3_RK3566_H
 #define __ANBERNIC_RGXX3_RK3566_H

-#include <configs/rk3568_common.h>
-
 #define ROCKCHIP_DEVICE_SETTINGS \
 			"stdout=serial,vidconsole\0" \
 			"stderr=serial,vidconsole\0"

+#include <configs/rk3568_common.h>
+
 #endif
--- a/include/configs/evb_rk3568.h
+++ b/include/configs/evb_rk3568.h
@@ -6,10 +6,10 @@
 #ifndef __EVB_RK3568_H
 #define __EVB_RK3568_H

-#include <configs/rk3568_common.h>
-
 #define ROCKCHIP_DEVICE_SETTINGS \
 			"stdout=serial,vidconsole\0" \
 			"stderr=serial,vidconsole\0"

+#include <configs/rk3568_common.h>
+
 #endif
--- a/include/configs/evb_rk3588.h
+++ b/include/configs/evb_rk3588.h
@@ -6,10 +6,10 @@
 #ifndef __EVB_RK3588_H
 #define __EVB_RK3588_H

-#include <configs/rk3588_common.h>
-
 #define ROCKCHIP_DEVICE_SETTINGS \
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"

+#include <configs/rk3588_common.h>
+
 #endif
--- a/include/configs/khadas-edge2-rk3588s.h
+++ b/include/configs/khadas-edge2-rk3588s.h
@@ -6,10 +6,10 @@
 #ifndef __KHADAS_EDGE2_RK3588_H
 #define __KHADAS_EDGE2_RK3588_H

-#include <configs/rk3588_common.h>
-
 #define ROCKCHIP_DEVICE_SETTINGS \
 		"stdout=serial,vidconsole\0" \
 		"stderr=serial,vidconsole\0"

+#include <configs/rk3588_common.h>
+
 #endif /* __KHADAS_EDGE2_RK3588_H */
--- a/include/configs/powkiddy-x55-rk3566.h
+++ b/include/configs/powkiddy-x55-rk3566.h
@@ -3,10 +3,10 @@
 #ifndef __POWKIDDY_X55_RK3566_H
 #define __POWKIDDY_X55_RK3566_H

-#include <configs/rk3568_common.h>
-
 #define ROCKCHIP_DEVICE_SETTINGS \
 			"stdout=serial,vidconsole\0" \
 			"stderr=serial,vidconsole\0"

+#include <configs/rk3568_common.h>
+
 #endif
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -20,6 +20,7 @@
 	"scriptaddr=0x00500000\0" \
 	"pxefile_addr_r=0x00600000\0" \
 	"fdt_addr_r=0x08300000\0" \
+	"fdtoverlay_addr_r=0x08400000\0" \
 	"kernel_addr_r=0x00280000\0" \
 	"ramdisk_addr_r=0x0a200000\0" \
 	"kernel_comp_addr_r=0x03e80000\0" \
--- a/Show More
+++ b/Show More