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arch: layerscape: Add SFP binding

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This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
This commit is contained in:
Sean Anderson
2022-04-22 14:34:20 -04:00
committed by Peng Fan
parent f99068a8b1
commit 7041601141
4 changed files with 28 additions and 0 deletions
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7
arch/arm/dts/fsl-ls1012a.dtsi
View File

@@ -34,6 +34,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

7
arch/arm/dts/fsl-ls1043a.dtsi
View File

@@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

7
arch/arm/dts/fsl-ls1046a.dtsi
View File

@@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1046a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

7
arch/arm/dts/ls1021a.dtsi
View File

@@ -89,6 +89,13 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x10000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x1ee0000 0x10000>;