board: phytec: phycore-imx91-93: Add phyCORE-i.MX91 support

As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it to the existing board-code "phycore_imx93", and rename that board to "phycore_imx91_93" to reflect the dual SoCs support. While at it, also rename and change common files accordingly. This way i.MX91 and i.MX93 SoC variants of the phyCORE SoM share most of the code and documentation without duplication, while maintaining own device-tree and defconfigs for each CPU variant. Supported features: - 1GB LPDDR4 RAM - Debug UART - EEPROM - eMMC - Ethernet - SD-card - USB Product page SoM: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
2026-06-02 09:46:37 +03:00 · 2026-03-17 13:31:26 +01:00
parent 97979e894b
commit 77801f4b64
25 changed files with 2637 additions and 386 deletions
--- a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
+++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ *
+ */
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	aliases {
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+	};
+
+	bootstd {
+		bootph-verify;
+		compatible = "u-boot,boot-std";
+
+		filename-prefixes = "/", "/boot/";
+		bootdev-order = "mmc0", "mmc1", "ethernet";
+
+		rauc {
+			compatible = "u-boot,distro-rauc";
+		};
+
+		script {
+			compatible = "u-boot,script";
+		};
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_cd {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_default {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+
+	pmic@25 {
+		bootph-pre-ram;
+		bootph-some-ram;
+
+		regulators {
+			bootph-pre-ram;
+			bootph-some-ram;
+		};
+	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&wdog3 {
+	bootph-all;
+	bootph-pre-ram;
+};
--- a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ *
+ */
+
+#include "imx91-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"
+
+/ {
+	/*
+	 * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as
+	 * reference, but does only make use of its SoM (phyCORE) contained
+	 * periphery.
+	 */
+	model = "PHYTEC phyCORE-i.MX91";
+};
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -9,6 +9,7 @@
 */

 #include "imx93-u-boot.dtsi"
+#include "imx91-93-phyboard-segin-common-u-boot.dtsi"

 / {
 	/*
@@ -17,224 +18,4 @@
 	 * periphery.
 	 */
 	model = "PHYTEC phyCORE-i.MX93";
-
-	wdt-reboot {
-		compatible = "wdt-reboot";
-		wdt = <&wdog3>;
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-
-	aliases {
-		ethernet0 = &fec;
-		ethernet1 = &eqos;
-	};
-
-	bootstd {
-		bootph-verify;
-		compatible = "u-boot,boot-std";
-
-		filename-prefixes = "/", "/boot/";
-		bootdev-order = "mmc0", "mmc1", "ethernet";
-
-		rauc {
-			compatible = "u-boot,distro-rauc";
-		};
-
-		script {
-			compatible = "u-boot,script";
-		};
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-};
-
-&{/soc@0} {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&aips1 {
-	bootph-pre-ram;
-	bootph-all;
-};
-
-&aips2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&aips3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&iomuxc {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_reg_usdhc2_vmmc {
-	bootph-pre-ram;
-};
-
-&pinctrl_uart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc1_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_cd {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_default {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_100mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&pinctrl_usdhc2_200mhz {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpuart1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&usdhc2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-	fsl,signal-voltage-switch-extra-delay-ms = <8>;
-};
-
-&lpi2c1 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c2 {
-	bootph-pre-ram;
-	bootph-some-ram;
-};
-
-&lpi2c3 {
-	bootph-pre-ram;
-	bootph-some-ram;
-
-	pmic@25 {
-		bootph-pre-ram;
-		bootph-some-ram;
-
-		regulators {
-			bootph-pre-ram;
-			bootph-some-ram;
-		};
-	};
-
-	eeprom@50 {
-		bootph-pre-ram;
-		bootph-some-ram;
-	};
-};
-
-&s4muap {
-	bootph-pre-ram;
-	bootph-some-ram;
-	status = "okay";
-};
-
-&clk {
-	bootph-all;
-	bootph-pre-ram;
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
-	/delete-property/ assigned-clock-parents;
-};
-
-&osc_32k {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&osc_24m {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&clk_ext1 {
-	bootph-all;
-	bootph-pre-ram;
-};
-
-&wdog3 {
-	bootph-all;
-	bootph-pre-ram;
 };
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -129,6 +129,14 @@ config TARGET_KONTRON_MX93
 	  Kontron Electronics BL i.MX93 using SoM module conformant to OSM
 	  standard 1.1 size S.

+config TARGET_PHYCORE_IMX91
+	bool "phycore_imx91"
+	select IMX91
+	select IMX9_LPDDR4X
+	imply OF_UPSTREAM
+	select OF_BOARD_FIXUP
+	select OF_BOARD_SETUP
+
 config TARGET_PHYCORE_IMX93
 	bool "phycore_imx93"
 	select IMX93
@@ -181,7 +189,7 @@ source "board/nxp/imx93_evk/Kconfig"
 source "board/nxp/imx93_frdm/Kconfig"
 source "board/nxp/imx93_qsb/Kconfig"
 source "board/kontron/osm-s-mx93/Kconfig"
-source "board/phytec/phycore_imx93/Kconfig"
+source "board/phytec/phycore_imx91_93/Kconfig"
 source "board/variscite/imx93_var_som/Kconfig"
 source "board/nxp/imx94_evk/Kconfig"
 source "board/nxp/imx95_evk/Kconfig"
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob)
 	return 0;
 }

-#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \
+	!defined(CONFIG_TARGET_PHYCORE_IMX91)
 #ifndef CONFIG_XPL_BUILD
 int board_fix_fdt(void *fdt)
 {
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION
 	  Support of I2C EEPROM based SoM detection. Supported
 	  for PHYTEC i.MX8MM/i.MX8MP boards

-config PHYTEC_IMX93_SOM_DETECTION
-	bool "Support SoM detection for i.MX93 PHYTEC platforms"
+config PHYTEC_IMX91_93_SOM_DETECTION
+	bool "Support SoM detection for i.MX91/93 PHYTEC platforms"
 	depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
 	default y
 	help
 	  Support of I2C EEPROM based SoM detection. Supported
-	  for PHYTEC i.MX93 based boards
+	  for PHYTEC i.MX91/93 based boards

 config PHYTEC_AM62_SOM_DETECTION
 	bool "Support SoM detection for AM62x PHYTEC platforms"
--- a/board/phytec/common/Makefile
+++ b/board/phytec/common/Makefile
@@ -10,4 +10,4 @@ endif
 obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
 obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
 obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
-obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
+obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o
--- a/board/phytec/common/imx91_93_som_detection.c
+++ b/board/phytec/common/imx91_93_som_detection.c
@@ -10,18 +10,19 @@
 #include <i2c.h>
 #include <u-boot/crc.h>

-#include "imx93_som_detection.h"
+#include "imx91_93_som_detection.h"

 extern struct phytec_eeprom_data eeprom_data;

-#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
+#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION)

 /* Check if the SoM is actually one of the following products:
+ * - i.MX91
 * - i.MX93
 *
 * Returns 0 in case it's a known SoM. Otherwise, returns 1.
 */
-u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data)
 {
 	u8 som;

@@ -35,7 +36,7 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
 	som = data->payload.data.data_api2.som_no;
 	debug("%s: som id: %u\n", __func__, som);

-	if (som == PHYTEC_IMX93_SOM && is_imx93())
+	if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93()))
 		return 0;

 	pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
@@ -43,15 +44,15 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
 }

 /*
- * Filter PHYTEC i.MX93 SoM options by option index
+ * Filter PHYTEC i.MX91/93 SoM options by option index
 *
 * Returns:
 *  - option value
 *  - PHYTEC_EEPROM_INVAL when the data is invalid
 *
 */
-u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-				       enum phytec_imx93_option_index idx)
+u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+					  enum phytec_imx91_93_option_index idx)
 {
 	char *opt;
 	u8 opt_id;
@@ -73,39 +74,41 @@ u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
 }

 /*
- * Filter PHYTEC i.MX93 SoM voltage
+ * Filter PHYTEC i.MX91/93 SoM voltage
 *
 * Returns:
- *  - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
+ *  - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3
 *  - PHYTEC_EEPROM_INVAL when the data is invalid
 *
 */
-enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
+enum phytec_imx91_93_voltage __maybe_unused
+phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data)
 {
-	u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
+	u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT);

 	if (option == PHYTEC_EEPROM_INVAL)
-		return PHYTEC_IMX93_VOLTAGE_INVALID;
-	return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
+		return PHYTEC_IMX91_93_VOLTAGE_INVALID;
+	return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 :
+				 PHYTEC_IMX91_93_VOLTAGE_3V3;
 }

 #else

-inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
+inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data)
 {
 	return 1;
 }

-inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-					      enum phytec_imx93_option_index idx)
+inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+						 enum phytec_imx91_93_option_index idx)
 {
 	return PHYTEC_EEPROM_INVAL;
 }

-inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
+inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage
 	(struct phytec_eeprom_data *data)
 {
 	return PHYTEC_EEPROM_INVAL;
 }

-#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */
--- a/board/phytec/common/imx91_93_som_detection.h
+++ b/board/phytec/common/imx91_93_som_detection.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ * Author: Primoz Fiser <primoz.fiser@norik.com>
+ */
+
+#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H
+#define _PHYTEC_IMX91_93_SOM_DETECTION_H
+
+#include "phytec_som_detection.h"
+
+#define PHYTEC_IMX91_93_SOM	77
+
+enum phytec_imx91_93_option_index {
+	PHYTEC_IMX91_93_OPT_DDR = 0,
+	PHYTEC_IMX91_93_OPT_EMMC = 1,
+	PHYTEC_IMX91_93_OPT_CPU = 2,
+	PHYTEC_IMX91_93_OPT_FREQ = 3,
+	PHYTEC_IMX91_93_OPT_NPU = 4,
+	PHYTEC_IMX91_93_OPT_DISP = 5,
+	PHYTEC_IMX91_93_OPT_ETH = 6,
+	PHYTEC_IMX91_93_OPT_FEAT = 7,
+	PHYTEC_IMX91_93_OPT_TEMP = 8,
+	PHYTEC_IMX91_93_OPT_BOOT = 9,
+	PHYTEC_IMX91_93_OPT_LED = 10,
+	PHYTEC_IMX91_93_OPT_EEPROM = 11,
+};
+
+enum phytec_imx91_93_voltage {
+	PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX91_93_VOLTAGE_3V3 = 0,
+	PHYTEC_IMX91_93_VOLTAGE_1V8 = 1,
+};
+
+enum phytec_imx91_93_ddr_eeprom_code {
+	PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
+	PHYTEC_IMX91_93_LPDDR4X_512MB = 0,
+	PHYTEC_IMX91_93_LPDDR4X_1GB = 1,
+	PHYTEC_IMX91_93_LPDDR4X_2GB = 2,
+	PHYTEC_IMX91_93_LPDDR4_512MB = 3,
+	PHYTEC_IMX91_93_LPDDR4_1GB = 4,
+	PHYTEC_IMX91_93_LPDDR4_2GB = 5,
+};
+
+u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data);
+u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data,
+					  enum phytec_imx91_93_option_index idx);
+enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage
+	(struct phytec_eeprom_data *data);
+
+#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */
--- a/board/phytec/common/imx93_som_detection.h
+++ b/board/phytec/common/imx93_som_detection.h
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2024 PHYTEC Messtechnik GmbH
- * Author: Primoz Fiser <primoz.fiser@norik.com>
- */
-
-#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
-#define _PHYTEC_IMX93_SOM_DETECTION_H
-
-#include "phytec_som_detection.h"
-
-#define PHYTEC_IMX93_SOM	77
-
-enum phytec_imx93_option_index {
-	PHYTEC_IMX93_OPT_DDR = 0,
-	PHYTEC_IMX93_OPT_EMMC = 1,
-	PHYTEC_IMX93_OPT_CPU = 2,
-	PHYTEC_IMX93_OPT_FREQ = 3,
-	PHYTEC_IMX93_OPT_NPU = 4,
-	PHYTEC_IMX93_OPT_DISP = 5,
-	PHYTEC_IMX93_OPT_ETH = 6,
-	PHYTEC_IMX93_OPT_FEAT = 7,
-	PHYTEC_IMX93_OPT_TEMP = 8,
-	PHYTEC_IMX93_OPT_BOOT = 9,
-	PHYTEC_IMX93_OPT_LED = 10,
-	PHYTEC_IMX93_OPT_EEPROM = 11,
-};
-
-enum phytec_imx93_voltage {
-	PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
-	PHYTEC_IMX93_VOLTAGE_3V3 = 0,
-	PHYTEC_IMX93_VOLTAGE_1V8 = 1,
-};
-
-enum phytec_imx93_ddr_eeprom_code {
-	PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
-	PHYTEC_IMX93_LPDDR4X_512MB = 0,
-	PHYTEC_IMX93_LPDDR4X_1GB = 1,
-	PHYTEC_IMX93_LPDDR4X_2GB = 2,
-	PHYTEC_IMX93_LPDDR4_512MB = 3,
-	PHYTEC_IMX93_LPDDR4_1GB = 4,
-	PHYTEC_IMX93_LPDDR4_2GB = 5,
-};
-
-u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
-u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
-				       enum phytec_imx93_option_index idx);
-enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
-	(struct phytec_eeprom_data *data);
-
-#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
--- a/board/phytec/phycore_imx91_93/Kconfig
+++ b/board/phytec/phycore_imx91_93/Kconfig
@@ -0,0 +1,47 @@
+
+if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93
+
+config SYS_BOARD
+	default "phycore_imx91_93"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_imx91_93"
+
+config PHYCORE_IMX91_93_RAM_TYPE_FIX
+	bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting"
+	default false
+	help
+	  RAM type and size is being automatically detected with the help
+	  of the PHYTEC EEPROM introspection data.
+	  Set RAM type to a fix value instead.
+
+choice
+	prompt "phyCORE-i.MX91/93 RAM type"
+	depends on PHYCORE_IMX91_93_RAM_TYPE_FIX
+	default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB
+	bool "LPDDR4 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB
+	  for phyCORE-i.MX91/93.
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB
+	bool "LPDDR4X 1GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
+	  for phyCORE-i.MX91/93.
+
+config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB
+	bool "LPDDR4X 2GB RAM"
+	help
+	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
+	  for phyCORE-i.MX91/93.
+
+endchoice
+
+source "board/phytec/common/Kconfig"
+endif
--- a/board/phytec/phycore_imx91_93/MAINTAINERS
+++ b/board/phytec/phycore_imx91_93/MAINTAINERS
@@ -0,0 +1,16 @@
+phyCORE-i.MX91/93
+M:      Mathieu Othacehe <m.othacehe@gmail.com>
+R:      Christoph Stoidner <c.stoidner@phytec.de>
+L:      upstream@lists.phytec.de
+W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
+S:      Maintained
+F:      arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi
+F:      arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi
+F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+F:      board/phytec/phycore_imx91_93/
+F:      board/phytec/common/imx91_93_som_detection.c
+F:      board/phytec/common/imx91_93_som_detection.h
+F:      configs/imx91-phycore_defconfig
+F:      configs/imx93-phycore_defconfig
+F:      include/configs/phycore_imx91_93.h
+F:      doc/board/phytec/imx91-93-phycore.rst
--- a/board/phytec/phycore_imx91_93/Makefile
+++ b/board/phytec/phycore_imx91_93/Makefile
@@ -7,8 +7,13 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #

-obj-y += phycore-imx93.o
+obj-y += phycore-imx91-93.o

 ifdef CONFIG_XPL_BUILD
-obj-y += spl.o lpddr4_timing.o
+obj-y += spl.o
+ifdef CONFIG_IMX91
+obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o
+else
+obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o
+endif
 endif
--- a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c
+++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c
--- a/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c
+++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c
--- a/board/phytec/phycore_imx91_93/phycore-imx91-93.c
+++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c
@@ -11,7 +11,7 @@
 #include <env.h>
 #include <fdt_support.h>

-#include "../common/imx93_som_detection.h"
+#include "../common/imx91_93_som_detection.h"

 #define EEPROM_ADDR            0x50

@@ -55,13 +55,13 @@ int board_late_init(void)

 static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
 {
-	enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
+	enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data);
 	int offset;

-	if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
+	if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID)
 		goto err;

-	if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
+	if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) {
 		offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
 						       0x42850000);
 		if (offset)
--- a/board/phytec/phycore_imx91_93/phycore_imx91_93.env
+++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env
@@ -9,6 +9,8 @@ fdtoverlay_addr_r=0x900c0000
 ip_dyn=yes
 kernel_addr_r=0x88000000
 nfsroot=/srv/nfs
+#ifdef CONFIG_IMX93
 prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted"
+#endif
 scriptaddr=0x83500000
 sd_dev=1    /* This is needed by built-in uuu flash scripts */
--- a/board/phytec/phycore_imx91_93/spl.c
+++ b/board/phytec/phycore_imx91_93/spl.c
@@ -19,7 +19,7 @@
 #include <power/pca9450.h>
 #include <spl.h>

-#include "../common/imx93_som_detection.h"
+#include "../common/imx91_93_som_detection.h"

 DECLARE_GLOBAL_DATA_PTR;

@@ -50,32 +50,38 @@ void spl_board_init(void)
 void spl_dram_init(void)
 {
 	int ret;
-	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
+	enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID;

 	ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
-	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
+	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX))
 		goto out;

-	ret = phytec_imx93_detect(NULL);
+	ret = phytec_imx91_93_detect(NULL);
 	if (!ret)
 		phytec_print_som_info(NULL);

-	if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
-		if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
-			ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
-		else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
-			ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) {
+		if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB;
+		else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB))
+			ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB;
 	} else {
-		ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
+		ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR);
 	}

 	switch (ddr_opt) {
-	case PHYTEC_IMX93_LPDDR4X_1GB:
-		if (is_voltage_mode(VOLT_LOW_DRIVE))
+	case PHYTEC_IMX91_93_LPDDR4_1GB:
+		/* Timings statically set for i.MX91 LPDDR4 1GB. */
+		break;
+	case PHYTEC_IMX91_93_LPDDR4X_1GB:
+		if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE))
 			set_dram_timings_1gb_lpddr4x_900mhz();
 		break;
-	case PHYTEC_IMX93_LPDDR4X_2GB:
-		set_dram_timings_2gb_lpddr4x();
+	case PHYTEC_IMX91_93_LPDDR4X_2GB:
+		if (IS_ENABLED(CONFIG_IMX93))
+			set_dram_timings_2gb_lpddr4x();
 		break;
 	default:
 		goto out;
@@ -84,7 +90,7 @@ void spl_dram_init(void)
 	return;
 out:
 	puts("Could not detect correct RAM type and size. Fall back to default.\n");
-	if (is_voltage_mode(VOLT_LOW_DRIVE))
+	if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE))
 		set_dram_timings_1gb_lpddr4x_900mhz();
 	ddr_init(&dram_timing);
 }
@@ -185,10 +191,12 @@ void board_init_f(ulong dummy)
 	/* DDR initialization */
 	spl_dram_init();

-	/* Put M33 into CPUWAIT for following kick */
-	ret = m33_prepare();
-	if (!ret)
-		printf("M33 prepare ok\n");
+	if (IS_ENABLED(CONFIG_IMX93)) {
+		/* Put M33 into CPUWAIT for following kick */
+		ret = m33_prepare();
+		if (!ret)
+			printf("M33 prepare ok\n");
+	}

 	board_init_r(NULL, 0);
 }
--- a/board/phytec/phycore_imx93/Kconfig
+++ b/board/phytec/phycore_imx93/Kconfig
@@ -1,41 +0,0 @@
-
-if TARGET_PHYCORE_IMX93
-
-config SYS_BOARD
-	default "phycore_imx93"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_CONFIG_NAME
-	default "phycore_imx93"
-
-config PHYCORE_IMX93_RAM_TYPE_FIX
-	bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
-	default false
-	help
-	  RAM type and size is being automatically detected with the help
-	  of the PHYTEC EEPROM introspection data.
-	  Set RAM type to a fix value instead.
-
-choice
-	prompt "phyCORE-i.MX93 RAM type"
-	depends on PHYCORE_IMX93_RAM_TYPE_FIX
-	default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
-
-config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
-	bool "LPDDR4X 1GB RAM"
-	help
-	  Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
-	  for phyCORE-i.MX93.
-
-config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
-	bool "LPDDR4X 2GB RAM"
-	help
-	  Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
-	  for phyCORE-i.MX93.
-
-endchoice
-
-source "board/phytec/common/Kconfig"
-endif
--- a/board/phytec/phycore_imx93/MAINTAINERS
+++ b/board/phytec/phycore_imx93/MAINTAINERS
@@ -1,12 +0,0 @@
-phyCORE-i.MX93
-M:      Mathieu Othacehe <m.othacehe@gmail.com>
-R:      Christoph Stoidner <c.stoidner@phytec.de>
-L:      upstream@lists.phytec.de
-W:      https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
-S:      Maintained
-F:      arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
-F:      board/phytec/phycore_imx93/
-F:      board/phytec/common/imx93_som_detection.c
-F:      board/phytec/common/imx93_som_detection.h
-F:      configs/imx93-phycore_defconfig
-F:      include/configs/phycore_imx93.h
--- a/configs/imx91-phycore_defconfig
+++ b/configs/imx91-phycore_defconfig
@@ -0,0 +1,167 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SOURCE_FILE="phycore_imx91_93"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_PHYTEC_SOM_DETECTION=y
+CONFIG_PHYTEC_EEPROM_BUS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-phyboard-segin"
+CONFIG_TARGET_PHYCORE_IMX91=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x204E0000
+CONFIG_SPL_TEXT_BASE=0x204A0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x20498000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x720000
+CONFIG_CMD_DEKBLOB=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_BOOTDEV is not set
+# CONFIG_CMD_BOOTMETH is not set
+# CONFIG_CMD_BOOTSTD is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_SIZE=4096
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_REDUNDANT=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_MMC_DEVICE_INDEX=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK_IMX93=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_GPIO_HOG=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY_TI_GENERIC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PCA9450=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PCA9450=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_ULP_WATCHDOG=y
+# CONFIG_RSA is not set
+# CONFIG_SPL_SHA256 is not set
+CONFIG_LZO=y
+CONFIG_BZIP2=y
--- a/configs/imx93-phycore_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x20000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SOURCE_FILE="phycore_imx93"
+CONFIG_ENV_SOURCE_FILE="phycore_imx91_93"
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_PHYTEC_SOM_DETECTION=y
 CONFIG_PHYTEC_EEPROM_BUS=2
--- a/doc/board/phytec/imx91-93-phycore.rst
+++ b/doc/board/phytec/imx91-93-phycore.rst
@@ -1,9 +1,11 @@
 .. SPDX-License-Identifier: GPL-2.0+

-phyCORE-i.MX 93
-===============
+phyCORE-i.MX 91/93
+==================

-U-Boot for the phyCORE-i.MX 93.
+U-Boot for the phyCORE-i.MX 91/93. Both SoC variants, that is i.MX 91 and i.MX 93,
+are supported by same board code, however each variant uses different defconfig
+and ATF/ELE firmware blobs. Please follow the correct steps for the populated SoC.

 Quick Start
 -----------
@@ -18,7 +20,17 @@ Get and Build the ARM Trusted firmware

 Note: srctree is U-Boot source directory
 Get ATF from: https://github.com/nxp-imx/imx-atf/
-branch: lf_v2.8
+branch: lf_v2.12
+
+For phyCORE-i.MX 91 variant:
+
+.. code-block:: bash
+
+   $ unset LDFLAGS
+   $ make PLAT=imx91 bl31
+   $ cp build/imx91/release/bl31.bin $(srctree)
+
+For phyCORE-i.MX 93 variant:

 .. code-block:: bash

@@ -41,14 +53,24 @@ Get ahab-container.img

 .. code-block:: bash

-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin
-   $ chmod +x firmware-sentinel-0.11.bin
-   $ ./firmware-sentinel-0.11.bin
-   $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree)
+   $ wget  https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
+   $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
+   $ ./firmware-ele-imx-1.3.0-17945fc.bin
+   $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
+   $ cp firmware-ele-imx-1.3.0-17945fc/mx93a1-ahab-container.img $(srctree)

 Build U-Boot
 ------------

+For phyCORE-i.MX 91 variant:
+
+.. code-block:: bash
+
+   $ make imx91-phycore_defconfig
+   $ make
+
+For phyCORE-i.MX 93 variant:
+
 .. code-block:: bash

   $ make imx93-phycore_defconfig
--- a/doc/board/phytec/index.rst
+++ b/doc/board/phytec/index.rst
@@ -8,7 +8,7 @@ PHYTEC

   imx8mp-libra-fpsc
   imx8mm-phygate-tauri-l
-   imx93-phycore
+   imx91-93-phycore
   phycore-am62x
   phycore-am62ax
   phycore-am64x
--- a/include/configs/phycore_imx91_93.h
+++ b/include/configs/phycore_imx91_93.h
@@ -6,8 +6,8 @@
 * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
 */

-#ifndef __PHYCORE_IMX93_H
-#define __PHYCORE_IMX93_H
+#ifndef __PHYCORE_IMX91_93_H
+#define __PHYCORE_IMX91_93_H

 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
@@ -25,4 +25,4 @@
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR          WDG3_BASE_ADDR

-#endif /* __PHYCORE_IMX93_H */
+#endif /* __PHYCORE_IMX91_93_H */