Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

clk: k210: Move soc_clk_dump function

Browse Source 
Move clock dump function to avoid forward declaration after switching to
dump in clk_ops.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-4-ivprusov@sberdevices.ru
This commit is contained in:
Igor Prusov
2023-11-09 13:55:11 +03:00
committed by Sean Anderson
parent 3f192541df
commit 77beaad3d1
1 changed files with 46 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
drivers/clk/clk_k210.c
View File

@@ -1239,52 +1239,6 @@ static int k210_clk_request(struct clk *clk)
return 0;
}
static const struct clk_ops k210_clk_ops = {
.request = k210_clk_request,
.set_rate = k210_clk_set_rate,
.get_rate = k210_clk_get_rate,
.set_parent = k210_clk_set_parent,
.enable = k210_clk_enable,
.disable = k210_clk_disable,
};
static int k210_clk_probe(struct udevice *dev)
{
int ret;
struct k210_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr_ptr(dev_get_parent(dev));
if (!priv->base)
return -EINVAL;
ret = clk_get_by_index(dev, 0, &priv->in0);
if (ret)
return ret;
/*
* Force setting defaults, even before relocation. This is so we can
* set the clock rate for PLL1 before we relocate into aisram.
*/
if (!(gd->flags & GD_FLG_RELOC))
clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
return 0;
}
static const struct udevice_id k210_clk_ids[] = {
{ .compatible = "canaan,k210-clk" },
{ },
};
U_BOOT_DRIVER(k210_clk) = {
.name = "k210_clk",
.id = UCLASS_CLK,
.of_match = k210_clk_ids,
.ops = &k210_clk_ops,
.probe = k210_clk_probe,
.priv_auto = sizeof(struct k210_clk_priv),
};
#if IS_ENABLED(CONFIG_CMD_CLK)
static char show_enabled(struct k210_clk_priv *priv, int id)
{
@@ -1343,3 +1297,49 @@ int soc_clk_dump(void)
return 0;
}
#endif
static const struct clk_ops k210_clk_ops = {
.request = k210_clk_request,
.set_rate = k210_clk_set_rate,
.get_rate = k210_clk_get_rate,
.set_parent = k210_clk_set_parent,
.enable = k210_clk_enable,
.disable = k210_clk_disable,
};
static int k210_clk_probe(struct udevice *dev)
{
int ret;
struct k210_clk_priv *priv = dev_get_priv(dev);
priv->base = dev_read_addr_ptr(dev_get_parent(dev));
if (!priv->base)
return -EINVAL;
ret = clk_get_by_index(dev, 0, &priv->in0);
if (ret)
return ret;
/*
* Force setting defaults, even before relocation. This is so we can
* set the clock rate for PLL1 before we relocate into aisram.
*/
if (!(gd->flags & GD_FLG_RELOC))
clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
return 0;
}
static const struct udevice_id k210_clk_ids[] = {
{ .compatible = "canaan,k210-clk" },
{ },
};
U_BOOT_DRIVER(k210_clk) = {
.name = "k210_clk",
.id = UCLASS_CLK,
.of_match = k210_clk_ids,
.ops = &k210_clk_ops,
.probe = k210_clk_probe,
.priv_auto = sizeof(struct k210_clk_priv),
};