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clk: renesas: Synchronize R8A779F0 S4 clock tables with Linux 6.5.3

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Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2023-09-17 16:11:36 +02:00
parent 2387f5613d
commit 79d4ef4b47
2 changed files with 3 additions and 3 deletions
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4
drivers/clk/renesas/r8a779f0-cpg-mssr.c
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@@ -47,7 +47,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a779f0_core_clks[] = {
static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] = {
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),

2
include/dt-bindings/clock/r8a779f0-cpg-mssr.h
View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/