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Merge tag 'u-boot-stm32-20260430' of https://source.denx.de/u-boot/custodians/u-boot-stm

Browse Source 
- arm; stm32mp2: Factorize TAMP_FWU_BOOT_IDX_MASK/OFFSET definition
- arm: stm32mp: Drop unnecessary BOARD_EARLY_INIT_F usage
- board: stm32mp25: support dynamic A/B bank bootup
- board: stm32pm1: Fix board_check_usb_power()
- clk: stm32: Add STM32MP23 support
- video: stm32: dsi: fix unchecked return values
- video: support Rocktech RK050HR345-CT106A panel
- Remove non-existent STM32_RESET flag
This commit is contained in:
Tom Rini
2026-04-30 09:10:18 -06:00
parent 9d3bc111ef ae1966e243
commit 817653c53d
20 changed files with 523 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-stm32/Kconfig
View File

@@ -10,7 +10,6 @@ config STM32F4
select PINCTRL_STM32
select RAM
select STM32_RCC
select STM32_RESET
select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
@@ -27,7 +26,6 @@ config STM32F7
select PINCTRL_STM32
select RAM
select STM32_RCC
select STM32_RESET
select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER
@@ -47,7 +45,6 @@ config STM32H7
select RAM
select REGMAP
select STM32_RCC
select STM32_RESET
select STM32_SDRAM
select STM32_SERIAL
select STM32_TIMER

4
arch/arm/mach-stm32mp/Kconfig
View File

@@ -50,7 +50,6 @@ config STM32MP13X
select OF_BOARD_SETUP
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select SUPPORT_SPL if !TFABOOT
select SYS_ARCH_TIMER
@@ -72,7 +71,6 @@ config STM32MP15X
select OF_BOARD_SETUP
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select SUPPORT_SPL
select SYS_ARCH_TIMER
@@ -91,7 +89,6 @@ config STM32MP21X
select OF_BOARD
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select STM32MP_TAMP_NVMEM
select SYS_ARCH_TIMER
@@ -143,7 +140,6 @@ config STM32MP25X
select OF_BOARD
select PINCTRL_STM32
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
select SYS_ARCH_TIMER
select TFABOOT

8
arch/arm/mach-stm32mp/include/mach/stm32.h
View File

@@ -135,6 +135,9 @@ enum forced_boot_mode {
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
#ifdef CONFIG_STM32MP15X
#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
@@ -144,9 +147,6 @@ enum forced_boot_mode {
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
#define TAMP_COPRO_STATE_OFF 0
#define TAMP_COPRO_STATE_INIT 1
#define TAMP_COPRO_STATE_CRUN 2
@@ -196,8 +196,6 @@ enum forced_boot_mode {
/* TAMP registers zone 3 RIF 1 (RW) at 96*/
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
#endif /* defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */
/* offset used for BSEC driver: misc_read and misc_write */

15
arch/arm/mach-stm32mp/stm32mp1/spl.c
View File

@@ -90,11 +90,6 @@ void spl_display_print(void)
}
#endif
__weak int board_early_init_f(void)
{
return 0;
}
uint32_t stm32mp_get_dram_size(void)
{
struct ram_info ram;
@@ -204,10 +199,12 @@ void board_init_f(ulong dummy)
/* enable console uart printing */
preloader_console_init();
ret = board_early_init_f();
if (ret) {
log_debug("board_early_init_f() failed: %d\n", ret);
hang();
if (IS_ENABLED(CONFIG_BOARD_EARLY_INIT_F)) {
ret = board_early_init_f();
if (ret) {
log_debug("board_early_init_f() failed: %d\n", ret);
hang();
}
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);

8
arch/sandbox/include/asm/test.h
View File

@@ -243,6 +243,14 @@ uint sandbox_spi_get_speed(struct udevice *dev);
*/
uint sandbox_spi_get_mode(struct udevice *dev);
/**
* sandbox_spi_get_wordlen() - Get current wordlen setting of a sandbox spi slave
*
* @dev: Device to check
* Return: current wordlen
*/
uint sandbox_spi_get_wordlen(struct udevice *dev);
/**
* sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
*

6
board/engicam/stm32mp1/spl.c
View File

@@ -15,9 +15,3 @@ void board_vddcore_init(u32 voltage_mv)
if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER))
opp_voltage_mv = voltage_mv;
}
int board_early_init_f(void)
{
return 0;
}

5
board/st/stm32h750-art-pi/stm32h750-art-pi.c
View File

@@ -32,11 +32,6 @@ int dram_init_banksize(void)
return 0;
}
int board_early_init_f(void)
{
return 0;
}
int board_late_init(void)
{
return 0;

7
board/st/stm32mp1/stm32mp1.c
View File

@@ -326,8 +326,8 @@ static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV)
static int board_check_usb_power(void)
{
ofnode node;
int max_uV = 0;
int min_uV = USB_START_HIGH_THRESHOLD_UV;
int max_uV;
int min_uV;
int adc_count, ret;
u32 nb_blink;
u8 i;
@@ -358,6 +358,9 @@ static int board_check_usb_power(void)
/* perform maximum of 2 ADC measurements to detect power supply current */
for (i = 0; i < 2; i++) {
max_uV = 0;
min_uV = USB_START_HIGH_THRESHOLD_UV;
ret = adc_measurement(node, adc_count, &min_uV, &max_uV);
if (ret)
return ret;

1
configs/stm32h750-art-pi_defconfig
View File

@@ -24,7 +24,6 @@ CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_BOARD_INIT is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "

2
drivers/clk/stm32/Kconfig
View File

@@ -49,7 +49,7 @@ config CLK_STM32MP21
config CLK_STM32MP25
bool "Enable RCC clock driver for STM32MP25"
depends on ARCH_STM32MP && CLK
default y if STM32MP25X
default y if STM32MP23X || STM32MP25X
select CLK_STM32_CORE
help
Enable the STM32 clock (RCC) driver. Enable support for

2
drivers/spi/Kconfig
View File

@@ -565,7 +565,7 @@ config SPI_SUNXI
config STM32_OSPI
bool "STM32MP2 OSPI driver"
depends on STM32MP25X && STM32_OMM
depends on (STM32MP23X || STM32MP25X) && STM32_OMM
help
Enable the STM32MP2 Octo-SPI (OSPI) driver. This driver can be
used to access the SPI NOR flash chips on platforms embedding

17
drivers/spi/sandbox_spi.c
View File

@@ -61,6 +61,22 @@ uint sandbox_spi_get_mode(struct udevice *dev)
return priv->mode;
}
uint sandbox_spi_get_wordlen(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
return slave->wordlen;
}
static int sandbox_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
slave->wordlen = wordlen;
return 0;
}
static int sandbox_spi_xfer(struct udevice *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -158,6 +174,7 @@ static const struct dm_spi_ops sandbox_spi_ops = {
.set_mode = sandbox_spi_set_mode,
.cs_info = sandbox_cs_info,
.get_mmap = sandbox_spi_get_mmap,
.set_wordlen = sandbox_spi_set_wordlen,
};
static const struct udevice_id sandbox_spi_ids[] = {

22
drivers/spi/spi-uclass.c
View File

@@ -88,6 +88,20 @@ void dm_spi_release_bus(struct udevice *dev)
ops->release_bus(dev);
}
int dm_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
{
struct udevice *bus = dev->parent;
struct dm_spi_ops *ops = spi_get_ops(bus);
if (bus->uclass->uc_drv->id != UCLASS_SPI)
return -EOPNOTSUPP;
if (!ops->set_wordlen)
return -ENOSYS;
return ops->set_wordlen(dev, wordlen);
}
int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -141,6 +155,11 @@ int spi_set_speed(struct spi_slave *slave, uint hz)
return ret;
}
int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen)
{
return dm_spi_set_wordlen(slave->dev, wordlen);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -245,6 +264,7 @@ static int spi_child_post_bind(struct udevice *dev)
}
plat->mode = mode;
plat->wordlen = SPI_DEFAULT_WORDLEN;
return 0;
}
@@ -277,7 +297,7 @@ static int spi_child_pre_probe(struct udevice *dev)
slave->max_hz = plat->max_hz;
slave->mode = plat->mode;
slave->wordlen = SPI_DEFAULT_WORDLEN;
slave->wordlen = plat->wordlen;
return 0;
}

71
drivers/spi/stm32_spi.c
View File

@@ -192,6 +192,11 @@ static void stm32_spi_read_rxfifo(struct udevice *bus)
log_debug("%d bytes left\n", priv->rx_len);
}
static bool stm32_spi_is_enabled(void __iomem *base)
{
return !!(readl(base + STM32_SPI_CR1) & SPI_CR1_SPE);
}
static int stm32_spi_enable(void __iomem *base)
{
log_debug("\n");
@@ -245,9 +250,7 @@ static void stm32_spi_stopxfer(struct udevice *dev)
dev_dbg(dev, "\n");
cr1 = readl(base + STM32_SPI_CR1);
if (!(cr1 & SPI_CR1_SPE))
if (!stm32_spi_is_enabled(base))
return;
/* Wait on EOT or suspend the flow */
@@ -381,6 +384,44 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz)
return 0;
}
static int _stm32_spi_set_wordlen(struct udevice *bus, unsigned int wordlen)
{
struct stm32_spi_priv *priv = dev_get_priv(bus);
struct stm32_spi_plat *plat = dev_get_plat(bus);
void __iomem *base = plat->base;
bool spi_enabled;
if ((wordlen - 1) < SPI_CFG1_DSIZE_MIN ||
(wordlen - 1) > SPI_CFG1_DSIZE) {
dev_err(bus, "Cannot set wordlen to %u [%d - %ld]\n",
wordlen, SPI_CFG1_DSIZE_MIN + 1,
SPI_CFG1_DSIZE + 1);
return -EINVAL;
}
spi_enabled = stm32_spi_is_enabled(plat->base);
if (spi_enabled)
stm32_spi_disable(plat->base);
dev_dbg(bus, "bits_per_word=%d\n", wordlen);
priv->cur_bpw = wordlen;
clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
priv->cur_bpw - 1);
if (spi_enabled)
stm32_spi_enable(plat->base);
return 0;
}
static int stm32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
{
struct udevice *bus = dev_get_parent(slave);
return _stm32_spi_set_wordlen(bus, wordlen);
}
static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
@@ -394,18 +435,28 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
u32 xferlen;
u32 mode;
int xfer_status = 0;
int nb_words;
xferlen = bitlen / 8;
if (xferlen <= SPI_CR2_TSIZE)
writel(xferlen, base + STM32_SPI_CR2);
if (priv->cur_bpw <= 8)
nb_words = xferlen;
else if (priv->cur_bpw <= 16)
nb_words = DIV_ROUND_UP(xferlen * 8, 16);
else
nb_words = DIV_ROUND_UP(xferlen * 8, 32);
if (nb_words <= SPI_CR2_TSIZE)
writel(nb_words, base + STM32_SPI_CR2);
else
return -EMSGSIZE;
priv->tx_buf = dout;
priv->rx_buf = din;
priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
priv->tx_len = priv->tx_buf ? xferlen : 0;
priv->rx_len = priv->rx_buf ? xferlen : 0;
dev_dbg(bus, "bitlen: %d, xferlen: %d, nb_words: %d\n",
bitlen, xferlen, nb_words);
mode = SPI_FULL_DUPLEX;
if (!priv->tx_buf)
@@ -567,9 +618,7 @@ static int stm32_spi_probe(struct udevice *dev)
priv->fifo_size = stm32_spi_get_fifo_size(dev);
priv->cur_mode = SPI_FULL_DUPLEX;
priv->cur_xferlen = 0;
priv->cur_bpw = SPI_DEFAULT_WORDLEN;
clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
priv->cur_bpw - 1);
_stm32_spi_set_wordlen(dev, SPI_DEFAULT_WORDLEN);
for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
if (!dm_gpio_is_valid(&plat->cs_gpios[i]))
@@ -630,10 +679,12 @@ static const struct dm_spi_ops stm32_spi_ops = {
.release_bus = stm32_spi_release_bus,
.set_mode = stm32_spi_set_mode,
.set_speed = stm32_spi_set_speed,
.set_wordlen = stm32_spi_set_wordlen,
.xfer = stm32_spi_xfer,
};
static const struct udevice_id stm32_spi_ids[] = {
{ .compatible = "st,stm32mp25-spi", },
{ .compatible = "st,stm32h7-spi", },
{ }
};

8
drivers/video/Kconfig
View File

@@ -552,6 +552,14 @@ config VIDEO_LCD_HIMAX_HX8394
Say Y here if you want to enable support for Himax HX8394
dsi 4dl panel.
config VIDEO_LCD_ILITEK_ILI9806E
bool "Ilitek ILI9806E-based panels"
depends on PANEL && BACKLIGHT
help
Say Y here if you want to enable support for panels base on
the Ilitek ILI9806E controller. Currently only the DBI panel
is implemented.
config VIDEO_LCD_MOT
tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel"
depends on PANEL && BACKLIGHT

1
drivers/video/Makefile
View File

@@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA) += hitachi-tx10d07vm0baa.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_ILITEK_ILI9806E) += ilitek-ili9806e.o
obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
obj-$(CONFIG_VIDEO_LCD_LG_LH400WV3) += lg-lh400wv3-sd04.o
obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o

356
drivers/video/ilitek-ili9806e.c Normal file
View File

@@ -0,0 +1,356 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
*/
#include <backlight.h>
#include <dm.h>
#include <mipi_display.h>
#include <panel.h>
#include <spi.h>
#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
#include <power/regulator.h>
struct ilitek_ili9806e_priv {
struct udevice *vdd;
struct udevice *backlight;
struct gpio_desc reset_gpio;
const struct ilitek_ili9806e_desc *desc;
};
struct ilitek_ili9806e_desc {
const struct display_timing timing;
void (*init_sequence)(struct udevice *dev);
};
static int ilitek_ili9806e_dcs_write(struct udevice *dev, u8 cmd, const u8 *seq, int len)
{
u16 data[16];
int i, ret;
if ((len + 1) > ARRAY_SIZE(data)) {
dev_err(dev, "Command length (%d) exceeds buffer size (%lu)\n",
len + 1, ARRAY_SIZE(data));
return -EMSGSIZE;
}
data[0] = cmd;
if (len) {
for (i = 0; i < len; i++)
data[i + 1] = seq[i] | 0x0100;
}
ret = dm_spi_xfer(dev, (len + 1) * 8 * sizeof(u16), data, NULL,
SPI_XFER_ONCE);
return 0;
}
#define ilitek_ili9806e_dcs_write_seq(dev, cmd, seq...) \
({ \
static const u8 b[] = { seq }; \
ilitek_ili9806e_dcs_write(dev, cmd, b, ARRAY_SIZE(b)); \
})
static int ilitek_ili9806e_enable_backlight(struct udevice *dev)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
const struct ilitek_ili9806e_desc *desc = priv->desc;
desc->init_sequence(dev);
return panel_set_backlight(dev, BACKLIGHT_DEFAULT);
}
static int ilitek_ili9806e_set_backlight(struct udevice *dev, int percent)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
int ret;
ret = backlight_enable(priv->backlight);
if (ret) {
dev_err(dev, "Cannot enable backlight\n");
return ret;
}
ret = backlight_set_brightness(priv->backlight, percent);
if (ret)
dev_err(dev, "Cannot set backlight brightness\n");
return ret;
}
static int ilitek_ili9806e_get_display_timing(struct udevice *dev,
struct display_timing *timing)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
memcpy(timing, &priv->desc->timing, sizeof(*timing));
return 0;
}
static int ilitek_ili9806e_of_to_plat(struct udevice *dev)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
int ret;
if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
if (ret) {
dev_err(dev, "Cannot get vdd supply\n");
return ret;
}
}
ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
"backlight", &priv->backlight);
if (ret) {
dev_err(dev, "Cannot get backlight\n");
return ret;
}
ret = gpio_request_by_name(dev, "reset-gpios", 0,
&priv->reset_gpio, GPIOD_IS_OUT);
if (ret) {
dev_err(dev, "Cannot get reset GPIO\n");
return ret;
}
return 0;
}
static int ilitek_ili9806e_hw_init(struct udevice *dev)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
int ret;
ret = dm_gpio_set_value(&priv->reset_gpio, 1);
if (ret) {
dev_err(dev, "Cannot enter reset\n");
return ret;
}
ret = regulator_set_enable_if_allowed(priv->vdd, 1);
if (ret) {
dev_err(dev, "Cannot enable vdd-supply\n");
return ret;
}
mdelay(20);
ret = dm_gpio_set_value(&priv->reset_gpio, 0);
if (ret) {
dev_err(dev, "Cannot exit reset\n");
return ret;
}
mdelay(20);
return 0;
}
static int ilitek_ili9806e_probe(struct udevice *dev)
{
struct ilitek_ili9806e_priv *priv = dev_get_priv(dev);
struct spi_slave *slave = dev_get_parent_priv(dev);
int ret;
ret = spi_set_wordlen(slave, 9);
if (ret) {
dev_err(dev, "Cannot set SPI.bits_per_word\n");
return ret;
}
ret = spi_claim_bus(slave);
if (ret) {
dev_err(dev, "Cannot get SPI bus\n");
return ret;
}
priv->desc = (struct ilitek_ili9806e_desc *)dev_get_driver_data(dev);
return ilitek_ili9806e_hw_init(dev);
}
static const struct panel_ops ilitek_ili9806e_ops = {
.enable_backlight = ilitek_ili9806e_enable_backlight,
.set_backlight = ilitek_ili9806e_set_backlight,
.get_display_timing = ilitek_ili9806e_get_display_timing,
};
static void rk050hr345_ct106a_init(struct udevice *dev)
{
/* Switch to page 1 */
ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
/* Interface Settings */
ilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x10);
ilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x01);
/* Panel Settings */
ilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x00);
/* Power Control */
ilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x15);
ilitek_ili9806e_dcs_write_seq(dev, 0x41, 0x44);
ilitek_ili9806e_dcs_write_seq(dev, 0x42, 0x03);
ilitek_ili9806e_dcs_write_seq(dev, 0x43, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0x44, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0x50, 0x78);
ilitek_ili9806e_dcs_write_seq(dev, 0x51, 0x78);
ilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x3a);
ilitek_ili9806e_dcs_write_seq(dev, 0x57, 0x50);
/* Timing Control */
ilitek_ili9806e_dcs_write_seq(dev, 0x60, 0x07);
ilitek_ili9806e_dcs_write_seq(dev, 0x61, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x62, 0x08);
ilitek_ili9806e_dcs_write_seq(dev, 0x63, 0x00);
/* Gamma Settings */
ilitek_ili9806e_dcs_write_seq(dev, 0xa0, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0xa1, 0x03);
ilitek_ili9806e_dcs_write_seq(dev, 0xa2, 0x0b);
ilitek_ili9806e_dcs_write_seq(dev, 0xa3, 0x0f);
ilitek_ili9806e_dcs_write_seq(dev, 0xa4, 0x0b);
ilitek_ili9806e_dcs_write_seq(dev, 0xa5, 0x1b);
ilitek_ili9806e_dcs_write_seq(dev, 0xa6, 0x0a);
ilitek_ili9806e_dcs_write_seq(dev, 0xa7, 0x0a);
ilitek_ili9806e_dcs_write_seq(dev, 0xa8, 0x02);
ilitek_ili9806e_dcs_write_seq(dev, 0xa9, 0x07);
ilitek_ili9806e_dcs_write_seq(dev, 0xaa, 0x05);
ilitek_ili9806e_dcs_write_seq(dev, 0xab, 0x03);
ilitek_ili9806e_dcs_write_seq(dev, 0xac, 0x0e);
ilitek_ili9806e_dcs_write_seq(dev, 0xad, 0x32);
ilitek_ili9806e_dcs_write_seq(dev, 0xae, 0x2d);
ilitek_ili9806e_dcs_write_seq(dev, 0xaf, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0xc0, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0xc1, 0x03);
ilitek_ili9806e_dcs_write_seq(dev, 0xc2, 0x0e);
ilitek_ili9806e_dcs_write_seq(dev, 0xc3, 0x10);
ilitek_ili9806e_dcs_write_seq(dev, 0xc4, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0xc5, 0x17);
ilitek_ili9806e_dcs_write_seq(dev, 0xc6, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0xc7, 0x07);
ilitek_ili9806e_dcs_write_seq(dev, 0xc8, 0x04);
ilitek_ili9806e_dcs_write_seq(dev, 0xc9, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0xca, 0x06);
ilitek_ili9806e_dcs_write_seq(dev, 0xcb, 0x06);
ilitek_ili9806e_dcs_write_seq(dev, 0xcc, 0x0c);
ilitek_ili9806e_dcs_write_seq(dev, 0xcd, 0x25);
ilitek_ili9806e_dcs_write_seq(dev, 0xce, 0x20);
ilitek_ili9806e_dcs_write_seq(dev, 0xcf, 0x00);
/* Switch to page 6 */
ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
/* GIP settings */
ilitek_ili9806e_dcs_write_seq(dev, 0x00, 0x21);
ilitek_ili9806e_dcs_write_seq(dev, 0x01, 0x09);
ilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x03, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x04, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x05, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x06, 0x80);
ilitek_ili9806e_dcs_write_seq(dev, 0x07, 0x05);
ilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x02);
ilitek_ili9806e_dcs_write_seq(dev, 0x09, 0x80);
ilitek_ili9806e_dcs_write_seq(dev, 0x0a, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x0b, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x0c, 0x0a);
ilitek_ili9806e_dcs_write_seq(dev, 0x0d, 0x0a);
ilitek_ili9806e_dcs_write_seq(dev, 0x0e, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x0f, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x10, 0xe0);
ilitek_ili9806e_dcs_write_seq(dev, 0x11, 0xe4);
ilitek_ili9806e_dcs_write_seq(dev, 0x12, 0x04);
ilitek_ili9806e_dcs_write_seq(dev, 0x13, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x14, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x15, 0xc0);
ilitek_ili9806e_dcs_write_seq(dev, 0x16, 0x08);
ilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x18, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x19, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x1a, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x1b, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x1c, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x1d, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x20, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x23);
ilitek_ili9806e_dcs_write_seq(dev, 0x22, 0x45);
ilitek_ili9806e_dcs_write_seq(dev, 0x23, 0x67);
ilitek_ili9806e_dcs_write_seq(dev, 0x24, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x25, 0x23);
ilitek_ili9806e_dcs_write_seq(dev, 0x26, 0x45);
ilitek_ili9806e_dcs_write_seq(dev, 0x27, 0x67);
ilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01);
ilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x11);
ilitek_ili9806e_dcs_write_seq(dev, 0x32, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, 0x33, 0xee);
ilitek_ili9806e_dcs_write_seq(dev, 0x34, 0xff);
ilitek_ili9806e_dcs_write_seq(dev, 0x35, 0xbb);
ilitek_ili9806e_dcs_write_seq(dev, 0x36, 0xca);
ilitek_ili9806e_dcs_write_seq(dev, 0x37, 0xdd);
ilitek_ili9806e_dcs_write_seq(dev, 0x38, 0xac);
ilitek_ili9806e_dcs_write_seq(dev, 0x39, 0x76);
ilitek_ili9806e_dcs_write_seq(dev, 0x3a, 0x67);
ilitek_ili9806e_dcs_write_seq(dev, 0x3b, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x3c, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x3d, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x3e, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x3f, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x10);
ilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x10);
/* Switch to page 7 */
ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
ilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x22);
ilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x77);
ilitek_ili9806e_dcs_write_seq(dev, 0xe1, 0x79);
ilitek_ili9806e_dcs_write_seq(dev, 0xb3, 0x10);
/* Switch to page 0 */
ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_ON);
mdelay(120);
}
static const struct ilitek_ili9806e_desc rk050hr345_ct106a_desc = {
.timing = {
.pixelclock.typ = 27000000,
.hactive.typ = 480,
.hfront_porch.typ = 10,
.hback_porch.typ = 10,
.hsync_len.typ = 10,
.vactive.typ = 854,
.vfront_porch.typ = 10,
.vback_porch.typ = 10,
.vsync_len.typ = 10,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
},
.init_sequence = rk050hr345_ct106a_init,
};
static const struct udevice_id ilitek_ili9806e_ids[] = {
{
.compatible = "rocktech,rk050hr345-ct106a",
.data = (ulong)&rk050hr345_ct106a_desc,
},
{ }
};
U_BOOT_DRIVER(ilitek_ili9806e) = {
.name = "ilitek_ili9806e",
.id = UCLASS_PANEL,
.of_match = ilitek_ili9806e_ids,
.ops = &ilitek_ili9806e_ops,
.of_to_plat = ilitek_ili9806e_of_to_plat,
.probe = ilitek_ili9806e_probe,
.priv_auto = sizeof(struct ilitek_ili9806e_priv),
.flags = DM_FLAG_PRE_RELOC,
};

7
drivers/video/stm32/stm32_dsi.c
View File

@@ -493,8 +493,11 @@ static int stm32_dsi_probe(struct udevice *dev)
priv->hw_version != HWVER_131) {
dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
dev_dbg(dev, "remove and unbind all DSI child\n");
device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
device_chld_unbind(dev, NULL);
ret = device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
if (!ret)
ret = device_chld_unbind(dev, NULL);
if (ret)
dev_err(dev, "Unbinding from %s failed %d\n", dev->name, ret);
ret = -ENODEV;
goto err_clk;
}

14
include/spi.h
View File

@@ -77,11 +77,13 @@ struct dm_spi_bus {
* @cs: Chip select number (0..n-1)
* @max_hz: Maximum bus speed that this slave can tolerate
* @mode: SPI mode to use for this device (see SPI mode flags)
* @wordlen: Word length in bits to use for this device
*/
struct dm_spi_slave_plat {
unsigned int cs[SPI_CS_CNT_MAX];
uint max_hz;
uint mode;
unsigned int wordlen;
};
/**
@@ -718,6 +720,18 @@ int dm_spi_claim_bus(struct udevice *dev);
*/
void dm_spi_release_bus(struct udevice *dev);
/**
* Set the word length for SPI transactions
*
* Set the word length (number of bits per word) for SPI transactions.
*
* @slave: The SPI slave
* @wordlen: The number of bits in a word
*
* Returns: 0 on success, -1 on failure.
*/
int dm_spi_set_wordlen(struct udevice *dev, unsigned int wordlen);
/**
* SPI transfer
*

16
test/dm/spi.c
View File

@@ -170,6 +170,22 @@ static int dm_test_spi_claim_bus(struct unit_test_state *uts)
}
DM_TEST(dm_test_spi_claim_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_spi_set_wordlen(struct unit_test_state *uts)
{
struct spi_slave *slave;
struct udevice *bus;
const int busnum = 0, cs = 0;
ut_assertok(spi_get_bus_and_cs(busnum, cs, &bus, &slave));
ut_assertok(spi_set_wordlen(slave, 8));
ut_asserteq(8, sandbox_spi_get_wordlen(slave->dev));
ut_assertok(spi_set_wordlen(slave, 9));
ut_asserteq(9, sandbox_spi_get_wordlen(slave->dev));
return 0;
}
DM_TEST(dm_test_spi_set_wordlen, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox SPI works correctly */
static int dm_test_spi_xfer(struct unit_test_state *uts)
{