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spi: cadence_qspi: pulse controller reset at probe

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The driver previously only deasserted the optional bulk reset,
leaving the controller in whatever state earlier stages left it and
risking failed probes or bad transfers. Assert the reset first, wait
10 µs, and then deassert so the OSPI block starts from a known state.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260215151639.3472200-1-padmarao.begari@amd.com
This commit is contained in:
Padmarao Begari
2026-02-15 20:46:26 +05:30
committed by Michal Simek
parent 1dcaeffc9c
commit 834d589b8f
1 changed files with 18 additions and 2 deletions
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20
drivers/spi/cadence_qspi.c
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@@ -13,6 +13,7 @@
#include <spi.h>
#include <spi-mem.h>
#include <dm/device_compat.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
@@ -254,8 +255,23 @@ static int cadence_spi_probe(struct udevice *bus)
}
priv->resets = devm_reset_bulk_get_optional(bus);
if (priv->resets)
reset_deassert_bulk(priv->resets);
if (priv->resets) {
/* Assert all OSPI reset lines */
ret = reset_assert_bulk(priv->resets);
if (ret) {
dev_err(bus, "Failed to assert OSPI reset: %d\n", ret);
return ret;
}
udelay(10);
/* Deassert all OSPI reset lines */
ret = reset_deassert_bulk(priv->resets);
if (ret) {
dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret);
return ret;
}
}
if (!priv->qspi_is_init) {
cadence_qspi_apb_controller_init(priv);