Merge patch series "Cumulative fixes and updates for MediaTek platform"

Weijie Gao <weijie.gao@mediatek.com> says: This patch series contains fixes and updates for MediaTek platform, including drivers, board and arch files. Link: https://lore.kernel.org/r/cover.1737104723.git.weijie.gao@mediatek.com
2026-06-13 15:03:58 +03:00 · 2025-01-23 08:20:42 -06:00
parent e67cbd7aba 8707ea0360
commit 8352727e33
19 changed files with 353 additions and 29 deletions
--- a/5
+++ b/5
@@ -412,9 +412,13 @@ F:	drivers/mmc/mtk-sd.c
 F:	drivers/phy/phy-mtk-*
 F:	drivers/pinctrl/mediatek/
 F:	drivers/power/domain/mtk-power-domain.c
+F:	drivers/pci/pcie_mediatek_gen3.c
+F:	drivers/pci/pcie_mediatek.c
+F:	drivers/pwm/pwm-mtk.c
 F:	drivers/ram/mediatek/
 F:	drivers/spi/mtk_snfi_spi.c
 F:	drivers/spi/mtk_spim.c
+F:	drivers/spi/mtk_snor.c
 F:	drivers/timer/mtk_timer.c
 F:	drivers/usb/host/xhci-mtk.c
 F:	drivers/usb/mtu3/
@@ -422,6 +426,7 @@ F:	drivers/watchdog/mtk_wdt.c
 F:	drivers/net/mtk_eth.c
 F:	drivers/net/mtk_eth.h
 F:	drivers/reset/reset-mediatek.c
+F:	drivers/serial/serial_mtk.c
 F:	include/dt-bindings/clock/mediatek,*
 F:	include/dt-bindings/power/mediatek,*
 F:	tools/mtk_image.c
--- a/arch/arm/dts/mt7981-emmc-rfb.dts
+++ b/arch/arm/dts/mt7981-emmc-rfb.dts
@@ -95,6 +95,14 @@
 		};
 	};

+	/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+	three_pwm_pins_1: three-pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0_0", "pwm1_1", "pwm2";
+		};
+	};
+
 	mmc0_pins_default: mmc0default {
 		mux {
 			function = "flash";
--- a/arch/arm/dts/mt7981-rfb.dts
+++ b/arch/arm/dts/mt7981-rfb.dts
@@ -123,6 +123,14 @@
 			groups = "pwm0_1", "pwm1_0", "pwm2";
 		};
 	};
+
+	/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+	three_pwm_pins_1: three-pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0_0", "pwm1_1", "pwm2";
+		};
+	};
 };

 &spi0 {
@@ -143,6 +151,8 @@
 		compatible = "spi-nand";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

@@ -164,6 +174,8 @@
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -95,6 +95,14 @@
 		};
 	};

+	/* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */
+	three_pwm_pins_1: three-pwm-pins {
+		mux {
+			function = "pwm";
+			groups = "pwm0_0", "pwm1_1", "pwm2";
+		};
+	};
+
 	mmc0_pins_default: mmc0default {
 		mux {
 			function = "flash";
@@ -110,7 +118,7 @@
 		};
 		conf-clk {
 			pins = "SPI1_CS";
-			drive-strength = <MTK_DRIVE_6mA>;
+			drive-strength = <MTK_DRIVE_8mA>;
 			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 		};
 		conf-rst {
@@ -132,10 +140,12 @@
 };

 &mmc0 {
+	assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
+				 <&topckgen CLK_TOP_CB_NET2_D2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_default>;
 	bus-width = <4>;
-	max-frequency = <52000000>;
+	max-frequency = <50000000>;
 	cap-sd-highspeed;
 	r_smpl = <0>;
 	vmmc-supply = <&reg_3p3v>;
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -137,8 +137,14 @@
 			 <&infracfg CLK_INFRA_PWM1_CK>,
 			 <&infracfg CLK_INFRA_PWM2_CK>,
 			 <&infracfg CLK_INFRA_PWM3_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
+		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+				  <&infracfg CLK_INFRA_PWM1_SEL>,
+				  <&infracfg CLK_INFRA_PWM2_SEL>,
+				  <&infracfg CLK_INFRA_PWM3_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+					 <&topckgen CLK_TOP_PWM_SEL>,
+					 <&topckgen CLK_TOP_PWM_SEL>,
+					 <&topckgen CLK_TOP_PWM_SEL>;
 		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 		status = "disabled";
 	};
@@ -300,13 +306,13 @@
 		reg = <0x11230000 0x1000>,
 		      <0x11C20000 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_EMMC_400M>,
-			 <&topckgen CLK_TOP_EMMC_208M>,
+		clocks = <&topckgen CLK_TOP_EMMC_208M>,
+			 <&topckgen CLK_TOP_EMMC_400M>,
 			 <&infracfg CLK_INFRA_MSDC_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_208M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
-					 <&topckgen CLK_TOP_CB_M_D2>;
+		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+					 <&topckgen CLK_TOP_CB_NET2_D2>;
 		clock-names = "source", "hclk", "source_cg";
 		status = "disabled";
 	};
--- a/arch/arm/dts/mt7986a-rfb.dts
+++ b/arch/arm/dts/mt7986a-rfb.dts
@@ -190,12 +190,16 @@
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};

 	spi_nand@1 {
 		compatible = "spi-nand";
 		reg = <1>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

--- a/arch/arm/dts/mt7986b-rfb.dts
+++ b/arch/arm/dts/mt7986b-rfb.dts
@@ -177,12 +177,16 @@
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};

 	spi_nand@1 {
 		compatible = "spi-nand";
 		reg = <1>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

--- a/arch/arm/dts/mt7988-rfb.dts
+++ b/arch/arm/dts/mt7988-rfb.dts
@@ -50,19 +50,36 @@
 	status = "okay";
 };

-&eth {
+&eth0 {
 	status = "okay";
-	mediatek,gmac-id = <0>;
 	phy-mode = "usxgmii";
 	mediatek,switch = "mt7988";

 	fixed-link {
-		speed = <1000>;
+		speed = <10000>;
 		full-duplex;
 		pause;
 	};
 };

+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+/* PCIE2 not working in u-boot */
+&pcie2 {
+	status = "disabled";
+};
+
+/* PCIE3 not working in u-boot */
+&pcie3 {
+	status = "disabled";
+};
+
 &pinctrl {
 	i2c1_pins: i2c1-pins {
 		mux {
@@ -84,6 +101,19 @@
 			function = "spi";
 			groups = "spi0", "spi0_wp_hold";
 		};
+
+		conf-pu {
+			pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+
 	};

 	spi2_pins: spi2-pins {
@@ -91,6 +121,18 @@
 			function = "spi";
 			groups = "spi2", "spi2_wp_hold";
 		};
+
+		conf-pu {
+			pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
 	};

 	mmc0_pins_default: mmc0default {
@@ -104,18 +146,25 @@
 			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 			input-enable;
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
 		};

 		conf-clk {
 			pins = "EMMC_CK";
+			drive-strength = <MTK_DRIVE_6mA>;
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
 		};

 		conf-dsl {
 			pins = "EMMC_DSL";
+			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
 		};

 		conf-rst {
 			pins = "EMMC_RSTB";
+			drive-strength = <MTK_DRIVE_4mA>;
+			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
 		};
 	};
 };
@@ -144,6 +193,8 @@
 		compatible = "spi-nand";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

@@ -165,6 +216,8 @@
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <52000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
 	};
 };

--- a/arch/arm/dts/mt7988-sd-rfb.dts
+++ b/arch/arm/dts/mt7988-sd-rfb.dts
@@ -41,14 +41,13 @@
 	status = "okay";
 };

-&eth {
+&eth0 {
 	status = "okay";
-	mediatek,gmac-id = <0>;
 	phy-mode = "usxgmii";
 	mediatek,switch = "mt7988";

 	fixed-link {
-		speed = <1000>;
+		speed = <10000>;
 		full-duplex;
 		pause;
 	};
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -188,6 +188,152 @@
 		status = "okay";
 	};

+	pcie2: pcie@11280000 {
+		compatible = "mediatek,mt7988-pcie",
+			     "mediatek,mt7986-pcie",
+			     "mediatek,mt8192-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0 0x11280000 0 0x2000>;
+		reg-names = "pcie-mac";
+		linux,pci-domain = <3>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
+		clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+			 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+			 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+			 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+		clock-names = "pl_250m", "tl_26m", "peri_26m",
+			      "top_133m";
+		phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+		phy-names = "pcie-phy";
+
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+				<0 0 0 2 &pcie_intc2 1>,
+				<0 0 0 3 &pcie_intc2 2>,
+				<0 0 0 4 &pcie_intc2 3>;
+
+		pcie_intc2: interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+	};
+
+	pcie3: pcie@11290000 {
+		compatible = "mediatek,mt7988-pcie",
+			     "mediatek,mt7986-pcie",
+			     "mediatek,mt8192-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0 0x11290000 0 0x2000>;
+		reg-names = "pcie-mac";
+		linux,pci-domain = <2>;
+		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
+		clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+			 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+			 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+			 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+		clock-names = "pl_250m", "tl_26m", "peri_26m",
+			      "top_133m";
+		use-dedicated-phy;
+
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+				<0 0 0 2 &pcie_intc3 1>,
+				<0 0 0 3 &pcie_intc3 2>,
+				<0 0 0 4 &pcie_intc3 3>;
+		pcie_intc3: interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+	};
+
+	pcie0: pcie@11300000 {
+		compatible = "mediatek,mt7988-pcie",
+			     "mediatek,mt7986-pcie",
+			     "mediatek,mt8192-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0 0x11300000 0 0x2000>;
+		reg-names = "pcie-mac";
+		linux,pci-domain = <0>;
+		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
+		clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+			 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+			 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+			 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+		clock-names = "pl_250m", "tl_26m", "peri_26m",
+			      "top_133m";
+		use-dedicated-phy;
+
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+				<0 0 0 2 &pcie_intc0 1>,
+				<0 0 0 3 &pcie_intc0 2>,
+				<0 0 0 4 &pcie_intc0 3>;
+		pcie_intc0: interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+	};
+
+	pcie1: pcie@11310000 {
+		compatible = "mediatek,mt7988-pcie",
+			     "mediatek,mt7986-pcie",
+			     "mediatek,mt8192-pcie";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		reg = <0 0x11310000 0 0x2000>;
+		reg-names = "pcie-mac";
+		linux,pci-domain = <1>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		bus-range = <0x00 0xff>;
+		ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
+		clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+			 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+			 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+			 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+		clock-names = "pl_250m", "tl_26m", "peri_26m",
+			      "top_133m";
+		use-dedicated-phy;
+
+		status = "disabled";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+				<0 0 0 2 &pcie_intc1 1>,
+				<0 0 0 3 &pcie_intc1 2>,
+				<0 0 0 4 &pcie_intc1 3>;
+		pcie_intc1: interrupt-controller {
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+		};
+	};
+
 	usbtphy: usb-phy@11c50000 {
 		compatible = "mediatek,mt7988",
 			     "mediatek,generic-tphy-v2";
@@ -215,6 +361,22 @@
 		};
 	};

+	xphy: xphy@11e10000 {
+		compatible = "mediatek,mt7988", "mediatek,xsphy";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		xphyu3port0: usb-phy@11e13000 {
+			reg = <0 0x11e13400 0 0x500>;
+			clocks = <&dummy_clk>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+			status = "okay";
+		};
+	};
+
 	xfi_pextp0: syscon@11f20000 {
 		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
 		reg = <0 0x11f20000 0 0x10000>;
@@ -425,11 +587,11 @@
 		#reset-cells = <1>;
 	};

-	eth: ethernet@15100000 {
+	eth0: ethernet@15110100 {
 		compatible = "mediatek,mt7988-eth", "syscon";
 		reg = <0 0x15100000 0 0x20000>;
+		mediatek,gmac-id = <0>;
 		mediatek,ethsys = <&ethdma>;
-		mediatek,sgmiisys = <&sgmiisys0>;
 		mediatek,usxgmiisys = <&usxgmiisys0>;
 		mediatek,xfi_pextp = <&xfi_pextp0>;
 		mediatek,xfi_pll = <&xfi_pll>;
@@ -442,4 +604,42 @@
 		mediatek,mcm;
 		status = "disabled";
 	};
+
+	eth1: ethernet@15110200 {
+		compatible = "mediatek,mt7988-eth", "syscon";
+		reg = <0 0x15100000 0 0x20000>;
+		mediatek,gmac-id = <1>;
+		mediatek,ethsys = <&ethdma>;
+		mediatek,sgmiisys = <&sgmiisys1>;
+		mediatek,usxgmiisys = <&usxgmiisys1>;
+		mediatek,xfi_pextp = <&xfi_pextp1>;
+		mediatek,xfi_pll = <&xfi_pll>;
+		mediatek,infracfg = <&topmisc>;
+		mediatek,toprgu = <&watchdog>;
+		resets = <&ethdma ETHDMA_FE_RST>;
+		reset-names = "fe";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mediatek,mcm;
+		status = "disabled";
+	};
+
+	eth2: ethernet@15110300 {
+		compatible = "mediatek,mt7988-eth", "syscon";
+		reg = <0 0x15100000 0 0x20000>;
+		mediatek,gmac-id = <2>;
+		mediatek,ethsys = <&ethdma>;
+		mediatek,sgmiisys = <&sgmiisys0>;
+		mediatek,usxgmiisys = <&usxgmiisys0>;
+		mediatek,xfi_pextp = <&xfi_pextp0>;
+		mediatek,xfi_pll = <&xfi_pll>;
+		mediatek,infracfg = <&topmisc>;
+		mediatek,toprgu = <&watchdog>;
+		resets = <&ethdma ETHDMA_FE_RST>;
+		reset-names = "fe";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mediatek,mcm;
+		status = "disabled";
+	};
 };
--- a/board/mediatek/mt7622/mt7622_rfb.c
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -15,10 +15,3 @@ int board_init(void)
 {
 	return 0;
 }
-
-int board_late_init(void)
-{
-	gd->env_valid = 1; //to load environment variable from persistent store
-	env_relocate();
-	return 0;
-}
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000
 CONFIG_SPL_TEXT_BASE=0x201000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_SYS_LOAD_ADDR=0x42007f1c
+CONFIG_SYS_LOAD_ADDR=0x42000000
 CONFIG_SPL_PAYLOAD="u-boot-lzma.img"
 CONFIG_BUILD_TARGET="u-boot-mtk.bin"
 CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin"
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
 CONFIG_TARGET_MT7988=y
-CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SYS_LOAD_ADDR=0x44000000
 CONFIG_DEBUG_UART_BASE=0x11000000
 CONFIG_DEBUG_UART_CLOCK=40000000
 CONFIG_DEBUG_UART=y
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
 		.id = _id, .mux_reg = (_reg) + 0x8,                            \
 		.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4,      \
 		.mux_shift = _shift, .mux_mask = BIT(_width) - 1,              \
+		.gate_shift = -1, .upd_shift = -1,			       \
 		.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
 		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
 	}
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
 		.id = _id, .mux_reg = (_reg) + 0x8,                            \
 		.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4,      \
 		.mux_shift = _shift, .mux_mask = BIT(_width) - 1,              \
+		.gate_shift = -1, .upd_shift = -1,			       \
 		.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
 		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED,                \
 	}
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
 		.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0,   \
 		.mux_clr_reg = _reg + 0x4, .mux_shift = _shift,                \
 		.mux_mask = BIT(_width) - 1, .parent = _parents,               \
+		.gate_shift = -1, .upd_shift = -1,			       \
 		.num_parents = ARRAY_SIZE(_parents),                           \
 		.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN,             \
 	}
--- a/drivers/pci/pcie_mediatek_gen3.c
+++ b/drivers/pci/pcie_mediatek_gen3.c
@@ -83,6 +83,28 @@ struct mtk_pcie {
 	struct phy phy;
 };

+static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf)
+{
+	int bdfs[3];
+
+	bdfs[0] = PCI_BUS(bdf);
+	bdfs[1] = PCI_DEV(bdf);
+	bdfs[2] = PCI_FUNC(bdf);
+
+	/*
+	 * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on
+	 * this port represents the controller itself and bus 1 represents the
+	 * external PCIe device. If multiple PCIe controllers are probed in U-Boot,
+	 * U-Boot will use bus numbers greater than 2 as input parameters. Therefore,
+	 * we should convert the BDF bus number to either 0 or 1 by subtracting the
+	 * offset by controller->seq_
+	 */
+
+	bdfs[0] = bdfs[0] - controller->seq_;
+
+	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
+}
+
 static void mtk_pcie_config_tlp_header(const struct udevice *bus,
 				       pci_dev_t devfn,
 				       int where, int size)
@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(const struct udevice *bus,
 	int bytes;
 	u32 val;

+	devfn = convert_bdf(bus, devfn);
+
 	size = 1 << size;
 	bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3);

--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_data = {
 };

 static const struct mtk_pwm_soc mt7981_data = {
-	.num_pwms = 2,
+	.num_pwms = 3,
 	.pwm45_fixup = false,
 	.reg_ver = PWM_REG_V2,
 };
--- a/drivers/spi/mtk_spim.c
+++ b/drivers/spi/mtk_spim.c
@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct spi_slave *slave,
 	struct udevice *bus = dev_get_parent(slave->dev);
 	struct mtk_spim_priv *priv = dev_get_priv(bus);

+	if (!spi_mem_default_supports_op(slave, op))
+		return false;
+
 	if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 ||
 	    op->addr.buswidth > 4 || op->dummy.buswidth > 4 ||
 	    op->data.buswidth > 4)
@@ -648,7 +651,7 @@ static int mtk_spim_probe(struct udevice *dev)
 	struct mtk_spim_priv *priv = dev_get_priv(dev);
 	int ret;

-	priv->base = devfdt_get_addr_ptr(dev);
+	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -EINVAL;