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thermal: imx_tmu: extend with QorIQ/Layerscape TMU
Add support for the on-die Thermal Monitoring Unit (TMU) of the new QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...): examples on a lx2160: => temperature list | Device | Driver | Parent | tmu@1f80000 | imx_tmu | root_driver | cluster67-thermal | imx_tmu | tmu@1f80000 | ddr1-cluster5-thermal | imx_tmu | tmu@1f80000 | wriop-thermal | imx_tmu | tmu@1f80000 | dce-qbman-hsio2-thermal | imx_tmu | tmu@1f80000 | ccn-dpaa-tbu-thermal | imx_tmu | tmu@1f80000 | cluster4-hsio3-thermal | imx_tmu | tmu@1f80000 | cluster23-thermal | imx_tmu | tmu@1f80000 => temperature get tmu@1f80000 tmu@1f80000: 82000 mC => temperature get wriop-thermal wriop-thermal: 81000 mC The parent tmu@... node owns the MMIO and calibration; one UCLASS_THERMAL device is bound per/thermal-zones site so each shows up by its zone name: => dm tree ... thermal 2 [ + ] imx_tmu |-- tmu@1f80000 thermal 3 [ + ] imx_tmu | |-- cluster67-thermal thermal 4 [ + ] imx_tmu | |-- ddr1-cluster5-thermal thermal 5 [ + ] imx_tmu | |-- wriop-thermal thermal 6 [ + ] imx_tmu | |-- dce-qbman-hsio2-thermal thermal 7 [ + ] imx_tmu | |-- ccn-dpaa-tbu-thermal thermal 8 [ + ] imx_tmu | |-- cluster4-hsio3-thermal thermal 9 [ + ] imx_tmu | `-- cluster23-thermal ... The dtsi additions mirror the existing fsl-ls1028a.dtsi: the LX2160A SoC dtsi gains the tmu@1f80000 node plus a thermal-zones hierarchy with 7 sites: cluster67-thermal site 0 A72 clusters 6 + 7 ddr1-cluster5-thermal site 1 DDR1 + A72 cluster 5 wriop-thermal site 2 WRIOP dce-qbman-hsio2-thermal site 3 DCE + QBMAN + HSIO2 ccn-dpaa-tbu-thermal site 4 CCN508 + DPAA + TBU cluster4-hsio3-thermal site 5 A72 cluster 4 + HSIO3 cluster23-thermal site 6 A72 clusters 2 + 3 Signed-off-by: Vincent Jardin <vjardin@free.fr> Suggested-by: Tom Rini <trini@konsulko.com> Inspired-by: Peng Fan <peng.fan@oss.nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Vincent Jardin
@@ -986,6 +986,27 @@ uint get_svr(void)
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}
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#endif
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/*
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* Layerscape mirror of the i.MX get_cpu_temp_grade(). i.MX reads the
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* OCOTP "CPU temp grade" fuses; Layerscape has no such fuse, so the
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* limits come from the data sheet instead. LX2160A Reference Manual
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* Rev. 1 (10/2021) section 1.12.1 specifies the maximum operating
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* junction temperature at 105 degC for commercial / embedded parts;
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* the lower bound is the standard -40 degC commercial low.
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*
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* The TMU itself is documented as accurate within +/- 3 degC (RM
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* section 28.1), which the thermal driver clears by setting its
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* alert threshold 10 degC below critical.
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*/
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u32 get_cpu_temp_grade(int *minc, int *maxc)
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{
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if (minc)
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*minc = -40;
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if (maxc)
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*maxc = 105;
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return 0; /* commercial */
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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@@ -594,6 +594,64 @@
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};
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};
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/* LX2160ARM Chapter 28 ("Thermal Monitoring Unit") */
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tmu: tmu@1f80000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f80000 0x0 0x10000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tmu-range = <0x800000e6 0x8001017d>;
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fsl,tmu-calibration = <0x00000000 0x00000035
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0x00000001 0x00000154>;
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little-endian;
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#thermal-sensor-cells = <1>;
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label = "lx2160a-tmu"; /* explicit naming */
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};
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/* explicit thermal-zones names per LX2160ARM Table 323 */
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thermal-zones {
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cluster67-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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};
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ddr1-cluster5-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 1>;
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};
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wriop-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 2>;
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};
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dce-qbman-hsio2-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 3>;
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};
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ccn-dpaa-tbu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 4>;
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};
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cluster4-hsio3-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 5>;
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};
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cluster23-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 6>;
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};
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};
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/* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
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emdio1: mdio@8b96000 {
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compatible = "fsl,ls-mdio";
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30
arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
Normal file
30
arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h
Normal file
@@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2026 Free Mobile - Vincent Jardin
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*
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* Layerscape mirror of the i.MX <asm/mach-imx/sys_proto.h>: declares
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* the SoC-personality helpers consumed by generic drivers that work on
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* both i.MX and QorIQ/Layerscape parts (e.g. drivers/thermal/imx_tmu.c
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* for the QorIQ TMU variant).
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*/
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#ifndef _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H
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#define _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H
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#include <linux/types.h>
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/*
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* Per LX2160A Reference Manual, Rev. 1 (10/2021):
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* - section 1.12.1: "NXP specs max power at 105 degC junction" for
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* commercial / embedded operating conditions.
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* - section 28.1: TMU "Accuracy within +/- 3 degC".
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*
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* Layerscape SoCs do not expose an OCOTP-style "CPU temp grade" fuse,
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* so the implementation returns the documented junction-temperature
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* limit from the data sheet (-40 .. 105 degC commercial range). The
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* thermal driver subtracts 10 degC for its alert threshold, which
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* comfortably clears the +/- 3 degC TMU accuracy in both directions.
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*/
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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#endif /* _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H */
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@@ -27,11 +27,12 @@ config IMX_SCU_THERMAL
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trip is crossed
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config IMX_TMU
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bool "Thermal Management Unit driver for NXP i.MX8M and iMX93"
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depends on ARCH_IMX8M || IMX93
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bool "Thermal Management Unit driver for NXP i.MX8M / i.MX93 and QorIQ"
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depends on ARCH_IMX8M || IMX93 || FSL_LAYERSCAPE
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help
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Support for Temperature sensors on NXP i.MX8M and iMX93.
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It supports one critical trip point and one passive trip point.
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Support for the NXP Thermal Management Unit (TMU) sensors on
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i.MX8M, i.MX93 and on QorIQ/Layerscape SoCs (LX2160A,
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LS1028A, LS1088A, ...).
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The boot is hold to the cool device to throttle CPUs when the
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passive trip is crossed
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@@ -6,14 +6,17 @@
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93)
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#include <asm/arch/clock.h>
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#endif
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/device-internal.h>
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#include <dm/device.h>
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#include <errno.h>
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#include <fuse.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <malloc.h>
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#include <thermal.h>
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@@ -22,10 +25,12 @@
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#define FLAGS_VER2 0x1
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#define FLAGS_VER3 0x2
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#define FLAGS_VER4 0x4
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#define FLAGS_QORIQ 0x8
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#define TMR_DISABLE 0x0
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#define TMR_ME 0x80000000
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#define TMR_ALPF 0x0c000000
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#define QORIQ_TMR_ALPF (0x3 << 24) /* QorIQ ALPF lives at bits[25:24] */
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#define TMTMIR_DEFAULT 0x00000002
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#define TIER_DISABLE 0x0
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@@ -33,7 +38,19 @@
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#define TER_ADC_PD 0x40000000
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#define TER_ALPF 0x3
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/* default CPU delay time to cool down if over temperature */
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#define IMX_TMU_POLLING_DELAY_MS 5000
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/* TRITSR - QorIQ Immediate Temperature Site Register.
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*
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* Per LX2160A Reference Manual, Rev. 1 (10/2021) section 28.3.1.24
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* the calibrated reading lives in TEMP[8:0] and is reported in
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* degrees Kelvin (integer). The QorIQ regs_v1 variant has no
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* fractional 0.5 degC bit, unlike the i.MX regs_v2 / VER4 layouts.
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*/
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#define TRITSR_V BIT(31) /* reading valid */
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#define TRITSR_TEMP_MASK GENMASK(8, 0) /* degrees Kelvin */
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#define TRITSR_KELVIN_OFFSET 273 /* TEMP[8:0] - 273 = degC */
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/*
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* i.MX TMU Registers
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*/
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@@ -148,11 +165,37 @@ struct imx_tmu_regs_v3 {
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u32 trim;
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};
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/*
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* fsl,qoriq-tmu (LX2160A, LS1028A, LS1088A, ...). Same TMU IP family as
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* the i.MX "regs_v1" layout but: site-enable is a discrete TMSR at 0x08
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* (TMTMIR moves to 0x0C), and the temperature range registers are
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* variable-length at 0xF10 (a SoC may use fewer than 16). Calibration is
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* taken from the DT (fsl,tmu-range / fsl,tmu-calibration) exactly like
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* the i.MX regs_v1 path, so qoriq reuses imx_tmu_calibration()'s scheme.
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*/
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struct qoriq_tmu_regs {
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u32 tmr; /* 0x000 mode */
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u32 tsr; /* 0x004 status */
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u32 tmsr; /* 0x008 monitor-site enable (bit N = site N) */
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u32 tmtmir; /* 0x00C measurement interval */
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u8 res0[0x10];
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u32 tier; /* 0x020 interrupt enable */
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u32 tidr; /* 0x024 interrupt detect */
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u8 res1[0x58];
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u32 ttcfgr; /* 0x080 temperature config (cal walk) */
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u32 tscfgr; /* 0x084 sensor config (cal walk) */
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u8 res2[0x78];
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struct imx_tmu_site_regs site[SITES_MAX]; /* 0x100 */
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u8 res3[0xd10];
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u32 ttrcr[16]; /* 0xF10 temperature range control */
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};
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union tmu_regs {
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struct imx_tmu_regs regs_v1;
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struct imx_tmu_regs_v2 regs_v2;
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struct imx_tmu_regs_v3 regs_v3;
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struct imx_tmu_regs_v4 regs_v4;
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struct qoriq_tmu_regs regs_qoriq;
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};
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struct imx_tmu_plat {
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@@ -189,6 +232,9 @@ static int read_temperature(struct udevice *dev, int *temp)
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} else if (drv_data & FLAGS_VER4) {
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val = readl(&pdata->regs->regs_v4.tritsr0);
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valid = val & 0x80000000;
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} else if (drv_data & FLAGS_QORIQ) {
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val = readl(&pdata->regs->regs_qoriq.site[pdata->id].tritsr);
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valid = val & TRITSR_V;
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} else {
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val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
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valid = val & 0x80000000;
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@@ -213,6 +259,19 @@ static int read_temperature(struct udevice *dev, int *temp)
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/* Convert Kelvin to Celsius */
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*temp -= 273000;
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} else if (drv_data & FLAGS_QORIQ) {
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/*
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* LX2160A Reference Manual, Rev. 1 (10/2021)
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* section 28.3.1.24: TEMP[8:0] is the calibrated
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* reading in degrees Kelvin (integer, no 0.5 degC
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* bit on the regs_v1 variant). The calibration
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* point examples in the same RM section 28.1.3
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* use the same Kelvin/Celsius offset:
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* TTR0CR=0x800000E6 -> 230K (-43 degC)
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* TTR1CR=0x8001017D -> 381K (108 degC)
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*/
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*temp = ((val & TRITSR_TEMP_MASK) -
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TRITSR_KELVIN_OFFSET) * 1000;
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} else {
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*temp = (val & 0xff) * 1000;
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}
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@@ -265,6 +324,35 @@ static int imx_tmu_calibration(struct udevice *dev)
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if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
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return 0;
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if (drv_data & FLAGS_QORIQ) {
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const fdt32_t *ranges;
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int n;
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ranges = dev_read_prop(dev, "fsl,tmu-range", &len);
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if (!ranges || len % 4 ||
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len / 4 > (int)ARRAY_SIZE(pdata->regs->regs_qoriq.ttrcr)) {
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dev_err(dev, "TMU: missing/invalid fsl,tmu-range\n");
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return -ENODEV;
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}
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n = len / 4;
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for (i = 0; i < n; i++)
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writel(fdt32_to_cpu(ranges[i]),
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&pdata->regs->regs_qoriq.ttrcr[i]);
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calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
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if (!calibration || len % 8) {
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dev_err(dev, "TMU: invalid calibration data.\n");
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return -ENODEV;
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}
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for (i = 0; i < len; i += 8, calibration += 2) {
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writel(fdt32_to_cpu(*calibration),
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&pdata->regs->regs_qoriq.ttcfgr);
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writel(fdt32_to_cpu(*(calibration + 1)),
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&pdata->regs->regs_qoriq.tscfgr);
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}
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return 0;
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}
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if (drv_data & FLAGS_VER4) {
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calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
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if (!calibration || len % 8 || len > 128) {
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@@ -402,6 +490,18 @@ static inline void imx_tmu_mx8mq_init(struct udevice *dev) { }
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static void imx_tmu_arch_init(struct udevice *dev)
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{
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/*
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* QorIQ takes its calibration from the DT (fsl,tmu-calibration),
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* not from OCOTP fuses, so it has no per-SoC arch init. The #if
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* below is still required: the i.MX SoC-ID helpers and fuse API
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* (<asm/arch/sys_proto.h>) do not exist in a Layerscape build, so
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* the references must be removed at compile time, not merely
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* skipped at runtime.
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*/
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if (dev_get_driver_data(dev) & FLAGS_QORIQ)
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return;
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#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93)
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if (is_imx8mm() || is_imx8mn())
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imx_tmu_mx8mm_mx8mn_init(dev);
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else if (is_imx8mp())
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@@ -412,6 +512,7 @@ static void imx_tmu_arch_init(struct udevice *dev)
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imx_tmu_mx8mq_init(dev);
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else
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dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n");
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#endif
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}
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static void imx_tmu_init(struct udevice *dev)
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@@ -443,6 +544,15 @@ static void imx_tmu_init(struct udevice *dev)
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/* Set update_interval */
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writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir);
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} else if (drv_data & FLAGS_QORIQ) {
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/* Disable monitoring */
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writel(TMR_DISABLE, &pdata->regs->regs_qoriq.tmr);
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/* Disable interrupt, using polling instead */
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writel(TIER_DISABLE, &pdata->regs->regs_qoriq.tier);
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/* Set update_interval */
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writel(TMTMIR_DEFAULT, &pdata->regs->regs_qoriq.tmtmir);
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} else {
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/* Disable monitoring */
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writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr);
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@@ -511,6 +621,18 @@ static int imx_tmu_enable_msite(struct udevice *dev)
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/* Enable ME */
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reg |= TMR_ME;
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writel(reg, &pdata->regs->regs_v4.tmr);
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} else if (drv_data & FLAGS_QORIQ) {
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/* Clear ME, enable every site at once via the discrete TMSR */
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reg = readl(&pdata->regs->regs_qoriq.tmr);
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reg &= ~TMR_ME;
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writel(reg, &pdata->regs->regs_qoriq.tmr);
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writel(GENMASK(SITES_MAX - 1, 0),
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&pdata->regs->regs_qoriq.tmsr);
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reg |= QORIQ_TMR_ALPF;
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reg |= TMR_ME;
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writel(reg, &pdata->regs->regs_qoriq.tmr);
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} else {
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/* Clear the ME before setting MSITE and ALPF*/
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reg = readl(&pdata->regs->regs_v1.tmr);
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@@ -650,6 +772,7 @@ static const struct udevice_id imx_tmu_ids[] = {
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{ .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
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{ .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, },
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{ .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, },
|
||||
{ .compatible = "fsl,qoriq-tmu", .data = FLAGS_QORIQ, },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user