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clk: starfive: jh7110: Add security clocks

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Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Chanho Park
2023-11-01 21:16:49 +09:00
committed by Leo Yu-Chi Liang
parent 83b443df26
commit 88af85cf92
1 changed files with 10 additions and 0 deletions
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10
drivers/clk/starfive/clk-jh7110.c
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@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
"pcie1_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE1_TL)));
/* Security clocks */
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
starfive_clk_gate(priv->reg,
"sec_ahb", "stg_axiahb",
OFFSET(JH7110_STGCLK_SEC_HCLK)));
clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
starfive_clk_gate(priv->reg,
"sec_misc_ahb", "stg_axiahb",
OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
return 0;
}