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clk: ti: clk-k3: Notify AVS driver upon setting clock rate
AVS is enabled at R5 SPL stage, on few platforms like J721E and J7200 clk-k3 is used instead if clk-sci driver. Add support in clk-k3 driver as well to notify AVS driver on setting clock rate so that voltage is changed accordingly. Cc: Keerthy <j-keerthy@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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@@ -11,6 +11,7 @@
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#include <errno.h>
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#include <soc.h>
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#include <clk-uclass.h>
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#include <k3-avs.h>
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#include "k3-clk.h"
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#define PLL_MIN_FREQ 800000000
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@@ -242,7 +243,11 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
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const struct clk_ops *ops;
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ulong new_rate, rem;
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ulong diff, new_diff;
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int freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0;
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if (IS_ENABLED(CONFIG_K3_AVS0) && freq_scale_up)
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k3_avs_notify_freq(data->map[clk->id].dev_id,
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data->map[clk->id].clk_id, rate);
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/*
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* We must propagate rate change to parent if current clock type
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* does not allow setting it.
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@@ -339,6 +344,10 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
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}
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}
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if (IS_ENABLED(CONFIG_K3_AVS0) && !freq_scale_up)
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k3_avs_notify_freq(data->map[clk->id].dev_id,
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data->map[clk->id].clk_id, rate);
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return new_rate;
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}
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