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arm: dts: mediatek: Add MediaTek MT8189 dtsi file
Add a basic .dtsi file for MediaTek MT8189. This will suffice until an upstream devicetree is available from Linux. Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com> Reviewed-by: Julien Stephan <jstephan@baylibre.com> Link: https://patch.msgid.link/20260323-mtk-mt8391-initial-support-v3-4-19dd92f4543f@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
Chris-QJ Chen
committed by
David Lechner
David Lechner
parent
8dfbebc31c
commit
8971055fe4
301
arch/arm/dts/mt8189.dtsi
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301
arch/arm/dts/mt8189.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2026 MediaTek Inc.
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* Author: Macpaul Lin <macpaul.lin@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8189-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8189";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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clk26m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x000>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <282>;
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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};
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memory: memory@40000000 {
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device_type = "memory";
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/* This memory size is filled in by the bootloader */
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reg = <0 0x40000000 0 0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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watchdog: watchdog@1c00a000 {
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compatible = "mediatek,mt8391-wdt",
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"mediatek,wdt";
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reg = <0 0x1c00a000 0 0x100>;
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status = "disabled";
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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reg = <0 0xc000000 0 0x40000>, /* distributor */
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<0 0xc040000 0 0x200000>; /* redistributor */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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#redistributor-regions = <1>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu6 &cpu7>;
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};
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};
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};
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uart0: serial@11001000 {
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compatible = "mediatek,mt8189-uart", "mediatek,mt6577-uart";
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reg = <0 0x11001000 0 0x1000>;
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interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8189-mmc";
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reg = <0 0x11230000 0 0x10000>,
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<0 0x11e70000 0 0x1000>;
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clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
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<&pericfg_ao_clk CLK_PERAO_MSDC0_H>,
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<&pericfg_ao_clk CLK_PERAO_MSDC0>;
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clock-names = "source", "hclk", "source_cg";
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interrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;
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status = "disabled";
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};
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clock-controller@1000c000 {
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compatible = "mediatek,mt8189-apmixedsys", "syscon";
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reg = <0 0x1000c000 0 0x1000>;
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#clock-cells = <1>;
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};
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clock-controller@14000000 {
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compatible = "mediatek,mt8189-dispsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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clock-controller@1e980000 {
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compatible = "mediatek,mt8189-gce-d", "syscon";
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reg = <0 0x1e980000 0 0x1000>;
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#clock-cells = <1>;
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};
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clock-controller@1e990000 {
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compatible = "mediatek,mt8189-gce-m", "syscon";
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reg = <0 0x1e990000 0 0x1000>;
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#clock-cells = <1>;
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};
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clock-controller@1e800000 {
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compatible = "mediatek,mt8189-mm-infra", "syscon";
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reg = <0 0x1e800000 0 0x1000>;
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#clock-cells = <1>;
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};
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pericfg_ao_clk: clock-controller@11036000 {
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compatible = "mediatek,mt8189-peri-ao", "syscon";
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reg = <0 0x11036000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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topckgen_clk: clock-controller@10000000 {
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compatible = "mediatek,mt8189-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8189-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11b50000 0 0x1000>,
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<0 0x11c50000 0 0x1000>,
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<0 0x11c60000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11d30000 0 0x1000>,
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<0 0x11d40000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e30000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11ce0000 0 0x1000>,
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<0 0x11de0000 0 0x1000>,
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<0 0x11e60000 0 0x1000>,
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<0 0x1c01e000 0 0x1000>,
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<0 0x11f00000 0 0x1000>;
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reg-names = "base",
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"lm",
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"rb0",
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"rb1",
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"bm0",
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"bm1",
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"bm2",
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"lt0",
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"lt1",
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"rt",
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"eint0",
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"eint1",
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"eint2",
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"eint3",
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"eint4";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 182>;
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interrupt-controller;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
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#interrupt-cells = <2>;
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};
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pwrap: pwrap@1cc04000 {
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compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon";
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reg = <0 0x1cc04000 0 0x1000>;
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reg-names = "pwrap";
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assigned-clocks = <&vlpckgen_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>;
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assigned-clock-parents = <&topckgen_clk CLK_TOP_OSC_D10>;
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clocks = <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>,
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<&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>;
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clock-names = "spi", "wrap";
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interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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vlpcfg_ao_clk: clock-controller@1c00c000 {
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compatible = "mediatek,mt8189-vlpcfg-ao", "syscon";
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reg = <0 0x1c00c000 0 0x1000>;
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#clock-cells = <1>;
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};
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vlpckgen_clk: clock-controller@1c012000 {
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compatible = "mediatek,mt8189-vlpckgen", "syscon";
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reg = <0 0x1c012000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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};
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