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riscv: mbv: Align addresses with default DT

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Better to align everything with memory map described in DT to avoid
mistakes. Execute both modes form the same address to make address map more
understandable.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/be54c668d5626ccd702507a86c2a95d1eaefc690.1707911544.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2024-02-14 12:52:29 +01:00
parent 11f54dff30
commit 8ef750872e
3 changed files with 3 additions and 6 deletions
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3
board/xilinx/mbv/Kconfig
View File

@@ -13,8 +13,7 @@ config SYS_CONFIG_NAME
default "xilinx_mbv"
config TEXT_BASE
default 0x80000000 if !RISCV_SMODE
default 0x80400000 if RISCV_SMODE && ARCH_RV32I
default 0x21200000
config BOARD_SPECIFIC_OPTIONS
def_bool y

3
configs/xilinx_mbv32_defconfig
View File

@@ -1,5 +1,4 @@
CONFIG_RISCV=y
CONFIG_TEXT_BASE=0x21200000
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_DEBUG_UART=y
CONFIG_TARGET_XILINX_MBV=y
CONFIG_FIT=y

3
configs/xilinx_mbv32_smode_defconfig
View File

@@ -1,5 +1,4 @@
CONFIG_RISCV=y
CONFIG_TEXT_BASE=0x21200000
CONFIG_SYS_MALLOC_LEN=0x800000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_TARGET_XILINX_MBV=y
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y