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arm64: zynqmp: versal: Consistently use enum tcm_mode

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Turn anonymous enum TCM_LOCK/TCM_SPLIT into enum tcm_mode {}, set
TCM_LOCK as 0 and TCM_SPLIT as 1 to match LOCK and SPLIT macros in
mach-zynqmp/mp.c, and unify all the functions and their parameters
on this one single enum tcm_mode {} instead of a mix of bool and u8.
No functional change intended.

Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Love Kumar <love.kumar@amd.com>
Link: https://lore.kernel.org/r/20250206213039.42756-1-marex@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Marek Vasut
2025-02-06 22:29:36 +01:00
committed by Michal Simek
parent 3ecf1b78d9
commit 931d96b594
6 changed files with 58 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/mach-versal/include/mach/sys_proto.h
View File

@@ -5,11 +5,11 @@
#include <linux/build_bug.h>
enum {
TCM_LOCK,
TCM_SPLIT,
enum tcm_mode {
TCM_LOCK = 0,
TCM_SPLIT = 1,
};
void initialize_tcm(bool mode);
void tcm_init(u8 mode);
void initialize_tcm(enum tcm_mode mode);
void tcm_init(enum tcm_mode mode);
void mem_map_fill(void);

12
arch/arm/mach-versal/mp.c
View File

@@ -24,7 +24,7 @@
#define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10
#define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
static void set_r5_halt_mode(u8 halt, u8 mode)
static void set_r5_halt_mode(u8 halt, enum tcm_mode mode)
{
u32 tmp;
@@ -45,7 +45,7 @@ static void set_r5_halt_mode(u8 halt, u8 mode)
}
}
static void set_r5_tcm_mode(u8 mode)
static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
@@ -63,7 +63,7 @@ static void set_r5_tcm_mode(u8 mode)
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
static void release_r5_reset(u8 mode)
static void release_r5_reset(enum tcm_mode mode)
{
u32 tmp;
@@ -87,9 +87,9 @@ static void enable_clock_r5(void)
writel(tmp, &crlapb_base->cpu_r5_ctrl);
}
void initialize_tcm(bool mode)
void initialize_tcm(enum tcm_mode mode)
{
if (!mode) {
if (mode == TCM_LOCK) {
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(HALT, TCM_LOCK);
enable_clock_r5();
@@ -102,7 +102,7 @@ void initialize_tcm(bool mode)
}
}
void tcm_init(u8 mode)
void tcm_init(enum tcm_mode mode)
{
puts("WARNING: Initializing TCM overwrites TCM content\n");
initialize_tcm(mode);

2
arch/arm/mach-zynqmp/cpu.c
View File

@@ -113,7 +113,7 @@ u64 get_page_table_size(void)
}
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(u8 mode)
void tcm_init(enum tcm_mode mode)
{
int ret;

12
arch/arm/mach-zynqmp/include/mach/sys_proto.h
View File

@@ -41,18 +41,18 @@ enum {
ZYNQMP_SILICON_V4,
};
enum {
TCM_LOCK,
TCM_SPLIT,
enum tcm_mode {
TCM_LOCK = 0,
TCM_SPLIT = 1,
};
unsigned int zynqmp_get_silicon_version(void);
int check_tcm_mode(bool mode);
void initialize_tcm(bool mode);
int check_tcm_mode(enum tcm_mode mode);
void initialize_tcm(enum tcm_mode mode);
void mem_map_fill(void);
#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(u8 mode);
void tcm_init(enum tcm_mode mode);
#endif
#endif /* _ASM_ARCH_SYS_PROTO_H */

81
arch/arm/mach-zynqmp/mp.c
View File

@@ -17,9 +17,6 @@
#include <linux/errno.h>
#include <linux/string.h>
#define LOCK 0
#define SPLIT 1
#define HALT 0
#define RELEASE 1
@@ -65,11 +62,11 @@ int cpu_reset(u32 nr)
return 0;
}
static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
static void set_r5_halt_mode(u32 nr, u8 halt, enum tcm_mode mode)
{
u32 tmp;
if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0) {
tmp = readl(&rpu_base->rpu0_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -78,7 +75,7 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
writel(tmp, &rpu_base->rpu0_cfg);
}
if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1) {
tmp = readl(&rpu_base->rpu1_cfg);
if (halt == HALT)
tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
@@ -88,12 +85,12 @@ static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
}
}
static void set_r5_tcm_mode(u8 mode)
static void set_r5_tcm_mode(enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
if (mode == LOCK) {
if (mode == TCM_LOCK) {
tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
@@ -106,12 +103,12 @@ static void set_r5_tcm_mode(u8 mode)
writel(tmp, &rpu_base->rpu_glbl_ctrl);
}
static void set_r5_reset(u32 nr, u8 mode)
static void set_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
if (mode == LOCK) {
if (mode == TCM_LOCK) {
tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -130,16 +127,16 @@ static void set_r5_reset(u32 nr, u8 mode)
writel(tmp, &crlapb_base->rst_lpd_top);
}
static void release_r5_reset(u32 nr, u8 mode)
static void release_r5_reset(u32 nr, enum tcm_mode mode)
{
u32 tmp;
tmp = readl(&crlapb_base->rst_lpd_top);
if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU0)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
if (mode == TCM_LOCK || nr == ZYNQMP_CORE_RPU1)
tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
@@ -165,9 +162,9 @@ static int check_r5_mode(void)
tmp = readl(&rpu_base->rpu_glbl_ctrl);
if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
return SPLIT;
return TCM_SPLIT;
return LOCK;
return TCM_LOCK;
}
int cpu_disable(u32 nr)
@@ -249,27 +246,27 @@ static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr)
}
}
void initialize_tcm(bool mode)
void initialize_tcm(enum tcm_mode mode)
{
if (!mode) {
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
if (mode == TCM_LOCK) {
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_LOCK);
enable_clock_r5();
release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
release_r5_reset(ZYNQMP_CORE_RPU0, TCM_LOCK);
} else {
set_r5_tcm_mode(SPLIT);
set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT);
set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
set_r5_tcm_mode(TCM_SPLIT);
set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, TCM_SPLIT);
set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, TCM_SPLIT);
enable_clock_r5();
release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT);
release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
release_r5_reset(ZYNQMP_CORE_RPU0, TCM_SPLIT);
release_r5_reset(ZYNQMP_CORE_RPU1, TCM_SPLIT);
}
}
int check_tcm_mode(bool mode)
int check_tcm_mode(enum tcm_mode mode)
{
u32 tmp, cpu_state;
bool mode_prev;
enum tcm_mode mode_prev;
tmp = readl(&rpu_base->rpu_glbl_ctrl);
mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp);
@@ -279,7 +276,7 @@ int check_tcm_mode(bool mode)
ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp);
cpu_state = cpu_state ? false : true;
if ((mode_prev == SPLIT && mode == LOCK) && cpu_state)
if ((mode_prev == TCM_SPLIT && mode == TCM_LOCK) && cpu_state)
return -EACCES;
if (mode_prev == mode)
@@ -288,11 +285,11 @@ int check_tcm_mode(bool mode)
return 0;
}
static void mark_r5_used(u32 nr, u8 mode)
static void mark_r5_used(u32 nr, enum tcm_mode mode)
{
u32 mask = 0;
if (mode == LOCK) {
if (mode == TCM_LOCK) {
mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
} else {
switch (nr) {
@@ -358,30 +355,30 @@ int cpu_release(u32 nr, int argc, char *const argv[])
return 1;
}
printf("R5 lockstep mode\n");
set_r5_reset(nr, LOCK);
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(nr, HALT, LOCK);
set_r5_reset(nr, TCM_LOCK);
set_r5_tcm_mode(TCM_LOCK);
set_r5_halt_mode(nr, HALT, TCM_LOCK);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(nr, LOCK);
release_r5_reset(nr, TCM_LOCK);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
set_r5_halt_mode(nr, RELEASE, LOCK);
mark_r5_used(nr, LOCK);
set_r5_halt_mode(nr, RELEASE, TCM_LOCK);
mark_r5_used(nr, TCM_LOCK);
} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
printf("R5 split mode\n");
set_r5_reset(nr, SPLIT);
set_r5_tcm_mode(SPLIT);
set_r5_halt_mode(nr, HALT, SPLIT);
set_r5_reset(nr, TCM_SPLIT);
set_r5_tcm_mode(TCM_SPLIT);
set_r5_halt_mode(nr, HALT, TCM_SPLIT);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(nr, SPLIT);
release_r5_reset(nr, TCM_SPLIT);
dcache_disable();
write_tcm_boot_trampoline(nr, boot_addr_uniq);
dcache_enable();
set_r5_halt_mode(nr, RELEASE, SPLIT);
mark_r5_used(nr, SPLIT);
set_r5_halt_mode(nr, RELEASE, TCM_SPLIT);
mark_r5_used(nr, TCM_SPLIT);
} else {
printf("Unsupported mode\n");
return 1;

2
arch/arm/mach-zynqmp/zynqmp.c
View File

@@ -146,7 +146,7 @@ static int do_zynqmp_aes(struct cmd_tbl *cmdtp, int flag, int argc,
static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
u8 mode;
enum tcm_mode mode;
if (argc != cmdtp->maxargs)
return CMD_RET_USAGE;