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pci: pcie-rcar-gen4: Fix PHY initialization

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R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025
page 4581 Figure 104.3b Initial Setting of PCIEC(example) middle
of the figure indicates that fourth write into register 0x148 [2:0]
is 0x3 or GENMASK(1, 0). The current code writes GENMASK(11, 0)
which is a typo. Fix the typo.

Fixes: be3dd0dc2f ("pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2025-08-06 21:23:54 +02:00
parent 0c558bbad9
commit 93297f1f9b
1 changed files with 1 additions and 1 deletions
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2
drivers/pci/pci-rcar-gen4.c
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@@ -235,7 +235,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable
clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(23, 22), BIT(22));
clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(18, 16), GENMASK(17, 16));
clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(7, 6), BIT(6));
clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(11, 0));
clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(1, 0));
clrsetbits_le32(rcar->phy_base + 0x1d4, GENMASK(16, 15), GENMASK(16, 15));
clrsetbits_le32(rcar->phy_base + 0x514, BIT(26), BIT(26));
clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(16), 0);