dts: msm8996: replace with upstream DTS

Drop the U-Boot specific dragonboard820c.dts file in favour of the
upstream apq8096-db820c.dts and an additional -u-boot.dtsi with the
U-Boot specific additions.

Taken from kernel tag v6.7

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly
2024-02-26 17:26:40 +00:00
parent 5566bb4476
commit 93441fc3b5
7 changed files with 5037 additions and 187 deletions

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@@ -625,7 +625,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
dragonboard820c.dtb \
apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb.dtb

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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024, Linaro Ltd.
*/
/ {
/* Ensure that the fdtfile variable is generated properly */
compatible = "qcom,apq8096-db820c", "qcom,apq8096";
};
&sdhc2 {
status = "okay";
clock-frequency = <100000000>;
};

File diff suppressed because it is too large Load Diff

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@@ -1,32 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot addition to handle Dragonboard 820c pins
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/ {
smem {
bootph-all;
};
soc {
bootph-all;
pinctrl@1010000 {
bootph-all;
uart {
bootph-all;
};
};
clock-controller@300000 {
bootph-all;
};
serial@75b0000 {
bootph-all;
};
};
};

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@@ -1,153 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Qualcomm APQ8096 based Dragonboard 820C board device tree source
*
* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
*/
/dts-v1/;
#include "skeleton64.dtsi"
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &blsp2_uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0 0x80000000 0 0xc0000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@86300000 {
reg = <0x0 0x86300000 0x0 0x200000>;
no-map;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x300000 0x90000>;
};
pinctrl: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x1010000 0x400000>;
blsp8_uart: uart {
function = "blsp_uart8";
pins = "GPIO_4", "GPIO_5";
drive-strength = <8>;
bias-disable;
};
};
blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>;
clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <&blsp8_uart>;
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
clock = <&gcc GCC_SDCC1_APPS_CLK>;
clock-frequency = <200000000>;
};
spmi_bus: spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
#address-cells = <0x1>;
#size-cells = <0x1>;
pmic0: pm8994@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800 0x100>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
debounce = <15625>;
bias-pull-up;
};
pm8994_resin: resin {
compatible = "qcom,pm8941-resin";
debounce = <15625>;
bias-pull-up;
};
};
pm8994_gpios: pm8994_gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000 0x400>;
gpio-controller;
gpio-ranges = <&pm8994_gpios 0 0 22>;
#gpio-cells = <2>;
};
};
pmic1: pm8994@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 0x1>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
};
};
#include "dragonboard820c-uboot.dtsi"

3884
arch/arm/dts/msm8996.dtsi Normal file

File diff suppressed because it is too large Load Diff

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@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x804000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0
CONFIG_ENV_SIZE=0x4000
CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c"
CONFIG_DEFAULT_DEVICE_TREE="apq8096-db820c"
CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C"
CONFIG_SYS_LOAD_ADDR=0x80080000
CONFIG_DISTRO_DEFAULTS=y