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arm64: dts: rockchip: add rk3576 otp node

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This adds the otp node to the rk3576 soc devicetree including the
individual fields we know about.

Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de

[ upstream commit: 8715d2eeb062f6859c252bb6c87b363230b66e9f ]

(cherry picked from commit d67cf6de8aacb4abcdfb516eeb8a511a4a657bc1)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stuebner
2025-04-15 23:51:25 +02:00
committed by Kever Yang
parent ed71874a73
commit 945711c6a3
1 changed files with 39 additions and 0 deletions
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39
dts/upstream/src/arm64/rockchip/rk3576.dtsi
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@@ -1260,6 +1260,45 @@
status = "disabled";
};
otp: otp@2a580000 {
compatible = "rockchip,rk3576-otp";
reg = <0x0 0x2a580000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
<&cru CLK_OTP_PHY_G>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
reset-names = "otp", "apb";
/* Data cells */
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
};
otp_cpu_version: cpu-version@5 {
reg = <0x05 0x1>;
bits = <3 3>;
};
otp_id: id@a {
reg = <0x0a 0x10>;
};
cpub_leakage: cpub-leakage@1e {
reg = <0x1e 0x1>;
};
cpul_leakage: cpul-leakage@1f {
reg = <0x1f 0x1>;
};
npu_leakage: npu-leakage@20 {
reg = <0x20 0x1>;
};
gpu_leakage: gpu-leakage@21 {
reg = <0x21 0x1>;
};
log_leakage: log-leakage@22 {
reg = <0x22 0x1>;
};
};
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,