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Merge tag 'xilinx-for-v2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

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AMD/Xilinx/FPGA changes for v2026.07-rc3

versal/fpga:
- Fix unaligned buffer handling

versal2:
- Fix buffer overflow in SOC name array
This commit is contained in:
Tom Rini
2026-05-25 09:43:44 -06:00
parent ba932756ca 8a5989acc6
commit 97208cb762
2 changed files with 6 additions and 5 deletions
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9
board/amd/versal2/board.c
View File

@@ -81,12 +81,13 @@ char *soc_name_decode(void)
}
/*
* --rev. are 6 chars
* max platform name is qemu which is 4 chars
* --rev.-el are 9 chars
* max platform name is emu-mmd which is 7 chars
* platform version number are 1+1
* Plus 1 char for \n
* el is 1 char
* Plus 1 char for NULL byte
*/
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20);
if (!name)
return NULL;

2
drivers/fpga/versalpl.c
View File

@@ -17,7 +17,7 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len)
if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
memcpy(new_buf, buf, len);
memmove(new_buf, buf, len);
buf = new_buf;
}