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clk: mediatek: mt7981: convert to unified infracfg gates + muxes

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Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
2024-08-02 15:53:14 +02:00
committed by Tom Rini
parent 2d20cc4064
commit 99da5bbd80
2 changed files with 22 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
arch/arm/dts/mt7981.dtsi
View File

@@ -98,14 +98,6 @@
bootph-all;
};
infracfg_ao: infracfg_ao@10001000 {
compatible = "mediatek,mt7981-infracfg_ao";
reg = <0x10001000 0x80>;
clock-parent = <&infracfg>;
#clock-cells = <1>;
bootph-all;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg";
reg = <0x10001000 0x30>;
@@ -141,10 +133,10 @@
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_PWM_SEL>,
<&infracfg_ao CK_INFRA_PWM_BSEL>,
<&infracfg_ao CK_INFRA_PWM1_CK>,
<&infracfg_ao CK_INFRA_PWM2_CK>,
<&infracfg_ao CK_INFRA_PWM3_CK>;
<&infracfg CK_INFRA_PWM_BSEL>,
<&infracfg CK_INFRA_PWM1_CK>,
<&infracfg CK_INFRA_PWM2_CK>,
<&infracfg CK_INFRA_PWM3_CK>;
assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
@@ -157,8 +149,8 @@
<0x10217080 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
clocks = <&infracfg_ao CK_INFRA_I2C0_CK>,
<&infracfg_ao CK_INFRA_AP_DMA_CK>;
clocks = <&infracfg CK_INFRA_I2C0_CK>,
<&infracfg CK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -169,9 +161,9 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
clocks = <&infracfg CK_INFRA_UART0_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART0_SEL>;
<&infracfg CK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&topckgen CK_TOP_UART_SEL>;
mediatek,force-highspeed;
@@ -183,9 +175,9 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
clocks = <&infracfg CK_INFRA_UART1_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART1_SEL>;
<&infracfg CK_INFRA_UART1_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&topckgen CK_TOP_UART_SEL>;
mediatek,force-highspeed;
@@ -196,9 +188,9 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
clocks = <&infracfg CK_INFRA_UART2_CK>;
assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
<&infracfg_ao CK_INFRA_UART2_SEL>;
<&infracfg CK_INFRA_UART2_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
<&topckgen CK_TOP_UART_SEL>;
mediatek,force-highspeed;
@@ -210,9 +202,9 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
<&infracfg_ao CK_INFRA_NFI1_CK>,
<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
clocks = <&infracfg CK_INFRA_SPINFI1_CK>,
<&infracfg CK_INFRA_NFI1_CK>,
<&infracfg CK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
<&topckgen CK_TOP_NFI1X_SEL>;
@@ -264,7 +256,7 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
clocks = <&infracfg CK_INFRA_SPI0_CK>,
<&topckgen CK_TOP_SPI_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
<&infracfg CK_INFRA_SPI0_SEL>;
@@ -279,7 +271,7 @@
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg_ao CK_INFRA_SPI1_CK>,
clocks = <&infracfg CK_INFRA_SPI1_CK>,
<&topckgen CK_TOP_SPIM_MST_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPIM_MST_SEL>,
<&infracfg CK_INFRA_SPI1_SEL>;
@@ -292,7 +284,7 @@
spi2: spi@11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
clocks = <&infracfg_ao CK_INFRA_SPI2_CK>,
clocks = <&infracfg CK_INFRA_SPI2_CK>,
<&topckgen CK_TOP_SPI_SEL>;
assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
<&infracfg CK_INFRA_SPI2_SEL>;
@@ -310,7 +302,7 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CK_TOP_EMMC_400M>,
<&topckgen CK_TOP_EMMC_208M>,
<&infracfg_ao CK_INFRA_MSDC_CK>;
<&infracfg CK_INFRA_MSDC_CK>;
assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
<&topckgen CK_TOP_EMMC_208M_SEL>;
assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,

26
drivers/clk/mediatek/clk-mt7981.c
View File

@@ -441,7 +441,7 @@ static const struct mtk_gate_regs infra_2_cg_regs = {
GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
/* INFRA GATE */
static const struct mtk_gate infracfg_ao_gates[] = {
static const struct mtk_gate infracfg_gates[] = {
GATE_INFRA0_INFRA(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
GATE_INFRA0_INFRA(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
GATE_INFRA0_INFRA(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BSEL, 2),
@@ -529,6 +529,7 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
.gates_offs = CK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
.flags = CLK_INFRASYS,
};
@@ -583,20 +584,9 @@ static const struct udevice_id mt7981_infracfg_compat[] = {
{}
};
static const struct udevice_id mt7981_infracfg_ao_compat[] = {
{ .compatible = "mediatek,mt7981-infracfg_ao" },
{}
};
static int mt7981_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
}
static int mt7981_infracfg_ao_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
infracfg_ao_gates);
return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree);
}
U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -609,16 +599,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
.name = "mt7981-clock-infracfg-ao",
.id = UCLASS_CLK,
.of_match = mt7981_infracfg_ao_compat,
.probe = mt7981_infracfg_ao_probe,
.priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
/* sgmiisys */
static const struct mtk_gate_regs sgmii_cg_regs = {
.set_ofs = 0xe4,